TWI665805B - Electrostatic discharge protection apparatus and applications thereof - Google Patents

Abstract

An electrostatic discharge protection device includes a first bipolar transistor parasitic circuit and a second bipolar transistor parasitic circuit formed in a substrate and having different majority carriers, and an electrostatic discharge protection element. The electrostatic discharge protection element has a ground terminal and a connection terminal connected to the first bipolar transistor parasitic circuit. When the electrostatic discharge voltage is greater than the ground voltage, the first current passes through the first protection circuit combination including the parasitic diode in the first bipolar transistor parasitic circuit and the electrostatic discharge protection element, and the first bipolar transistor parasitic circuit. One of them combined with the second protection circuit of the second bipolar transistor parasitic circuit is introduced into the ground. When the electrostatic discharge voltage is less than the ground voltage, the second current is introduced into the voltage source from the ground through the other of the first protection circuit combination and the second protection circuit combination.

Description

Electrostatic discharge protection device and its application

This disclosure relates to a semiconductor circuit and its application. In particular, it relates to an electrostatic discharge (ESD) protection device and its application.

Electrostatic discharge is a phenomenon of electrostatic charge accumulation and transfer between different objects. In a very short time, usually only a few nanoseconds, a very high-energy, high-density current is generated. Once flowing through a semiconductor device, the semiconductor device is usually damaged. Therefore, when an electrostatic charge is generated in a semiconductor device by a machine or a human body, an electrostatic discharge protection device and a discharge path must be provided to prevent the semiconductor device from being damaged.

Taking an electrostatic discharge protection structure that is widely used between an input / output (I / O) pad of an integrated circuit and an internal circuit as an example, it utilizes a parasitic doubler built in the integrated circuit Bipolar junction transistor (BJT) and / or other electrostatic discharge protection components, such as metal-oxide-semiconductor (Metal-Oxide-Semiconductor, MOS) transistors, constitute an electrostatic discharge protection circuit to protect the internal circuit Protected against electrostatic discharge currents introduced by the input / output pads. In order to improve the trigger voltage (Trigger Voltage, Vtr) and holding voltage (Vh) of the electrostatic discharge protection circuit, in order to improve the current shunting capability of the electrostatic discharge protection circuit, the input / output pad and static electricity are generally used. At least one diode element connected in series is arranged between the discharge protection circuits.

However, the arrangement of the diode element will block the reverse electrostatic discharge current, which may damage the internal circuit and the electric discharge protection circuit. Therefore, another electrostatic discharge circuit must be additionally provided to disperse reverse electrostatic discharge current. However, this will prevent the overall layout size of the integrated circuit from being reduced, which is not in line with the design trend of the size reduction of the integrated circuit.

Therefore, there is a need to provide an advanced electrostatic discharge protection device and its application to solve the problems faced by the conventional technology.

An embodiment of the present specification discloses an electrostatic discharge protection device including a semiconductor substrate, a first doped well region, a second doped well region, a first doped region, a second doped region, a third doped region, A fourth doped region and an electrostatic discharge protection element. The first doped well region is located in the semiconductor substrate. The second doped well region is located in the first doped well region. The first doped region and the second doped region are respectively located in the second doped well region, are isolated from each other, and are respectively connected to a voltage source. The third doped region is located in the first doped well region. The fourth doped region is located in the semiconductor substrate, is adjacent to the first doped well region, and is grounded. The first doped region, the second doped well region, and the first doped well region form a first bipolar transistor parasitic (BJT) circuit; the second doped region, the first doped well region, and The fourth doped region forms a second bipolar transistor parasitic circuit; and the first bipolar transistor parasitic circuit and the second bipolar transistor parasitic circuit have different majority carriers. The electrostatic discharge protection element has a ground terminal and a connection terminal connected to the third doped region. When the voltage source is greater than the ground voltage, the first current passes through a first protection circuit combination including a parasitic diode in the first bipolar transistor parasitic circuit and an electrostatic discharge protection element, and a first bipolar transistor parasitic circuit and A second protection circuit combination of the second bipolar transistor parasitic circuit is introduced into the ground. When the voltage source is less than the ground voltage, the second current is introduced into the voltage source from the ground through the other of the first protection circuit combination and the second protection circuit combination.

Another embodiment of the present disclosure discloses a memory device including the electrostatic discharge protection device as described above and a memory cell array electrically connected to the electrostatic discharge protection device.

Another embodiment of the present specification discloses an electrostatic discharge protection method to protect an internal circuit electrical connection. The method includes the following steps: First, the electrostatic discharge protection device described above is electrically connected to the internal circuit. . When the electrostatic discharge stress (ESD stress) applied to the internal circuit is greater than the ground voltage, a first protection circuit combination including a parasitic diode in a first bipolar transistor parasitic circuit and an electrostatic discharge protection element and a first protection circuit The bipolar transistor parasitic circuit and the second protection circuit of the second bipolar transistor parasitic circuit combine one of the two to direct the first electrostatic discharge current to the ground; when the electrostatic discharge stress applied to the internal circuit is less than the ground voltage, The other of the first protection circuit combination and the second protection circuit combination is used to introduce a second electrostatic discharge current from the ground to a voltage source that applies an electrostatic discharge stress.

According to the above embodiments, this specification is to provide an electrostatic discharge protection device and an application thereof. At least one bipolar transistor parasitic circuit is formed on a semiconductor substrate by means of ion doping to form a reverse-triggering ) Parasitic Silicon Controlled Rectifier (SCR). It is then electrically connected to an internal circuit with another forward ESD protection element. When electrostatic discharge stress is applied to the internal circuit, the forward electrostatic discharge current can be directed to the ground by using the electrostatic discharge protection element in the forward direction; or the reverse electrostatic discharge current can be directed from the ground to apply static electricity through the reverse parasitic silicon controlled rectifier. Voltage source for discharge stress.

Among them, the "inverted parasitic silicon controlled rectifier" uses a doped well region with an N-type dopant as the base, and contains a parasitic circuit with two bipolar transistors of electrical conductivity PNP and NPN. The doped region with a type dopant is used as a ground terminal, and the doped region with an N-type dopant is electrically connected to the protected internal circuit. Because the conventional reverse electrostatic discharge path is generally the P pole is grounded, and the N pole is connected to the PN parasitic diode of the internal circuit. When the electrostatic discharge stress makes the operating voltage of the internal circuit lower than the ground, the reverse path will occur. Large leakage current. The parasitic silicon controlled rectifier provided in the foregoing embodiment is used to replace the conventional PN parasitic diode to solve the problem that a large amount of leakage current is generated when the operating voltage of the internal circuit is lower than the ground.

In another embodiment of the present specification, a forward-triggering parasitic silicon-controlled rectifier and another reverse electrostatic discharge protection element may be matched to be electrically connected to the internal circuit. When electrostatic discharge stress is applied to the internal circuit, reverse electrostatic discharge protection elements can be used to direct reverse electrostatic discharge current from the ground to a voltage source that applies electrostatic discharge stress; or forward parasitic silicon-controlled rectifiers The electrostatic discharge current is conducted to the ground. It is not necessary to additionally provide another electrostatic discharge protection element occupying a large layout space, and the purpose of simultaneously dispersing the forward and reverse electrostatic discharge currents and reducing the overall layout size of the integrated circuit can be achieved. Among them, the "forward parasitic silicon controlled rectifier" uses a doped well region with a P-type dopant as the base, and a parasitic circuit containing two bipolar transistors of electrical conductivity PNP and NPN, respectively. The doped region of a type dopant is used as a ground terminal, and the doped region with a P type dopant is electrically connected to the internal circuit.

In order to have a better understanding of the above and other aspects of this specification, the following specific examples are described in detail below in conjunction with the drawings:

This specification provides an electrostatic discharge protection device and its application, which can simultaneously disperse forward and reverse electrostatic discharge currents, and achieve the purpose of reducing the overall layout size of integrated circuits and negative voltage operation. In order to make the above-mentioned embodiments and other objects, features, and advantages of this specification more comprehensible, a plurality of electrostatic discharge protection devices and their application devices and methods are given below as preferred embodiments, and described in detail in conjunction with the attached drawings. .

It must be noted that these specific implementation cases and methods are not intended to limit the present invention. The invention can still be implemented with other features, elements, methods and parameters. The proposal of the preferred embodiment is only used to illustrate the technical features of the present invention, and is not intended to limit the scope of patent application of the present invention. Those with ordinary knowledge in the technical field can make equal modifications and changes according to the description of the following description without departing from the spirit of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

Please refer to FIG. 1. FIG. 1 is a schematic structural cross-sectional view and an equivalent circuit diagram of the electrostatic discharge protection device 100 according to an embodiment of the present specification. In this embodiment, the ESD protection device 100 includes a semiconductor substrate 101, a first doped well region 102, a second doped well region 103, a first doped region 104, a second doped region 105, and a third The doped region 106, the fourth doped region 107, the bonding pad 108, and an ESD protection element 109.

The first doped well region 102 is located in the semiconductor substrate 101. The second doped well region 103 is located in the first doped well region 102. The first doped region 104 and the second doped region 105 are respectively located in the second doped well region 103, and both are electrically connected to a voltage source 116 through the bonding pad 108. The third doped region 106 is located in the first doped well region 102. The fourth doped region 107 is located in the semiconductor substrate 101, is adjacent to the first doped well region 102, and is grounded. In this embodiment, the fourth doped region 107 may (but is not limited to) surrounding the first doped well region 102.

In some embodiments of the present specification, the semiconductor substrate 101 may be made of any suitable base semiconductor, such as crystalline silicon or germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, iodine phosphide, arsenic Iodine and / or antimony iodide, or a combination thereof. For example, in this embodiment, the semiconductor substrate 101 is preferably a polycrystalline silicon wafer.

In this embodiment, the semiconductor substrate 101 having the first property may include a doped well region (represented by P-well) having a P-type dopant. The P-type dopant may be, for example, aluminum (Al), boron (B), gallium (Ga), or any combination thereof. The first doped well region 102 is a deep-doped well region (N-well) with N-type dopants, such as arsenic (As) and phosphorus (P) ions; the second doped well region 103 has P Type doped well region (PWI). The first doped region 104 and the third doped region 106 are N-type doped regions (N +) having an N-type dopant concentration higher than that of the second doped well region 103; the second doped region 105 and the fourth doped region The region 107 is a P-type doped region (P +) having a P-type dopant concentration higher than that of the first doped well region 102.

The first doped region 104, the second doped well region 103, and the first doped well region 102 form an NPN bipolar transistor parasitic circuit 110A having an N-type majority carrier; the fourth doped region 107, the first A doped well region 102 and a second doped region 105 form a second bipolar transistor parasitic circuit 110B; and the first bipolar transistor parasitic circuit 110A and the second bipolar transistor parasitic circuit 110B have different majority loads. child. The collector of the PNP bipolar transistor parasitic circuit 110B is connected to the base of the NPN bipolar transistor parasitic circuit 110A; and the base of the PNP bipolar transistor parasitic circuit 110B and the NPN bipolar transistor The collector of the crystal parasitic circuit 110A is connected to form a parasitic silicon controlled rectifier 110 in the semiconductor substrate 101. The first doped region 104 serves as the cathode of the parasitic silicon-controlled rectifier 110; the fourth doped region 107 serves as the anode of the parasitic silicon-controlled rectifier 110.

In some examples of this specification, the electrostatic discharge protection element 109 may include one of a metal-oxide-semiconductor crystal and a silicon-controlled rectifier. The electrostatic discharge protection element 109 may also include any element or circuit having an electrostatic discharge function. For example, the ESD protection element 109 includes a gate electrode 111 on the semiconductor substrate 101, and a fifth doped region 112 and a sixth doped region 113 on the semiconductor substrate 101. The fifth doped region 112 and the sixth doped region 113 are adjacent to the gate electrode 111. In this embodiment, the fifth doped region 112 and the sixth doped region 113 are N-type deeply doped regions, and can form an N-type metal-oxide-semiconductivity in the semiconductor substrate 101 with the gate electrode 111. Crystal (NMOS). The fifth doped region 112 and the sixth doped region 113 can be used as the drain and source of an N-type metal-oxide-semiconducting crystal, respectively. The fifth doped region 112 is electrically connected to the third doped region 106 through a wire 115. When the voltage of the voltage source is greater than the ground voltage, the current generated by the voltage source passes through the pad 108, the second doped region 105, the second doped well region 103, the first doped well region 102, and the third doped region. The area 106 flows to the electric discharge protection element 109 through the wire 115 and is introduced into the ground.

In addition, in order to increase the trigger voltage and the sustain voltage of the ESD protection element 109, in other embodiments of the present specification, the ESD protection device 100 may further include a plurality of diode elements 114 or resistance elements (not shown). It is disposed between the electric discharge protection element 109 and the third doped region 106.

In some embodiments of the present specification, the electrostatic discharge protection device 100 may be used to protect the internal circuit 21 in the integrated circuit 20 from being damaged by electrostatic discharge. For example, please refer to FIG. 2, which is a schematic diagram showing a circuit layout of the integrated circuit 20 using the electrostatic discharge protection device 100 of FIG. 1. In this embodiment, the integrated circuit 20 may be a memory element, and the internal circuit 21 thereof may be a memory cell array. The internal circuit 21 is electrically connected to the parasitic silicon controlled rectifier 110 of the electrostatic discharge protection device 100. In other embodiments of the present specification, the internal circuit 21 is not limited to a memory element, and may also be another semiconductor element, a circuit, or a combination of the two.

When a forward electrostatic discharge stress (electrostatic discharge voltage is greater than the ground voltage) is applied to the internal circuit 21, if the electrostatic discharge voltage is greater than the trigger voltage of the electrostatic discharge protection element 109, the forward electrostatic discharge current will pass through the pad 108 The first protection circuit combination 118A (through the parasitic diode and the electrostatic discharge protection element 109 formed in the NPN bipolar transistor circuit 110A (formed between the second doped well region 103 and the first doped well region 102) The bonding pad 108, the second doped region 105, the second doped well region 103, the first doped well region 102, and the third doped region 106, and then flow to the electric discharge protection element 109 through the wire 115 and are introduced into the ground. When a reverse electrostatic discharge stress (electrostatic discharge voltage is less than the ground voltage) is applied to the internal circuit 21, if the electrostatic discharge voltage is greater than the trigger voltage of the NPN bipolar transistor parasitic circuit 110A and the PNP bipolar transistor parasitic circuit 110B, The parasitic silicon controlled rectifier 110 is activated, and the reverse electrostatic discharge current generated from the reverse electrostatic discharge stress voltage source (from the ground GND) passes through the NPN bipolar transistor parasitic circuit 110A and the PNP bipolar transistor parasitic circuit 110B. The second protection circuit combination 118B is introduced into the bonding pad 108.

Please refer to FIG. 3, which is a schematic structural cross-sectional view and an equivalent circuit diagram of the electrostatic discharge protection device 300 according to another embodiment of the present specification. The configuration of the ESD protection device 300 is substantially the same as that of the ESD protection device 100 shown in FIG. 1, except that the second doped well region 303 of the ESD protection device 300 is divided into a first portion 303A and The second portion 303B; and the first doped region 104 is located in the first portion 303A, and the second doped region 105 is located in the second portion 303B.

In this embodiment, the first doped well region 102, the first portion 303A of the second doped well region 303, and the first doped region 104 form an NPN bipolar transistor parasitic circuit 310A; the second doped well region A part 303A, the first doped well region 102 and the fourth doped region 107 form a PNP bipolar transistor parasitic circuit 310B. Among them, the collector of the PNP bipolar transistor parasitic circuit 310B and the base of the NPN bipolar transistor parasitic circuit 310A are connected; and the base of the PNP bipolar transistor parasitic circuit 310B and the collection of the NPN bipolar transistor parasitic circuit 310A极 连接。 Extremely connected. The first doped region 104 serves as the cathode of the parasitic silicon controlled rectifier 310; the fourth doped region 107 serves as the anode of the parasitic silicon controlled rectifier 310.

When a forward electrostatic discharge stress (electrostatic discharge voltage is greater than the ground voltage) is applied to the pad 108 and the voltage is greater than the trigger voltage of the electrostatic discharge protection element 109, the forward electrostatic discharge current will pass through the NPN bipolar transistor parasitic circuit 310A (formed between the second portion 303B and the first doped well region 102), a first protection circuit combination 318A (via the bonding pad 108, the second doped region) formed by the parasitic diode and the electrostatic discharge protection element 109 105, the second portion 303B of the second doped well region 303, the first doped well region 102, and the third doped region 106, and then flow through the wire 115 to the electric discharge protection element 109) to the ground. When a reverse electrostatic discharge stress is applied to the bonding pad 108 and the voltage is higher than the trigger voltage of the NPN bipolar transistor parasitic circuit 310A and the PNP bipolar transistor parasitic circuit 310B, the parasitic silicon controlled rectifier 310 is activated and the reverse direction is reversed. The reverse electrostatic discharge current (from the ground GND) generated by the electrostatic discharge stress voltage source is introduced into the bonding pad 108 through the second protection circuit combination 318B composed of the NPN bipolar transistor parasitic circuit 310A and the PNP bipolar transistor parasitic circuit 310B. In an embodiment of the present specification, if a part 303A of the second doped well region 303 is left floating, the trigger voltage of the parasitic silicon controlled rectifier 310 will be greatly reduced.

Please refer to FIG. 4. FIG. 4 is a schematic structural cross-sectional view and an equivalent circuit diagram of the electrostatic discharge protection device 400 according to another embodiment of the present specification. The configuration of the ESD protection device 400 is roughly similar to that of the ESD protection device 100 shown in FIG. 1 except that the electrical properties of each doped region and the diode element 414 in the ESD protection device 400 are just the same as those of the ESD. The protection device 100 is reversed.

In this embodiment, the first doped well region 402, the second doped well region 403, and the first doped region 404 form a PNP bipolar transistor parasitic circuit 410A; the second doped region 405 and the first doped well The region 402 and the fourth doped region 407 form an NPN bipolar transistor parasitic circuit 410B. Among them, the collector of the PNP bipolar transistor parasitic circuit 410A and the base of the NPN bipolar transistor parasitic circuit 410B are connected; and the base of the PNP bipolar transistor parasitic circuit 410A and the collection of the NPN bipolar transistor parasitic circuit 410B极 连接。 Extremely connected. The first doped region 404 serves as the anode of the parasitic silicon controlled rectifier 410; the fourth doped region 407 serves as the cathode of the parasitic silicon controlled rectifier 410.

The ESD protection element 409 includes a gate electrode 411 on the semiconductor substrate 401 and a fifth doped region 412 and a sixth doped region 413 in the semiconductor substrate 401. In this embodiment, the fifth doped region 412 and the sixth doped region 413 are two P-type deeply doped regions adjacent to the gate electrode 411; the gate electrode 411, the fifth doped region 412, and the sixth doped region The region 413 may constitute a P-type metal-oxide-semiconducting crystal; the fifth doped region 412 and the sixth doped region 413 may be used as the drain and source of the P-type metal-oxide-semiconductive crystal, respectively. The fifth doped region 412 is electrically connected to the third doped region 406 through a wire 115. The electrostatic discharge protection device 400 further includes a plurality of diode elements 414 disposed between the electric discharge protection element 409 and the third doped region 406.

When a reverse electrostatic discharge stress (electrostatic discharge voltage is less than the ground voltage) is applied to the pad 108 and the voltage is greater than the trigger voltage of the electrostatic discharge protection element 409, the reverse electrostatic discharge current (electron flow) will be protected by electrostatic discharge The parasitic diode of the element 409 and the PNP bipolar transistor parasitic circuit 410A (formed between the first doped well region 402 and the second doped well region 403) and the first protection circuit combination 418A (after welding The pad 108, the second doped region 405, the second doped well region 403, the first doped well region 402, and the third doped region 406, and then flow to the electric discharge protection element 409 through the wire 115), and introduce an anti-reflection element Voltage source VDD stressing to electrostatic discharge. When a positive electrostatic discharge stress (electrostatic discharge voltage is greater than the ground voltage) is applied to the pad 108 and the voltage is greater than the trigger voltage of the PNP bipolar transistor parasitic circuit 410A and the NPN bipolar transistor parasitic circuit 410B, the parasitics are initiated. The silicon controlled rectifier 410 introduces the forward electrostatic discharge current generated by the electrostatic discharge stress voltage source VDD through the second protection circuit combination 418B formed by the PNP bipolar transistor parasitic circuit 410A and the NPN bipolar transistor parasitic circuit 410B into the bonding pad. 108.

According to the above embodiments, the present specification is to provide an electrostatic discharge protection device and its application. At least one bipolar transistor parasitic circuit is formed on a semiconductor substrate by ion doping to form a reverse parasitic silicon controlled rectifier. . It is then electrically connected to an internal circuit with another forward ESD protection element. When an electrostatic discharge stress is applied to the internal circuit, a forward electrostatic discharge protection element can be used to direct the forward electrostatic discharge current to the ground; or a reverse parasitic silicon controlled rectifier can be used to introduce the reverse electrostatic discharge current to the ground.

Among them, the "inverted parasitic silicon controlled rectifier" uses a doped well region with an N-type dopant as the base, and contains a parasitic circuit with two bipolar transistors of electrical conductivity PNP and NPN. The doped region with a type dopant is used as a ground terminal, and the doped region with an N-type dopant is electrically connected to the protected internal circuit. Because the conventional reverse electrostatic discharge path is generally the P pole is grounded, and the N pole is connected to the PNP parasitic diode of the internal circuit. When the electrostatic discharge stress makes the operating voltage of the internal circuit lower than the ground, the reverse path will occur. Large leakage current. The parasitic silicon-controlled rectifier provided in the foregoing embodiment is used to replace the conventional PNP parasitic diode to solve the problem that a large amount of leakage current is generated when the operating voltage of the internal circuit is lower than the ground.

In another embodiment of the present specification, a forward parasitic silicon controlled rectifier and another reverse electrostatic discharge protection element can also be matched to be electrically connected to the internal circuit. When an electrostatic discharge stress is applied to the internal circuit, a reverse electrostatic discharge protection element can be used to introduce reverse electrostatic discharge current to the ground; or a forward parasitic silicon controlled rectifier can be used to introduce a forward electrostatic discharge current to the ground. It is not necessary to additionally provide another electrostatic discharge protection element occupying a large layout space, and the purpose of simultaneously dispersing the forward and reverse electrostatic discharge currents and reducing the overall layout size of the integrated circuit can be achieved.

Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in this technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the appended patent application.

20‧‧‧Integrated Circuit

21‧‧‧ Internal Circuit

100, 300, 400‧‧‧‧ electrostatic discharge protection device

101, 401‧‧‧ semiconductor substrate

102, 402‧‧‧First doped well area

103, 403‧‧‧Second doped well area

104, 404‧‧‧first doped region

105‧‧‧second doped region, 405

106, 406‧‧‧ third doped region

107, 407‧‧‧ Fourth doped region

108‧‧‧pad

109, 409‧‧‧ electrostatic discharge protection element

110, 310, 410‧‧‧‧ Parasitic silicon controlled rectifier

110A, 310A, 410B‧‧‧NPN bipolar transistor parasitic circuit

110B, 310B, 410A‧‧‧PNP bipolar transistor parasitic circuit

111‧‧‧Gate electrode

112, 412‧‧‧ fifth doped region

113‧‧‧ sixth doped region, 413

114, 414‧‧‧diode elements

115‧‧‧Wire

118A, 318A, 418A‧‧‧First protection circuit combination

118B, 318B, 418B‧‧‧Second protection circuit combination

Figure 1 is a schematic cross-sectional view of the structure of an electrostatic discharge protection device and an equivalent circuit diagram according to an embodiment of the present specification; Figure 2 is a circuit layout of a integrated circuit using the electrostatic discharge protection device of Figure 1 FIG. 3 is a schematic sectional view of the structure of an electrostatic discharge protection device and an equivalent circuit diagram according to another embodiment of the present specification; and FIG. 4 is an electrostatic discharge protection device according to another embodiment of the present specification. Schematic cross-section of the device structure and equivalent circuit diagram.

no.

Claims (10)

An electrostatic discharge (ESD) protection device includes: a semiconductor substrate; a first doped well region located in the semiconductor substrate; a second doped well region located in the first doped well A first doped region, located in the second doped well region, connected to a voltage source; a second doped region, located in the second doped well region, and the first doped region Miscellaneous regions are isolated and connected to the voltage source; a third doped region is located in the first doped well region; a fourth doped region is located in the semiconductor substrate adjacent to the first doped well And the first doped region, the second doped well region, and the first doped well region form a first bipolar transistor parasitic (BJT) circuit; The second doped region, the first doped well region, and the fourth doped region form a second bipolar transistor parasitic circuit; and the first bipolar transistor parasitic circuit and the second bipolar transistor Parasitic circuits have distinct majority carriers; and an electrostatic discharge (electr ostatic discharge (ESD) protection element, which has a ground terminal and a connection terminal, the connection terminal is connected to the third doped region; when the voltage source is greater than a ground voltage, a first current passes through the first bipolar A parasitic diode in a transistor parasitic circuit and a first protection circuit combination of the electrostatic discharge protection element and a second protection including the first bipolar transistor parasitic circuit and the second bipolar transistor parasitic circuit One of the two circuit combinations is introduced to the ground; when the voltage source is less than the ground voltage, a second current is introduced to the voltage source from the ground through the other of the first protection circuit combination and the second protection circuit combination. The electrostatic discharge protection device according to item 1 of the scope of patent application, wherein the second doped well region includes a first portion and a second portion isolated from the first portion, and the first doped region is located at In the first part, the second doped region is located in the second part. The electrostatic discharge protection device according to item 1 of the scope of patent application, wherein the first doped region, the first doped well region, and the third doped region are N-type doped regions; the semiconductor substrate, the The second doped well region, the second doped region, and the fourth doped region are P-type doped regions. The electrostatic discharge protection device according to item 3 of the scope of patent application, wherein the first bipolar transistor parasitic circuit and the second bipolar transistor parasitic circuit form a parasitic silicon controlled rectifier (SCR); and The first doped region serves as a cathode of the parasitic silicon-controlled rectifier; the fourth doped region serves as an anode of the parasitic silicon-controlled rectifier. The electrostatic discharge protection device according to item 1 of the scope of patent application, wherein the first doped region, the first doped well region, and the third doped region are P-type doped regions; the semiconductor substrate, the The second doped well region, the second doped region, and the fourth doped region are N-type doped regions. The electrostatic discharge protection device described in item 1 of the patent application scope further includes a diode element electrically connected in series between the electrostatic discharge protection element and the third doped region. The electrostatic discharge protection device according to item 1 of the patent application scope, wherein the electrostatic discharge protection element includes at least one of a metal-oxide-semiconductor (MOS) transistor and a silicon controlled rectifier. One. The electrostatic discharge protection device according to item 1 of the application, wherein the fourth doped region surrounds the fourth doped region of the first doped well region. A memory element includes: an electrostatic discharge protection device including: a semiconductor substrate; a first doped well region located in the semiconductor substrate; a second doped well region located in the first doped region In a well region; a first doped region in the second doped well region connected to a voltage source; a second doped region in the second doped well region and the first doped region The doped regions are isolated and connected to the voltage source; a third doped region is located in the first doped well region; a fourth doped region is located in the semiconductor substrate adjacent to the first doped region Well region, and ground; wherein the first doped region, the second doped well region, and the first doped well region form a first bipolar transistor parasitic circuit; the second doped region, the first doped region The doped well region and the fourth doped region form a second bipolar transistor parasitic circuit; and the first bipolar transistor parasitic circuit and the second bipolar transistor parasitic circuit have different majority carriers; And an electrostatic discharge protection element having a ground terminal and a connection terminal, the connection terminal and the third doping Zone connection; when the voltage source is greater than a ground voltage, a first current passes through a parasitic diode including a parasitic diode of the first bipolar transistor parasitic circuit and a first protection circuit combination of the electrostatic discharge protection element and includes One of a combination of the first bipolar transistor parasitic circuit and a second protection circuit combination of the second bipolar transistor parasitic circuit is introduced into the ground; when the voltage source is less than the ground voltage, a second current passes through the first The other of the protection circuit combination and the second protection circuit combination is introduced into the voltage source from the ground; and a memory cell array is electrically connected to the electrostatic discharge protection device. An electrostatic discharge protection method to protect an internal circuit includes: providing an electrostatic discharge protection device electrically connected to the internal circuit. The electrostatic discharge protection device includes: a semiconductor substrate; a first doping A well region is located in the semiconductor substrate; a second doped well region is located in the first doped well region; a first doped region is located in the second doped well region; A voltage source; a second doped region located in the second doped well region, isolated from the first doped region and connected to the voltage source; a third doped region located in the first doped well A fourth doped region, located in the semiconductor substrate, adjacent to the first doped well region, and grounded; wherein the first doped region, the second doped well region, and the first doped region The doped well region forms a first bipolar transistor parasitic circuit; the second doped region, the first doped well region, and the fourth doped region form a second bipolar transistor parasitic circuit; and the first A bipolar transistor parasitic circuit and the second bipolar transistor parasitic circuit have different A number of carriers; and an electrostatic discharge protection element having a ground terminal and a connection terminal connected to the third doped region; when a first electrostatic discharge stress greater than a ground voltage is applied to the internal circuit Via a first protection circuit combination comprising a parasitic diode in the first bipolar transistor parasitic circuit and the electrostatic discharge protection element, and a parasitic circuit including the first bipolar transistor and the second bipolar transistor One of a second protection circuit combination of the crystal parasitic circuit introduces a first current into the ground; and when a second electrostatic discharge stress less than a ground voltage is applied to the internal circuit, the first protection circuit combination and The other of the second protection circuit combination introduces a second current from the ground to the voltage source.