JPH11251533A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device in which the occupied area by an electrostatic breakdown preventing circuit can be reduced, while electrostatic breakdown voltage of the electrostatic breakdown preventing circuit is improved, and to provide a manufacturing method of the semiconductor integrated circuit device which is able to reduce the number of manufacturing processes. SOLUTION: An electrostatic breakdown preventing circuit is constituted of a bipolar transistor Tr. The collector region of the bipolar transistor Tr is connected with an external part connecting terminal BP, and the emitter region is connected with power sources (a circuit reference power source and a circuit operation power source). The base region and the collector region are connected, and a resistance element 21R is interposed in series between the base region and the collector region. A surge current is absorbed by the power sources through bipolar operation and absorbed by the power sources via a diode element formed of the collector region and the base region. The resistance element 21R is formed is the same manufacturing process as the electrode of the transistor of an internal integrated circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device having an electrostatic discharge protection circuit (electrostatic discharge protection circuit) between an external connection terminal and an internal integrated circuit. And its manufacturing method.

[0002]

2. Description of the Related Art In order to prevent the internal integrated circuit from being destroyed by unexpected static electricity generated by a man-made factor during a manufacturing process or during the handling of a product, a semiconductor integrated circuit device is provided with electrostatic discharge protection. A circuit is provided. FIG. 14 is a circuit diagram of an electrostatic discharge protection circuit according to the related art.

An electrostatic discharge protection circuit PC includes an external connection terminal (bonding pad) BP for input signals and an internal integrated circuit I.
And C. The electrostatic breakdown prevention circuit PC includes a resistance element R and two diode elements D1 and D2. The resistance element R is inserted in series in a signal path from the external connection terminal BP to the internal integrated circuit IC, and has a function of smoothing a surge current that causes electrostatic breakdown. The diode element D1 has a signal path and a circuit reference power supply (for example, 0 V).
A positive surge current is absorbed by the circuit reference power supply Vss as a forward current with a negative surge current as a forward current by a reverse breakdown current. The diode element D2 is inserted between the signal path and a circuit operation power supply (for example, 5 V) Vcc, and absorbs a negative surge current into a circuit operation power supply Vcc by using a positive surge current as a forward current and a reverse breakdown current.

FIG. 15 is a longitudinal sectional structural view of a main part of the electrostatic discharge prevention circuit PC, and FIG. 16 is a plan view of a main part of the electrostatic discharge prevention circuit PC. The semiconductor integrated circuit device is formed of a semiconductor substrate 1 having a low impurity concentration p-type single crystal silicon substrate 1A and a low impurity concentration n-type epitaxial layer 1B grown on the surface thereof. The diode elements D1 and D2 of the electrostatic discharge protection circuit PC are formed on the main surface of the semiconductor substrate 1 in a region surrounded by the element isolation region.
The element isolation region is formed by the p-type single crystal silicon substrate 1A and the p-type semiconductor region 3 having a high impurity concentration.

The diode element D1 is formed by a p-type semiconductor region 5 having a high impurity concentration used as an anode region and an n-type epitaxial layer 1B used as a cathode region. The anode region is connected to a circuit reference power supply Vss. The cathode region is connected to the input signal external connection terminal BP through each of the high impurity concentration n-type buried semiconductor region 2 and the high impurity concentration n-type semiconductor region 4.

The diode element D2 is formed by a p-type semiconductor region 5 having a high impurity concentration used as an anode region and an n-type epitaxial layer 1B used as a cathode region. The anode region is the external connection terminal B for the input signal.
Connected to P. The cathode region is connected to the circuit operating power supply Vcc through each of the high impurity concentration n-type buried semiconductor region 2 and the high impurity concentration n-type semiconductor region 4.

FIG. 17 is a plan view of a main part of an electrostatic discharge prevention circuit PC for explaining another structure, and FIG. 18 is a longitudinal sectional structural view of a main part of the electrostatic discharge prevention circuit PC. As shown in FIG. 17, one diode element D1 constituting the electrostatic discharge protection circuit PC is arranged below the input signal external connection terminal (BP) 7. For example, a bonding wire 8 is bonded to the incoming signal external connection terminal 7 as shown in FIG. As shown in FIG. 18, the diode element D1 is formed of a p-type semiconductor region (also used as an element isolation region) 3 used as an anode region and an n-type epitaxial layer 1B used as a cathode region. Is done.
The cathode region is connected to the input signal external connection terminal 7 through the n-type semiconductor region 4. The n-type semiconductor region 4 is disposed at four corners of the input signal external connection terminal 7 which is not easily damaged by bonding, and the n-type semiconductor region 4 and the input signal external connection terminal 7 disposed at each of these four positions are provided. A connection is made between and. The anode region is connected to a circuit reference power supply Vss through a high impurity concentration p-type semiconductor region 5 formed on a surface portion of the p-type semiconductor region 3 forming the anode region.

[0008]

In the above-mentioned semiconductor integrated circuit device, no consideration is given to the following points. 2. Description of the Related Art Semiconductor integrated circuit devices tend to be highly integrated, and transistors constituting an internal integrated circuit IC are miniaturized.
With the miniaturization of the transistor, the p-type semiconductor region 5 used as an anode region in each of the diode elements D1 and D2 of the electrostatic discharge protection circuit PC is formed as a shallow diffusion layer. For this reason, the pn junction area between the anode region and the cathode region is reduced, and the electrostatic discharge protection circuit P
Since the surge current cannot be sufficiently absorbed by C, electrostatic breakdown occurs in the transistors of the internal integrated circuit IC, and the electrostatic breakdown withstand voltage decreases.

Therefore, as a method of increasing the surge current absorbing capability of the electrostatic discharge protection circuit PC, a method of increasing the plane area of the anode region and simply increasing the respective pn junction areas of the diode elements D1 and D2 is adopted. ing. As a result, the pn junction area similarly increases, but as shown in FIG. 16, the p-type semiconductor region 5 used as the anode region and the n-type semiconductor region 4 used as the cathode potential take-out region of the cathode region. A method of increasing the opposing length L is adopted. Both methods are p
Although the ability to absorb surge current increases due to the increase in the n-junction area, there is a problem that the area occupied by the electrostatic breakdown prevention circuit PC increases and the degree of integration of the semiconductor integrated circuit device decreases.

The present invention has been made to solve the above problems. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device which can reduce the area occupied by an electrostatic breakdown prevention circuit, improve the electrostatic breakdown withstand voltage and improve the degree of integration while improving the electrostatic breakdown prevention capability of the electrostatic breakdown prevention circuit. It is to provide.

Still another object of the present invention is to provide a method of manufacturing a semiconductor integrated circuit device which can achieve the above object and reduce the number of manufacturing steps.

[0012]

According to a first aspect of the present invention, there is provided a semiconductor integrated circuit device having an electrostatic discharge protection circuit between an external connection terminal and an internal integrated circuit. The circuit includes a bipolar transistor that absorbs a surge current input to an external connection terminal into a power supply by a bipolar operation. It is preferable that the bipolar transistor is inserted into at least one of the circuit reference power supply side and the circuit operation power supply side, or both.

In the semiconductor integrated circuit device configured as described above, a large amount of surge current can be instantaneously absorbed by the power supply by the bipolar operation of the bipolar transistor of the electrostatic breakdown prevention circuit. As a result, electrostatic breakdown of the elements of the internal integrated circuit can be prevented, and the surge current absorption ability is high. Therefore, the element size of the bipolar transistor can be reduced, and the area occupied by the electrostatic breakdown prevention circuit can be reduced.
Therefore, in the semiconductor integrated circuit device, the integration degree can be improved while improving the electrostatic breakdown voltage.

A second invention is characterized in that the base region and the emitter region of the bipolar transistor are short-circuited. Further, a resistance element for reducing the electrostatic breakdown voltage is inserted in series between the base region and the emitter region of the bipolar transistor. It is preferable that the resistance value of the resistance element is set in a range of several KΩ to several tens KΩ.

In the semiconductor integrated circuit device configured as described above, the electrostatic breakdown voltage of the bipolar transistor in the electrostatic breakdown prevention circuit is determined by the resistance element inserted between the base region and the emitter region or between the base region and the emitter region. Can be reduced by Accordingly, the electrostatic breakdown withstand voltage of the electrostatic breakdown prevention circuit can be set to be smaller than the electrostatic breakdown withstand voltage of the transistor forming the internal integrated circuit, and thus, the electrostatic breakdown of the transistor forming the internal integrated circuit can be prevented.

A third invention is characterized in that the emitter region of the bipolar transistor is divided into a plurality.

In the semiconductor integrated circuit device configured as described above, a base potential extraction region can be formed between a plurality of divided emitter regions of the bipolar transistor of the electrostatic breakdown prevention circuit, so that carriers in the base region are immediately absorbed. it can. Therefore, the surge current input to the collector region or the emitter region of the bipolar transistor can be immediately absorbed by the power supply, so that the electrostatic breakdown voltage can be improved.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device having an electrostatic discharge protection circuit between an external connection terminal and an internal integrated circuit. First, a transistor for forming an internal integrated circuit is formed. A bipolar transistor of an electrostatic breakdown prevention circuit for absorbing a surge current input to an external connection terminal into a power supply by a bipolar operation is formed. Next, the electrodes of the transistors forming the internal integrated circuit are formed, and a resistive element for reducing the electrostatic breakdown voltage is formed between the base region and the emitter region of the bipolar transistor of the electrostatic discharge prevention circuit in the same conductive layer as the electrodes. I do.

MISFET as transistor in internal integrated circuit
Is formed, the resistance element is formed by the same manufacturing process as that of the gate electrode of the MISFET. When a bipolar transistor is formed as a transistor in an internal integrated circuit, a resistance element is formed by the same manufacturing process as that of the emitter electrode of the bipolar transistor.

In the method of manufacturing a semiconductor integrated circuit device configured as described above, the electrode of the transistor constituting the internal integrated circuit and the resistance element of the electrostatic discharge protection circuit are formed in the same manufacturing process, thereby forming the resistance element. Since the number of steps can be reduced, the number of manufacturing steps can be reduced.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 2 shows a first embodiment of the present invention.
FIG. 9 is a circuit diagram of an electrostatic discharge protection circuit arranged on the input side of the semiconductor integrated circuit device according to the embodiment.

The electrostatic discharge protection circuit PC is arranged between the input signal external connection terminal BP and the internal integrated circuit IC.
The electrostatic breakdown prevention circuit PC includes a resistance element R and two bipolar transistors Tr1 and Tr2.

The resistance element R is inserted in series in a signal path from the external connection terminal BP to the internal integrated circuit IC, and has a function of smoothing a surge current that causes electrostatic breakdown.

The bipolar transistor Tr1 is inserted between a signal path and a circuit reference power supply (for example, 0 V) Vss, and has an npn type. Bipolar transistor T
The collector region of r1 is connected to the external connection terminal BP, and the emitter region is connected to the circuit reference power supply Vss. The base region and the emitter region are electrically connected,
A resistor R1 is provided between the base region and the emitter region.
Are electrically connected in series. The bipolar transistor Tr1 is connected to the external connection terminal B by the bipolar operation.
The positive surge current input to P is absorbed by the circuit reference power supply Vss. A large amount of the surge current is immediately absorbed by the circuit reference power supply Vss. Further, a pn junction between the collector region and the base region of the bipolar transistor Tr1 forms a diode element, and a positive surge current is absorbed by the circuit reference power supply Vss as a reverse breakdown current caused by the diode element. When a negative surge current is input to the external connection terminal BP, the bipolar transistor Tr1
By the bipolar operation, a current is supplied from the circuit reference power supply Vss to the external connection terminal BP side to offset the negative surge current. In terms of the flow of electrons, it can be said that a large amount of electrons in the collector region due to the negative surge current are immediately absorbed by the circuit reference power supply Vss. Further, the diode element formed at the pn junction between the collector region and the base region of the bipolar transistor Tr1 supplies a forward current that cancels a negative surge current to the circuit reference power supply V.
Supply from ss to the collector region side.

The bipolar transistor Tr2 is inserted between a signal path and a circuit operation power supply (for example, 5 V) Vcc, and is of a pnp type. Bipolar transistor T
The collector region of r2 is connected to the external connection terminal BP, and the emitter region is connected to the circuit operation power supply Vcc. The base region and the emitter region are electrically connected,
A resistor R2 is provided between the base region and the emitter region.
Are electrically connected in series. The bipolar transistor Tr2 is connected to the external connection terminal B by the bipolar operation.
The positive surge current input to P is absorbed by the circuit operating power supply Vcc. A large amount of surge current is immediately absorbed by the circuit operation power supply Vcc. Further, a pn junction between the collector region and the base region of the bipolar transistor Tr2 forms a diode element, and a positive surge current is absorbed by the circuit operation power supply Vcc as a forward current generated by the diode element. When a negative surge current is input to the external connection terminal BP, the bipolar transistor Tr2 supplies a current that cancels the negative surge current from the circuit operating power supply Vcc to the external connection terminal BP due to the bipolar operation. . In terms of the flow of electrons, it can be said that a large amount of electrons in the collector region due to the negative surge current are immediately absorbed by the circuit operating power supply Vcc. Further, the diode element formed at the pn junction between the collector region and the base region of the bipolar transistor Tr2 generates a reverse breakdown current that offsets a negative surge current by the circuit operation power supply V.
Supply from cc to the collector region side.

FIG. 1 is a longitudinal sectional view of a main part of a semiconductor integrated circuit device showing the external connection terminal BP, the electrostatic discharge protection circuit PC, and the internal integrated circuit IC. The semiconductor integrated circuit device is a p-type single crystal silicon substrate 10 having a low impurity concentration.
The semiconductor substrate 10 includes A and a low impurity concentration n-type epitaxial layer 10B grown on the surface thereof. The p-type single crystal silicon substrate 10A is, for example, several Ωcm to several tens Ω.
Set to a resistance value of cm. n-type epitaxial layer 10B
Is set to, for example, an impurity concentration of 10 ¹⁵ -10 ¹⁶ atoms / cm ³ .

In the semiconductor integrated circuit device according to the present embodiment, the internal integrated circuit IC is a complementary MISFET (Metal Ins
ulator Semiconductor Field Effect Transistor) and bipolar transistors. The internal integrated circuit IC constructs a logic circuit based on these semiconductor elements. As shown in FIG. 1, each semiconductor element is formed in a region surrounded by an element isolation region. The element isolation region includes a p-type single crystal silicon substrate 10A, a high impurity concentration p
The buried semiconductor region 12 and the p-type semiconductor region 16 having a high impurity concentration are formed. The p-type buried semiconductor region 12 is
P-type single crystal silicon substrate 10A and n-type epitaxial layer 10
B and is set to an impurity concentration of, for example, 10 ¹⁸ atoms / cm ³ . The p-type semiconductor region 16 is formed in the n-type epitaxial layer 10B so as to be electrically connected to the p-type buried semiconductor region 12, and is set to an impurity concentration of, for example, 10 ¹⁸ atoms / cm ³ . Although not shown, an inter-element isolation insulating film (for example, a silicon oxide film) is formed between the semiconductor elements on the surface of the n-type epitaxial layer 10B.

The n-channel MISFET Qn of the complementary MISFET is
In FIG. 1, as shown on the right side of the center, it is formed on the main surface of the p-type well region 13 having a low impurity concentration. p-type well region 1
3 is formed on the n-type epitaxial layer 10B, for example,
The impurity concentration is set to 10 ¹⁵ -10 ¹⁶ atoms / cm ³ . The n-channel MISFET Qn has a gate insulating film 20 and a gate electrode 2
1, a pair of high impurity concentration n-type semiconductor regions 23 used as a source region and a drain region. The gate insulating film 20 is formed of, for example, a single-layer film of a silicon oxide film or a composite film in which a silicon oxide film and a silicon nitride film are combined.
The gate electrode 21 is formed on the surface of the gate insulating film 20 and is formed of, for example, a polycrystalline silicon film having a thickness of 300 to 500 nm and doped with an impurity (for example, adjacent or arsenic) for reducing a resistance value. . The gate electrode 21 is formed of a single layer of a silicide film or a refractory metal film, which is a compound of silicon and a refractory metal, or a composite film in which a silicide film or a refractory metal film is stacked on a polycrystalline silicon film. May be. n
The type semiconductor region 23 is formed on the surface of the p-type well region 13B, and is set to, for example, an impurity concentration of 10 ²⁰ atoms / cm ³ . Impurities are introduced into the n-type semiconductor region 23 by an ion implantation method using the gate electrode 21 as a mask, and are formed by self-alignment with the gate electrode 21.

Type semiconductor region 23 of n-channel MISFET Qn
Is electrically connected to the first layer wiring 26. Wiring 2
6 is formed on the surface of the interlayer insulating film 25 and is connected to the n-type semiconductor region 23 through a connection hole (not numbered) formed in the interlayer insulating film 25. The wiring 26 is formed of, for example, a single layer film of an aluminum alloy film or a composite film mainly including the aluminum alloy film. The wiring 26 is electrically connected to a second-layer wiring 28. The wiring 28 is formed on the surface of the interlayer insulating film 27, and is connected to the wiring 26 through a connection hole (not denoted by a reference numeral) formed in the interlayer insulating film 27. The wiring 28 is formed of the same material as the wiring 26.

The p-channel MISFET Qp of the complementary MISFET is:
In FIG. 1, as shown on the right side of the center, it is formed on the main surface of the n-type well region 14 having a low impurity concentration. n-type well region 1
4 is formed on the n-type epitaxial layer 10B, for example,
The impurity concentration is set to 10 ¹⁵ -10 ¹⁶ atoms / cm ³ . The p-channel MISFET Qp has a gate insulating film 20 and a gate electrode 2
1. A pair of high impurity concentration p-type semiconductor regions 24 used as a source region and a drain region. Each of the gate insulating film 20 and the gate electrode 21 is an n-channel MI
The gate insulating film 20 and the gate electrode 21 of the SFET Qn are formed of the same material and in the same manufacturing process. The p-type semiconductor region 24 is formed on the surface of the n-type well region 14 and has an impurity concentration of, for example, 10 ²⁰ atoms / cm ³ . Similarly, p-type semiconductor region 24 is formed by self-alignment with gate electrode 21.

P-type semiconductor region 2 of p-channel MISFET Qp
4 is electrically connected to a first layer wiring 26,
6 is electrically connected to a second layer wiring 28.

The bipolar transistor Tr of the internal integrated circuit IC is formed of a vertical npn type having an n-type collector region, a p-type base region and an n-type emitter region, as shown at the right end in FIG. .

The n-type collector region is formed of an n-type epitaxial layer 10B used as an intrinsic collector region, an n-type buried semiconductor region 11 and an n-type semiconductor region 15 used as a collector potential extracting region. . The n-type buried semiconductor region 11 is buried between the p-type single crystal silicon substrate 10A and the n-type epitaxial layer 10B, and is set to an impurity concentration of, for example, 10 ¹⁸ atoms / cm ³ .
The n-type semiconductor region 15 is formed in the n-type epitaxial layer 10B so as to be electrically connected to the n-type buried semiconductor region 11, and is set to, for example, an impurity concentration of 10 ¹⁸ atoms / cm ³ . The first layer wiring 26 is electrically connected to the n-type semiconductor region 15.

The p-type base region includes a p-type semiconductor region 17 having a medium impurity concentration used as an intrinsic base region and a p-type semiconductor region 24 used as a base potential extraction region.
Is formed in each of. The p-type semiconductor region 17 is formed on the surface of the n-type epitaxial layer 11,
The impurity concentration is set to ¹⁸ atoms / cm ³ . The p-type semiconductor region 24 is formed in the same manufacturing process as the p-type semiconductor region 24 of the p-channel MISFET Qp. The first-layer wiring 26 is electrically connected to the p-type semiconductor region 24.

The n-type emitter region is formed on the surface of p-type semiconductor region 17 used as an intrinsic base region, and is formed of n-type semiconductor region 22 having a high impurity concentration.
In the present embodiment, the n-type emitter region of the bipolar transistor Tr, that is, the n-type semiconductor region 22 is formed with an emitter diffusion type structure formed by doping an n-type impurity from the emitter electrode 21. The bipolar transistor Tr employing the emitter diffusion type structure can realize a shallow diffusion layer of the n-type emitter region. The n-type semiconductor region 22 is set to, for example, an impurity concentration of 10 ²⁰ atoms / cm ³ .

The emitter electrode 21 is formed of, for example, a polycrystalline silicon film serving as a diffusion source of an n-type impurity. In the present embodiment, the emitter electrode 21 is an n-channel MISFET Qn,
The gate electrode 21 of the p-channel MISFET Qp is formed of the same material as the gate electrode 21 and formed by the same manufacturing process. Note that the emitter electrode 21 may be formed in a different manufacturing process from that of the gate electrode 21 or may be formed of an electrode material different from that of the gate electrode 21. The emitter electrode 21 has a first layer wiring 2
6 are electrically connected.

FIG. 3 is a plan view of the electrostatic discharge protection circuit PC. In FIG. 1, as shown in the center left and FIG. 3, the bipolar transistor Tr1 of the electrostatic discharge protection circuit PC is
Basically, it has a structure similar to the bipolar transistor Tr of the internal integrated circuit IC. That is, the bipolar transistor Tr1 is formed of a vertical npn type having an n-type collector region, a p-type base region, and an n-type emitter region.

The n-type collector region is formed of an n-type epitaxial layer 10B used as an intrinsic collector region, an n-type buried semiconductor region 11 and an n-type semiconductor region 15 used as a collector potential take-out region. . The n-type semiconductor region 15 includes a first layer wiring 26, a second layer
Through each of the wirings 28 of the layer, electricity is supplied to the input signal external connection terminal BP (shown on the left end in FIG. 1) formed in the same wiring layer and made of the same material as the wiring 28 of the second layer. Connected.

The p-type base region includes a p-type semiconductor region 17 having a medium impurity concentration used as an intrinsic base region and a p-type semiconductor region 24 used as a base potential extraction region.
Is formed in each of.

The n-type emitter region is formed on the surface of p-type semiconductor region 17 used as an intrinsic base region, and is formed of n-type semiconductor region 23 having a high impurity concentration.
In the present embodiment, the n-type emitter region of the bipolar transistor Tr, that is, the n-type semiconductor region 23 is formed in the same manufacturing process as the n-type semiconductor region 23 used as each of the source region and the drain region of the n-channel MISFET Qn. It is formed with the same impurity concentration. The n-type semiconductor region 23 is formed by an ion implantation method in the manufacturing process, and the depth of the diffusion layer can be slightly deeper than that of the n-type semiconductor region 22 in the above-described emitter diffusion type structure. Therefore, the n-type semiconductor region 23 can increase the pn junction area formed between the n-type semiconductor region 23 and the p-type semiconductor region 17, and can increase the cross-sectional area of the passage path of the surge current. Note that the n-type emitter region may be formed with an emitter diffusion type structure, similarly to the n-type emitter region of the bipolar transistor Tr described above.

The p-type semiconductor region 24 of the p-type base region and n
The p-type semiconductor region 24 and the n-type semiconductor region 23 are basically electrically connected (short-circuited) to the n-type semiconductor region 23 of the type emitter region by the first-layer wiring 26.
A resistance element 21R (R1) is electrically inserted in series. The resistance element 21R is provided near and around the bipolar transistor Tr1. Resistance element 21
One end of R is connected to n-type semiconductor region 23 through wiring 26, and the other end of resistance element 21R is connected to n-type semiconductor region 23 through wiring 26.
Is connected to the type semiconductor region 24.

FIGS. 4A and 4B respectively show a bipolar transistor Tr1 for explaining an electrostatic breakdown preventing operation.
FIG. As shown in FIG. 4A, when an unexpected positive surge current that causes electrostatic discharge damage to the transistor at the first input stage that constitutes the internal integrated circuit IC is input to the input signal external connection terminal BP, a bipolar transistor is used. The transistor Tr1 causes a positive surge current to flow from the n-type collector region to the n-type emitter region by a bipolar operation, and this positive surge current is absorbed by the circuit reference power supply Vss. Further, since the bipolar transistor Tr1 electrically connects the p-type base region and the n-type emitter region, the n-type epitaxial layer 10B of the n-type collector region
A positive surge current can flow through a diode element formed by a pn junction between the (intrinsic collector region) and the p-type semiconductor region 17 (intrinsic base region) of the p-type base region. The positive surge current flowing through this diode element is absorbed by the circuit reference power supply Vss. In the diode element,
The positive surge current flows as a reverse breakdown current. That is, the bipolar transistor Tr1 has two paths through which a surge current flows, and a large amount of surge current is immediately absorbed by the circuit reference power supply Vss. Further, since the diode element is formed by a pn junction having a relatively low impurity concentration between the n-type epitaxial layer 10B and the p-type semiconductor region 17, the electrostatic breakdown voltage of the diode element itself is increased.

On the other hand, as shown in FIG. 4B, when a negative surge current is input to the input signal external connection terminal BP,
The bipolar transistor Tr1 supplies a current that cancels a negative surge current from the circuit reference power supply Vss to the external connection terminal BP side by a bipolar operation. Similarly to the above, the bipolar transistor Tr1 is connected to the circuit reference power supply Vss through a diode element formed by a pn junction between the n-type collector region and the p-type base region. Supply to terminal BP side. In the diode element, the negative surge current flows as a forward current. When viewed as a flow of electrons, it can be expressed that electrons generated by a negative surge current are absorbed by the circuit reference power supply Vss through the bipolar transistor Tr1.

FIG. 4C shows a bipolar transistor Tr.
FIG. 4 is a diagram showing a relationship between a resistance value (KΩ) of a resistance element 21R inserted between a p-type base region and an n-type emitter region and an electrostatic breakdown voltage (V). As described above, by electrically connecting the p-type base region and the n-type emitter region of the bipolar transistor Tr1, this connection path can be used as a surge current absorption path, and a large amount of surge current can be instantaneously provided. Can be absorbed. In the present embodiment, a resistance element 21R is further inserted into a surge current absorption path including a diode element. As shown in FIG. 4C, with respect to a positive surge current, the electrostatic breakdown voltage of the bipolar transistor Tr1 itself improves as the resistance value of the resistance element 21R increases. Conversely, for a negative surge current, the electrostatic breakdown voltage of the bipolar transistor Tr1 itself decreases as the resistance value of the resistance element 21R increases. In the present embodiment, while maintaining the same electrostatic breakdown voltage with respect to each of the positive surge current and the negative surge current, the electrostatic breakdown protection circuit is more than the electrostatic breakdown voltage of the first input transistor of the internal integrated circuit IC. To reduce the electrostatic breakdown voltage of the PC and protect the transistor at the first input stage, the resistance value of the resistance element 21R is set to about 8-12 KΩ. Preferably, resistance element 21R is set to about 10 KΩ.

In FIG. 1, as shown in the left side of the center and in FIG.
Bipolar transistor Tr of static electricity prevention circuit PC
Reference numeral 2 denotes a pnp type transistor having a lateral structure including a p-type collector region, an n-type base region, and a p-type emitter region.

The p-type collector region is formed of a high impurity concentration p-type semiconductor region 24 used as an intrinsic collector region. The p-type collector region has a planar shape formed in a ring shape surrounding the p-type emitter region with the n-type base region interposed therebetween. In the bipolar transistor Tr2 having such a planar shape, in particular, the pn junction area between the p-type collector region and the n-type base region can be increased (the pn junction length can be increased), so that the electrostatic breakdown voltage can be improved. p
The p-type semiconductor region 24 is formed in the same manufacturing process as the p-type semiconductor region 24 used as each of the source region and the drain region of the p-channel MISFET Qp, and is formed with the same impurity concentration. The p-type semiconductor region 24 is electrically connected to the input signal external connection terminal BP formed by the second layer wiring 28 through each of the first layer wiring 26 and the second layer wiring 28. Is done.

The n-type base region includes an n-type epitaxial layer 10B used as an intrinsic base region, and an n-type buried semiconductor region 11 used as a base potential extraction region.
And n-type semiconductor region 23.

The p-type emitter region is formed of a high impurity concentration n-type semiconductor region 23. Both the p-type collector region and the p-type emitter region are formed on the surface of the n-type epitaxial layer 10B used as the intrinsic base region.

The n-type semiconductor region 23 of the n-type base region and p
The p-type semiconductor region 24 of the type emitter region is basically electrically connected to the p-type semiconductor region 24 by the first layer wiring 26 in the same manner as the bipolar transistor Tr1.
1R (R2) is electrically inserted in series. The resistance element 21R is provided near and around the bipolar transistor Tr2. One end of the resistance element 21R is connected to the wiring 26.
Through the resistance element 21
The other end of R is connected to n-type semiconductor region 23 through wiring 26.

When a positive surge current higher than the potential of the circuit operating power supply Vcc is input to the input signal external connection terminal BP, the bipolar transistor Tr2 operates in the same manner as the above-described bipolar transistor Tr1. Flow to the power supply Vcc side. This positive surge current is absorbed by the circuit operation power supply Vcc. Further, as shown in FIG. 2, since the n-type base region and the p-type emitter region are electrically connected, the p-type semiconductor region 24 of the p-type collector region and the n-type epitaxial region of the n-type base region are electrically connected. Layer 10
A positive surge current flows through a diode element formed by a pn junction with B, and the positive surge current is absorbed by the circuit operation power supply Vcc. In the diode element, a positive surge current flows as a forward current. That is, the bipolar transistor Tr2 has two paths through which a surge current flows, and a large amount of surge current can be immediately absorbed by the circuit operation power supply Vcc.

On the other hand, when a negative surge current is input to the input signal external connection terminal BP, the bipolar transistor T
r2 supplies a current that cancels the negative surge current from the circuit operation power supply Vcc to the external connection terminal BP side by the bipolar operation. As described above, the bipolar transistor Tr2 further passes through a diode element formed by a pn junction between the p-type collector region and the n-type base region.
The circuit operating power supply V
cc to the external connection terminal BP. In the diode element, the negative surge current flows as a reverse breakdown current. When viewed as a flow of electrons, it can be expressed that electrons generated by a negative surge current are absorbed by the circuit operating power supply Vcc through the bipolar transistor Tr2.

Further, since the resistance element 21R having an appropriate resistance value is inserted between the n-type base region and the p-type emitter region of the bipolar transistor Tr2,
Electrostatic breakdown can be prevented in the first input transistor of the internal integrated circuit IC.

Next, a brief description will be given of a method of manufacturing the resistance element 21R to be added to each of the bipolar transistors Tr1 and Tr2 of the above-described electrostatic breakdown prevention circuit PC. FIGS. 5A and 5B respectively show the resistance element 21.
It is a longitudinal section structural view of a semiconductor integrated circuit device shown for every manufacturing process explaining a manufacturing method of R.

(1) As shown in FIG. 5A, a p-type well region 13 and an n-type well region 14 are formed in a main surface portion of a semiconductor substrate 1 in a region where an internal integrated circuit IC is to be formed. An n-type collector region and an intrinsic base region (p-type semiconductor region 17) of a p-type base region of the transistor Tr are formed. Further, the n-type collector region of the bipolar transistor Tr1 and the intrinsic base region (p-type base region) of the p-type base region are formed in the formation region of the electrostatic discharge protection circuit PC by the same manufacturing process as the respective operation regions of the bipolar transistor Tr of the internal integrated circuit IC. The semiconductor region 17) and the intrinsic base region (n-type epitaxial 10B) of the n-type base region of the bipolar transistor Tr2 are formed.

(2) In the formation region of the internal integrated circuit IC, the n-type well region 1 is formed on the surface of the p-type well region 13.
Then, a gate insulating film 20 and a gate electrode 21 are formed on the surface of the substrate 4 (see FIG. 5B). This gate electrode 2
The emitter electrode 21 of the bipolar transistor Tr is formed in the same manufacturing process as the process for forming the transistor 1. Gate electrode 2
1. Each of the emitter electrodes 21 is formed of, for example, a polycrystalline silicon film formed by a CVD method, and this polycrystalline silicon film is doped with an n-type impurity for adjusting a resistance value. In the formation region of the bipolar transistor Tr, an n-type impurity is diffused from the emitter electrode 21 to the intrinsic base region.
An n-type semiconductor region 22 used as a type emitter region is formed.

Further, a step of forming a gate electrode 21;
Alternatively, the resistance element 21R inserted between the base region and the emitter region of each of the bipolar transistors Tr1 and Tr2 in the formation region of the electrostatic discharge protection circuit PC by the same manufacturing process as the process of forming the emitter electrode 21.
Is formed. That is, resistance element 21R is formed of, for example, a polycrystalline silicon film. The resistance value of the resistance element 21R is set by adjusting the size (for example, adjusting the resistance length, the cross-sectional area, etc.) and by adjusting the doping amount of the n-type impurity.

(3) As shown in FIG. 5B, in the formation region of the internal integrated circuit IC, a pair of n-type semiconductor regions 23 are formed in the p-type well region 13 and the n-type well region 14 is formed.
Then, a pair of p-type semiconductor regions 24 are formed. The formation of the n-type semiconductor region 23 completes the n-channel MISFET Qn. By forming the p-type semiconductor region 24, the p-channel MISF
ETQp is completed. By the same manufacturing process as that of forming the p-type semiconductor region 24, the p-type semiconductor region 24 of the p-type base region is formed in the formation region of the bipolar transistor Tr of the internal integrated circuit IC. By forming the p-type semiconductor region 24, the bipolar transistor Tr is completed.

Further, in the formation region of the bipolar transistor Tr1 of the electrostatic breakdown prevention circuit PC, the n-type semiconductor region 23 of the n-type emitter region is formed in the same manufacturing process as the process of forming the n-type semiconductor region 23, and the p-type semiconductor is formed. The p-type semiconductor region 24 of the p-type base region is formed in the same manufacturing process as the process of forming the region 24. By forming each of the n-type semiconductor region 23 and the p-type semiconductor region 24,
The bipolar transistor Tr1 is completed. In the formation region of the bipolar transistor Tr2, the n-type semiconductor region 23 of the n-type base region is formed in the same manufacturing process as the process of forming the n-type semiconductor region 23, and the p-type semiconductor region 2 is formed.
4, a p-type collector region in the same manufacturing process as the process of forming
Each p-type semiconductor region 24 of the p-type emitter region is formed. The n-type semiconductor region 23 and the p-type semiconductor region 2
4, the bipolar transistor T
r2 is completed.

(4) As shown in FIG. 1 described above, an interlayer insulating film 25, a first layer wiring 26, an interlayer insulating film 27, and a second layer wiring 28 are sequentially formed. By forming a protective film that is not used, the semiconductor integrated circuit device according to the present embodiment is completed.

It is to be noted that the present invention relates to an integrated
The semiconductor integrated circuit device (Bipola-Complementary MISFET type semiconductor integrated circuit device) in which the ETQ and the bipolar transistor Tr are mixed has been described. However, the semiconductor integrated circuit device (pure Bipola type semiconductor integrated device) in which the internal integrated circuit IC is constructed by the bipolar transistor Tr Circuit device). In this case, the bipolar transistor Tr1 of the internal integrated circuit IC preferably employs the emitter diffusion type structure as described above in order to improve the degree of integration, and the same manufacturing process as that of the emitter electrode 21 used in the emitter diffusion type structure is employed. The resistance element 21R used in the destruction prevention circuit PC is formed.

Further, according to the present invention, the gate electrode 21 of the MISFET Q and the emitter electrode 21 of the bipolar transistor Tr are provided.
The resistance element 21R used in the electrostatic discharge protection circuit PC may be formed by a manufacturing process different from the above.
In this case, the resistance value of the resistance element 21R can be set independently and optimally.

In the semiconductor integrated circuit device configured as described above, the electrostatic breakdown prevention circuit PC includes the bipolar transistors Tr1 and Tr2, and the bipolar operation of each of the bipolar transistors Tr1 and Tr2 generates a large amount of surge current immediately. It can be absorbed by each of the circuit reference power supply Vss and the circuit operation power supply Vcc. Since a large amount of surge current can be instantaneously absorbed, electrostatic breakdown of the transistor at the first input stage of the internal integrated circuit IC can be prevented. That is, since the surge current absorbing ability is high, the element size of each of the bipolar transistors Tr1 and Tr2 can be reduced, and the area occupied by the electrostatic discharge protection circuit PC can be reduced. Therefore, in the semiconductor integrated circuit device, the integration degree can be improved while improving the electrostatic breakdown voltage.

Further, in each of the bipolar transistors Tr1 and Tr2 of the electrostatic discharge protection circuit PC,
The base region and the emitter region are electrically connected,
Alternatively, a resistor 21R may be provided between the base region and the emitter region.
Are inserted in series, the electrostatic breakdown withstand voltage of the electrostatic breakdown prevention circuit PC is reduced. Therefore, the internal integrated circuit IC
Of the first input transistor can be prevented from being destroyed by static electricity.

Further, when the MISFET Q is formed as a transistor in the internal integrated circuit IC, the electrostatic discharge protection circuit P is formed by the same manufacturing process as the gate electrode 21 of the MISFET Q.
C resistance element 21R can be formed. Further, a bipolar transistor Tr is used as a transistor in the internal integrated circuit IC.
Is formed, the resistance element 21R is formed by the same manufacturing process as the emitter electrode 21 of the bipolar transistor Tr.
Can be formed. Therefore, the number of steps for forming the resistance element 21R can be reduced, and the number of manufacturing steps of the semiconductor integrated circuit device can be reduced.

First Application Example A first application example describes a case where the pnp bipolar transistor Tr2 of the electrostatic discharge protection circuit PC is formed in a vertical structure. FIG. 6 is a longitudinal sectional structural view of a bipolar transistor according to a first application example in the first embodiment of the present invention.

The bipolar transistor Tr2 of the electrostatic breakdown prevention circuit PC has a p-type collector region, an n-type base region, and a p-type collector region within a region surrounded by an element isolation region.
It has a pnp type with a vertical structure having a type emitter region. The element isolation region is formed in the low impurity concentration n-type buried semiconductor region 30, the n-type epitaxial layer 10B, and the surface portion of the n-type epitaxial layer 10B formed on the surface of the p-type single crystal silicon substrate 10A. And is formed of an n-type semiconductor region 23 used as a potential extraction region. Note that, in the following description, the components denoted by the same reference numerals as those of the configuration described in the semiconductor integrated circuit device according to the first embodiment have the same functions, and have the same impurity concentration. Or formed by the same manufacturing process.

The p-type collector region of the bipolar transistor Tr2 includes a p-type well region 13 used as an intrinsic collector region, a p-type buried semiconductor region 12 and a p-type semiconductor region 16 used as a collector potential extraction region.
Is formed. The p-type semiconductor region 16 is connected to the input signal external connection terminal BP.

The n-type base region includes an n-type semiconductor region 31 having a medium impurity concentration used as an intrinsic base region and an n-type semiconductor region 2 used as a base potential extraction region.
3 is formed.

The p-type emitter region is formed by the p-type semiconductor region 24. The p-type semiconductor region 24 is electrically connected to the n-type semiconductor region 23 of the n-type base region and is connected to a circuit operation power supply Vcc. Further, a resistor 21R is provided between the p-type emitter region and the n-type base region.
(R2) is electrically inserted in series.

In the electrostatic breakdown prevention circuit PC thus configured, a vertical bipolar transistor Tr2 is provided on the side of the circuit operating power supply Vcc, and a surge current flows through a wide pn junction including the bottom and side surfaces of the intrinsic base region. Flows. Therefore, the ability to absorb surge current can be improved,
The electrostatic breakdown prevention voltage of the electrostatic breakdown prevention circuit PC can be improved.

Second Application Example In a second application example, in the electrostatic discharge protection circuit PC, the bipolar transistor Tr2 on the circuit operation power supply Vcc side is formed in an npn type structure, and the circuit reference power supply Vss side and the circuit operation power supply Vcc side Of both bipolar transistors Tr
The case where both Tr1 and Tr2 are formed in an npn-type structure will be described. FIG. 7 is a circuit diagram of an electrostatic discharge protection circuit PC according to a second application example in the first embodiment of the present invention.

As shown in FIG. 7, the electrostatic discharge protection circuit P
In C, the bipolar transistor Tr2 on the side of the circuit operation power supply Vcc is formed in an npn type structure. The bipolar transistor Tr2 has the same structure as the structure of the bipolar transistor Tr1 shown in FIG.
The n-type collector region of bipolar transistor Tr2 is electrically connected to circuit operation power supply Vcc. The p-type base region and the n-type emitter region are electrically connected, and both the p-type base region and the n-type emitter region are electrically connected to the input signal external connection terminal BP. Between the p-type base region and the n-type emitter region, a resistance element 21R (R
2) are inserted electrically in series. That is, the circuit reference power supply Vss side of the electrostatic breakdown prevention circuit PC and the circuit operation power supply V
Both bipolar transistors Tr1 and Tr2 on the cc side
Are formed with an npn-type structure.

In the electrostatic breakdown prevention circuit PC configured as described above, the same effects as those of the electrostatic breakdown prevention circuit PC described in the first embodiment can be obtained.

Third Application Example In a third application example, in the electrostatic discharge protection circuit PC, the bipolar transistor Tr1 on the circuit reference power supply Vss side is formed of a pnp type having a horizontal structure, and the circuit reference power supply Vss side is used.
A case where both of the bipolar transistors Tr1 and Tr2 on the circuit operation power supply Vcc side are formed in a pnp type structure will be described. FIG. 8 is a circuit diagram of an electrostatic discharge protection circuit PC according to a third application example in the first embodiment of the present invention.

As shown in FIG. 8, the electrostatic discharge protection circuit P
In C, the bipolar transistor Tr1 on the circuit reference power supply Vss side is formed in a pnp type structure. The bipolar transistor Tr2 has the same structure as the structure of the bipolar transistor Tr2 shown in FIG. 1 or FIG. The p-type collector region of bipolar transistor Tr1 is electrically connected to circuit reference power supply Vss. The n-type base region and the p-type emitter region are electrically connected,
Both the n-type base region and the p-type emitter region are electrically connected to the input signal external connection terminal BP. A resistor 21R is provided between the n-type base region and the p-type emitter region.
(R1) is inserted electrically in series. That is, the bipolar transistors Tr1 and T2 on both the circuit reference power supply Vss side and the circuit operation power supply Vcc side of the electrostatic discharge protection circuit PC.
Each of r2 has a pnp type structure.

FIG. 9 is a longitudinal sectional structural view of the bipolar transistor Tr1 on the circuit reference power supply side of the electrostatic discharge protection circuit PC. The bipolar transistor Tr1 is formed of a lateral pnp type having a p-type collector region, an n-type base region, and a p-type emitter region in a region surrounded by an element isolation region. The element isolation region is formed by the p-type single crystal silicon substrate 10A, the p-type semiconductor region 16, and the p-type semiconductor region 24.

The p-type collector region of the bipolar transistor Tr1 is formed by a p-type semiconductor region 16 used as an intrinsic collector region and a p-type semiconductor region 24 used as a collector potential extraction region.

The n-type base region includes an n-type epitaxial layer 10B used as an intrinsic base region, an n-type buried semiconductor region 30 used as a connection wiring connecting the n-type epitaxial layers 10B, and a base potential extraction region. It is formed of an n-type semiconductor region 23 used as a semiconductor device.

The p-type emitter region is a p-type semiconductor region 16 used as an intrinsic emitter region and used as an emitter potential extraction region, and a p-type buried semiconductor used as a connection wiring connecting between the p-type semiconductor regions 16. Area 1
2 are formed. The p-type semiconductor region 16 is connected to the input signal external connection terminal BP.

The bipolar transistor Tr1 is formed in a horizontal type, and in order to enlarge the passage of the surge current, the planar shape of the p-type emitter region is formed in a ring shape. Each of the n-type base region and the p-type collector region is formed. Also p
The planar shape is formed in a ring shape so as to surround the periphery of the mold emitter region.

In the electrostatic discharge protection circuit PC thus configured, the same effects as those of the electrostatic discharge prevention circuit PC described in the first embodiment can be obtained.

Fourth Application Example In a fourth application example, in the electrostatic discharge protection circuit PC, the bipolar transistor Tr1 on the circuit reference power supply Vss side is formed in a pnp structure, and the bipolar transistor Tr2 on the circuit operation power supply Vcc side is npn-type. The case of forming with a structure will be described. FIG. 10 is a circuit diagram of an electrostatic discharge protection circuit PC according to a fourth application example in the first embodiment of the present invention.

As shown in FIG. 10, in the electrostatic discharge protection circuit PC, the bipolar transistor Tr1 on the circuit reference power supply Vss side has a pnp structure, and the bipolar transistor Tr2 on the circuit operation power supply Vcc side has an npn structure. Is done. Bipolar transistor T
r1 is the bipolar transistor Tr shown in FIG.
2. It is formed with the same structure as any one of the bipolar transistor Tr2 shown in FIG. 6 and the bipolar transistor Tr1 shown in FIG. Bipolar transistor Tr2
Is formed with the same structure as the structure of the bipolar transistor Tr1 shown in FIG.

In the electrostatic breakdown prevention circuit PC configured as described above, the same effects as those of the electrostatic breakdown prevention circuit PC described in the first embodiment can be obtained.

Fifth Application Example A fifth application example describes a case where only the bipolar transistor Tr1 on the circuit reference power supply Vss side is formed in the electrostatic discharge protection circuit PC. FIG. 11 is a circuit diagram of an electrostatic discharge protection circuit PC according to a fifth application example in the first embodiment of the present invention.

As shown in FIG. 11, only the bipolar transistor Tr1 on the circuit reference power supply Vss side is formed in the electrostatic breakdown prevention circuit PC. The bipolar transistor Tr1 is formed of, for example, an npn type having a vertical structure. Since the bipolar transistor Tr1 can absorb both the positive surge current and the negative surge current, at least one bipolar transistor Tr1 is included in the electrostatic breakdown prevention circuit PC.
What is necessary is just to be formed. Moreover, since the bipolar transistor Tr1 electrically connects the p-type base region and the n-type emitter region and the resistor 21R is inserted between the two, the surge current absorbing capability is high.

In the electrostatic breakdown prevention circuit PC thus configured, the same effect as the electrostatic breakdown prevention circuit PC described in the first embodiment can be obtained.
Since the electrostatic breakdown prevention circuit PC can be constructed with the bipolar transistors Tr1, the area occupied by the electrostatic breakdown prevention circuit PC can be further reduced.

(Second Embodiment) In the second embodiment, the surge current absorption speed is increased in the electrostatic discharge protection circuit PC of the semiconductor integrated circuit device according to the first embodiment. A case where the electrostatic breakdown voltage is further improved will be described. FIG. 12 shows a bipolar transistor Tr1 of the electrostatic discharge protection circuit PC according to the second embodiment of the present invention.
FIG. 13 shows a bipolar transistor Tr.
1 is a plan view of FIG.

As shown in FIGS. 12 and 13, in the bipolar transistor Tr1 on the circuit reference power supply Vss side of the electrostatic discharge protection circuit PC, the n-type emitter region is formed by the divided n-type semiconductor region 23. That is, n is provided at an appropriate interval on the surface of the p-type semiconductor region 17 used as the intrinsic base region of the p-type base region.
A plurality of n-type semiconductor regions 23 forming a type emitter region are arranged.

A p-type semiconductor region 17 exists between the n-type semiconductor regions 23 divided into a plurality of n-type emitter regions, and the p-type semiconductor region 17 between the n-type semiconductor regions 23 is used as a base potential extraction region. A base carrier extraction path 17P reaching the p-type semiconductor region 24 is constructed. n
In the intrinsic base region immediately below the n-type emitter region, the base area is increased due to the increase of the planar area of the n-type emitter region and the reduction of the base width, and the extraction of the base carrier is deteriorated.
With the provision of the extraction path 17P, the extraction of the base carrier is performed smoothly. Therefore, the bipolar operation of the bipolar transistor Tr1 is reliably performed, so that the surge current can be immediately absorbed by the circuit reference power supply Vss.

The formation of the extraction path 17P by dividing the emitter region is particularly effective for a bipolar transistor having a vertical structure. In the semiconductor integrated circuit device according to the first embodiment, the vertical structure shown in FIG. The extraction path 17P can be formed also in the pnp type bipolar transistor Tr2 (first application example). Of course, this embodiment is
The present invention is also applicable to the respective electrostatic breakdown prevention circuits PC described in the first to fifth application examples of the first embodiment.

In the electrostatic breakdown prevention circuit PC configured as described above, the same effects as those obtained by the semiconductor integrated circuit device according to the first embodiment can be obtained.
Further, in the bipolar transistor Tr1 of the electrostatic discharge protection circuit PC, the base extraction region is formed along the extraction path 17P between the n-type semiconductor regions 23 divided into a plurality of n-type emitter regions, so that carriers in the p-type base region are reduced. Can be absorbed immediately. Therefore, the surge current input to the n-type collector region or the n-type emitter region of the bipolar transistor Tr1 can be immediately absorbed by the circuit reference power supply Vss, so that the electrostatic breakdown voltage can be improved.

The present invention is not limited to the above embodiment. For example, the present invention is also applicable to an electrostatic discharge protection circuit arranged between an output signal external connection terminal and a transistor at the final output stage of the internal integrated circuit IC.

[0095]

According to the present invention, there is provided a semiconductor integrated circuit capable of reducing the occupation area of the electrostatic breakdown prevention circuit while improving the electrostatic breakdown resistance of the electrostatic breakdown prevention circuit, improving the electrostatic breakdown resistance, and realizing an improvement in the degree of integration. Equipment can be provided.

Further, the present invention can provide a method of manufacturing a semiconductor integrated circuit device which can obtain the above-described effects and can reduce the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a vertical sectional structural view of a semiconductor integrated circuit device having an electrostatic discharge protection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an electrostatic discharge protection circuit.

FIG. 3 is a plan view of an electrostatic discharge protection circuit.

FIGS. 4A and 4B are circuit diagrams of a bipolar transistor Tr1 for explaining an electrostatic breakdown prevention operation, respectively.
(C) is a diagram showing the relationship between the resistance value of the resistance element and the electrostatic breakdown voltage in the electrostatic breakdown prevention circuit.

FIGS. 5A and 5B are longitudinal sectional structural views of a semiconductor integrated circuit device showing respective manufacturing steps for explaining a method of manufacturing a resistance element of an electrostatic discharge protection circuit.

FIG. 6 is a longitudinal sectional structural view of a bipolar transistor according to a first application example in the first embodiment of the present invention.

FIG. 7 is a circuit diagram of an electrostatic discharge protection circuit according to a second application example in the first embodiment of the present invention.

FIG. 8 is a circuit diagram of an electrostatic discharge protection circuit PC according to a third application example in the first embodiment of the present invention.

FIG. 9 is a vertical sectional view of a bipolar transistor on the circuit reference power supply side of the electrostatic breakdown prevention circuit.

FIG. 10 is a circuit diagram of an electrostatic discharge protection circuit PC according to a fourth application example in the first embodiment of the present invention.

FIG. 11 is a circuit diagram of an electrostatic discharge protection circuit PC according to a fifth application example in the first embodiment of the present invention.

FIG. 12 is a longitudinal sectional structural view of a bipolar transistor of an electrostatic discharge protection circuit according to a second embodiment of the present invention.

FIG. 13 is a plan view of a bipolar transistor of the electrostatic discharge protection circuit.

FIG. 14 is a circuit diagram of an electrostatic discharge protection circuit according to the related art.

FIG. 15 is a longitudinal sectional structural view of a main part of an electrostatic discharge protection circuit according to a conventional technique.

FIG. 16 is a plan view of a main part of an electrostatic discharge protection circuit according to the related art.

FIG. 17 is a plan view of a main part of an electrostatic discharge protection circuit illustrating another structure according to the related art.

FIG. 18 is a longitudinal sectional structural view of a main part of an electrostatic discharge protection circuit illustrating another structure according to the related art.

[Explanation of symbols]

Reference Signs List 10 semiconductor substrate 10A single-crystal silicon substrate 10B epitaxial layer 11, 12, 15, 16, 17, 22, 23, 24, 3
Reference Signs List 1 semiconductor region 13, 14 well region 21 gate electrode or emitter electrode 21R, R, R1, R2 resistance element 26, 28 wiring 17P extraction path BP external connection terminal PC electrostatic discharge prevention circuit IC internal integrated circuit Tr bipolar transistor Q MISFET

Claims (5)

[Claims] 1. A semiconductor integrated circuit device having an electrostatic breakdown prevention circuit between an external connection terminal and an internal integrated circuit, wherein a surge current input to the external connection terminal is supplied to the electrostatic breakdown prevention circuit by a bipolar operation. A semiconductor integrated circuit device comprising a bipolar transistor that absorbs power. 2. The bipolar transistor is inserted between at least one of the external connection terminal and a circuit reference power supply, at least one of the external connection terminal and a circuit operation power supply, or both. The semiconductor integrated circuit device according to claim 1. 3. The bipolar transistor according to claim 1, wherein the base region and the emitter region of the bipolar transistor are short-circuited, or a resistance element for reducing electrostatic breakdown voltage is inserted in series between the base region and the emitter region. The semiconductor integrated circuit device according to claim 1. 4. The semiconductor integrated circuit device according to claim 1, wherein an emitter region of said bipolar transistor is divided into a plurality. 5. A method of manufacturing a semiconductor integrated circuit device provided with an electrostatic discharge protection circuit between an external connection terminal and an internal integrated circuit, wherein a transistor for constructing the internal integrated circuit is formed and the external connection terminal is connected to the external connection terminal. Forming a bipolar transistor of an electrostatic discharge prevention circuit that absorbs an input surge current into a power supply by a bipolar operation; forming an electrode of a transistor constituting the internal integrated circuit; and forming a base of the bipolar transistor of the electrostatic discharge prevention circuit. Forming a resistor between the region and the emitter region to reduce the electrostatic breakdown voltage with the same conductive layer as the electrode.