TWI753751B - Electrostatic discharge protection apparatus and operating method - Google Patents

Abstract

An ESD protection device includes a semiconductor substrate, a first well, a second well, a third well, a first doping area, a second doping area, a third doping area and a fourth doping area. The first well, the second well and the third well are disposed in the semiconductor substrate, and the third well area is directly coupled between the first well and the second well. The first well and the second well have a first conductivity, and the third well has a second conductivity. The first doping region having the first conductivity is disposed in the first well. The second doping region having a second conductivity is disposed in the third well, and the first doping region and the second doping region are isolated from each other. The third doping region and the fourth doping region have the first conductivity and the second conductivity, respectively, and are disposed in the second well and isolated from each other. The second doping region and the third doping region are electrically coupled. The first well, the second well, the third well and the fourth doping region form a parasitic SCR.

Description

Electrostatic discharge protection device and operation method thereof

The present invention relates to a semiconductor device, and more particularly, to an electrostatic discharge protection device and an operation method thereof.

Electrostatic discharges result from powerful current pulses introduced by high voltage discharges over a short period of time (typically within 100 nanoseconds). Integrated circuits and semiconductor components are quite sensitive to electrostatic discharge. Especially during component installation, because humans or machines touch the contact pins, strong current pulses often pass through the integrated circuit, resulting in component failure. There is therefore a need to provide effective electrostatic discharge protection devices for integrated circuits.

Parasitic Silicon Controlled Rectifier (SCR) is an on-chip semiconductor ESD protection device, which can be turned on by snapback when ESD occurs, conducting ESD current to ground to achieve the protection function of electrostatic discharge. Therefore, SCR is one of the electrostatic discharge protection devices widely used in the industry. However, when the parasitic silicon-controlled rectifier cannot be turned on smoothly, the capability of current shunt cannot be improved.

Therefore, there is a need to provide an advanced electrostatic discharge protection device and an operating method thereof to improve the problems faced by the prior art.

The present invention relates to an electrostatic discharge protection device and an operation method thereof, which can solve the problem that the conventional parasitic silicon-controlled rectifier cannot be turned on smoothly, and can reduce the effective resistance of the electrostatic discharge protection device.

According to an aspect of the present invention, an electrostatic discharge protection device is provided, comprising a semiconductor substrate, a first well region, a second well region, a third well region, a first doped region, a second doped region, and a third doped region region and a fourth doped region. The first well region, the second well region and the third well region are located in the semiconductor substrate, and the third well region is directly coupled between the first well region and the second well region. The first well region and the second well region have a first electrical property, and the third well region has a second electrical property. The first doped region has a first electrical property and is located in the first well region. The second doping region has the second electrical property, is located in the third well region, and the first doping region and the second doping region are isolated from each other. The third doping region and the fourth doping region respectively have the first electrical property and the second electrical property, and are located in the second well region and isolated from each other, and the second doping region and the third doping region are electrically coupled. The first well region, the second well region, the third well region and the fourth doped region form a parasitic silicon controlled rectifier.

According to an aspect of the present invention, an operation method of an electrostatic discharge protection device is provided, which includes the following steps. An electrostatic discharge protection device is provided. The electrostatic discharge protection device is electrically connected with an internal circuit. The electrostatic discharge protection device includes a parasitic silicon-controlled rectifier and a diode string connected to each other. When an electrostatic discharge stress is applied to the internal circuit, the electrostatic discharge current is guided from one bonding pad to another bonding pad by the electrostatic discharge protection device.

In order to have a better understanding of the above-mentioned and other aspects of the present invention, the following specific examples are given and described in detail in conjunction with the accompanying drawings as follows:

100, 200, 300, 400: Electrostatic discharge protection devices

101: Semiconductor substrates

101a: Deep N-well area

101b: N-well area

101c: N-well area

102: The first well area

103: The second well area

104: The third well area

106, 109: Solder pads

107: Isolator

111, 211, 311: first doped region

113,313: Second Doping Region

115: Metal Wire

121,321: The third doped region

123: the fourth doped region

112, 116, 212, 214, 312, 314: Diodes

114,414: Diode String

118,218,318,418: Parasitic Silicon Controlled Rectifiers

316: Junction

FIG. 1A is a schematic cross-sectional view of an electrostatic discharge protection device according to an embodiment of the present invention; FIG. 1B is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device of FIG. 1A ; and FIG. 2A is another schematic diagram of the present invention. Figure 2B is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device in Figure 2A; Figure 3A is a cross-section of an electrostatic discharge protection device according to another embodiment of the present invention Schematic diagrams; FIG. 3B is a schematic diagram of an equivalent circuit of the electrostatic discharge protection device of FIG. 3A ; and FIG. 4 is a schematic cross-sectional view of an electrostatic discharge protection device of a comparative example.

The following examples are provided for detailed description, and the examples are only used as examples to illustrate, and are not intended to limit the scope of protection of the present invention. In the following, the same/similar symbols are used to represent the same/similar elements for description.

first embodiment

Please refer to FIGS. 1A and 1B , which respectively illustrate a cross-sectional schematic diagram of an electrostatic discharge protection device 100 according to an embodiment of the present invention and a schematic diagram of an equivalent circuit thereof.

According to an embodiment of the present invention, the ESD protection device 100 includes a semiconductor substrate 101 , a first well region 102 , a second well region 103 , a third well region 104 , a first doped region 111 , and a second doped region 113 , the third doped region 121 and the fourth doped region 123 .

In one embodiment, the semiconductor substrate 101 may be made of any suitable base semiconductor (eg, crystalline silicon or germanium), compound semiconductors (eg, silicon carbide, gallium arsenide, gallium phosphide, iodine phosphide, iodine arsenide, and / or antimony iodine) or a combination of the above. The semiconductor substrate 101 is, for example, a P-type substrate. The semiconductor substrate 101 includes a first well region 102 and a second well region 103 with P-type conductivity and a third well region 104 with N-type conductivity, wherein the third well region 104 is coupled to the first well region 102 and between the second well area 103 . In addition, the semiconductor substrate 101 is isolated from the first well region 102, the second well region 103 and the third well region 104, for example, by a deep N-well region 101a. Besides, the semiconductor substrate 101 and the first well region 102 are isolated, for example, by an N-well region 101b, and the semiconductor substrate 101 and the second well region 103 are isolated, for example, by an N-well region 101c.

The first doped region 111 has P-type conductivity and is located in the first well region 102 . The first doping region 111 has a doping concentration (represented by P+) substantially greater than that of the first well region 102 . The second doped region 113 has an N-type conductivity and is located in the third well region 104 . The second doped region 113 has a doping concentration (represented by N+) substantially greater than that of the third well region 104 . In one embodiment, the first doping region 111 and the second doping region 113 may have a doping concentration of 10 ¹⁵ /cm ² , respectively. The first well region 102 and the third well region 104 may have a doping concentration of 10 ¹³ /cm ² .

The first doped region 111 can be connected to the voltage source 105 through a pad 106 . During normal voltage operation (eg, the operating voltage is about 2V), the voltage can be applied to the first doped region 111 by the voltage source 105 . A plurality of spacers 107 can be respectively disposed in the ESD protection device 100 . The spacers 107 are located between the first doping region 111 and the second doping region 113 , the second doping region 113 and the third doping region 121 , for example. between the third doping region 121 and the fourth doping region 123 to perform the function of electrical isolation.

The third doped region 121 has P-type conductivity and is located in the second well region 103 . The third doping region 121 has a doping concentration (represented by P+) substantially greater than that of the second well region 103 . The fourth doped region 123 has N-type conductivity and is located in the second well region 103 . The fourth doping region 123 has a doping concentration (represented by N+) substantially greater than that of the second well region 103 . In one embodiment, the third doping region 121 and the fourth doping region 123 may have a doping concentration of 10 ¹⁵ /cm ² respectively, and the second well region 103 may have a doping concentration of 10 ¹³ /cm ² .

It can be seen from FIGS. 1A and 1B that the second doped region 113 and the third doped region 121 are electrically coupled by a metal wire 115 . The first well region 102 and the third well region 104 are directly connected and contacted with each other to form a diode 112 , the second well region 103 and the fourth doped region 123 are directly connected and contacted with each other to form another diode 116 , The two diodes are electrically coupled by a metal wire 115 to form a diode string 114 . That is, the ESD current can flow into the diode string 114 from the pad 106 through the first doped region 111 and then into the pad 109 to protect the internal circuits in the integrated circuit from being damaged by ESD.

1A and 1B, the first well region 102, the third well region 104 and the second well region 103 form a PNP bipolar transistor (Bipolar Junction Transistor) with a P-type majority carrier. BJT) parasitic circuit. The third well region 104, the second well region 103 and the fourth doped region 123 form an NPN bipolar transistor parasitic circuit with N-type majority carriers. The collector of the parasitic circuit of the PNP bipolar transistor is connected to the base of the parasitic circuit of the NPN bipolar transistor; and the base of the parasitic circuit of the PNP bipolar transistor and the collector of the parasitic circuit of the NPN bipolar transistor A parasitic silicon-controlled rectifier 118 is formed in the semiconductor substrate 101 . The electrostatic discharge protection device In 100 , the first doped region 111 is the anode of the parasitic silicon-controlled rectifier 118 , and the fourth doped region 123 is the cathode of the parasitic silicon-controlled rectifier 118 .

In one embodiment, when ESD stress is applied to the internal circuit, the ESD stress flows from the pad 106 to the pad 109 through the two forward diodes 112 and 116 , and the pad 106 is a PNP transistor The base-emitter, the pad 109 is the base-emitter of the NPN transistor, when the pads 106 and 109 are turned on in the forward direction, the parasitic silicon-controlled rectifier 118 is turned on, and there is no need to generate a collapse Electron hole. Therefore, in addition to flowing into the diode string 114 , the electrostatic discharge current can also flow into the parasitic silicon-controlled rectifier 118 from the bonding pad 106 through the first doped region 111 , and into the bonding pad 109 through the fourth doped region 123 .

Please refer to FIG. 4 , which shows a schematic cross-sectional view of an electrostatic discharge protection device 400 of a comparative example. Compared with the first embodiment, the comparative example does not have the ESD protection device coupled between the first well region 102 and the second well region 103 . Although the third well region 104 can form a parasitic silicon-controlled rectifier 418 (P+/N-well region/P-well region/N-well region) in the semiconductor substrate of the comparative example, one of the diodes (P+/N-Well) is not the base-emitter of the NPN transistor (N-well/P-well/N-well) in the parasitic silicon-controlled rectifier 418, so when the diode string 414 is turned on, the parasitic silicon-controlled rectifier 418 could not be turned on smoothly. In this embodiment, a parasitic silicon-controlled rectifier 118 (P-well/N-well/P-well/N+) is formed in the semiconductor substrate 101 , and the parasitic silicon-controlled rectifier 118 is connected in parallel with the diode string 114 The provision of two ESD paths improves the current shunting capability, increases the effective circuit paths for ESD, reduces the effective resistance of the ESD protection device 100, and does not need to additionally provide another ESD protection device that occupies a larger layout space. ESD protection components to reduce the overall layout size of integrated circuits.

Second Embodiment

Please refer to FIGS. 2A and 2B, which respectively illustrate a cross-sectional schematic diagram of an electrostatic discharge protection device 200 according to another embodiment of the present invention and a schematic diagram of an equivalent circuit thereof. The structure of the ESD protection device 200 is similar to that of the ESD protection device 100 shown in FIG. 1A , except that a part of the first doped region 211 is located in the first well region 102 , and another part of the first doped region 211 is located in the first well region 102 . The third well area 104 . The first doped region 211 is similar to the first doped region 111 .

In the ESD protection device 200 , there are two diodes connected in parallel, which are coupled by the first well region 102 and the third well region 104 to form a diode 212 , and the first doped region 211 is used to form a diode 212 . And the third well region 104 is coupled to form another diode 214, thereby increasing the effective circuit path of electrostatic discharge.

In addition, when the ESD stress is applied to the internal circuit protected by the ESD protection device 200 , the ESD current not only flows into the diode strings 212 , 214 and 116 , but also can be separated from the pad 106 through the first doped region 211 . into the first well region 102 and the third well region 104 , wherein the first well region 102 , the third well region 104 , the second well region 103 and the fourth doped region 123 constitute a first branch of a parasitic silicon controlled rectifier 218 , and the first doping region 211, the third well region 104, the second well region 103 and the fourth doping region 123 constitute the second branch of the parasitic silicon-controlled rectifier 218, and the first branch and the second branch are connected in parallel, Further, the effective circuit path of the electrostatic discharge is increased, and then the electrostatic discharge current is introduced into the bonding pad 109 through the fourth doping region 123 .

In the present embodiment, the second branch of the parasitic silicon-controlled rectifier 218 includes a PNP bipolar transistor parasitic circuit formed by the first doping region 211 , the third well region 104 and the second well region 103 and a parasitic circuit formed by the third The well region 104, the second well region 103 and the fourth doped region 123 are formed of an NPN bipolar transistor parasitic circuit. The collector of the parasitic circuit of the PNP bipolar transistor is connected to the base of the parasitic circuit of the NPN bipolar transistor; and the base of the parasitic circuit of the PNP bipolar transistor and the collector of the parasitic circuit of the NPN bipolar transistor A second shunt of the parasitic silicon-controlled rectifier 218 is formed in the semiconductor substrate 101 to improve the current shunt capability.

Referring to FIG. 4, the comparative example does not have the third well region 104 coupled between the first well region 102 and the second well region 103 compared to the second embodiment, although the semiconductor substrate of the comparative example can A parasitic silicon-controlled rectifier 418 (P+/N-well/P-well/N-well) is formed, but one of the diodes (P+/N-Well) is not the NPN circuit in the parasitic silicon-controlled rectifier 418. The base-emitter of the crystal (N-well/P-well/N-well), so when the diode string 414 (P+/N-well and another P+/N-well) is turned on, the parasitic silicon The controlled rectifier 418 cannot be turned on normally. In this embodiment, parasitic silicon-controlled rectifiers 218 with two shunts are formed in the semiconductor substrate 101 (P-well/N-well/P-well/N+ and P+/N-well/P-well). /N+), and the parasitic silicon-controlled rectifier 218 is connected in parallel with the diode strings 212, 214, 116 to provide two or more ESD paths, improving the current shunting capability and increasing the effective circuit path for ESD , the effective resistance of the ESD protection device 200 is reduced, and there is no need to additionally provide another ESD protection element that occupies a larger layout space, so as to reduce the overall layout size of the integrated circuit.

Third Embodiment

Please refer to FIGS. 3A and 3B , which respectively illustrate a cross-sectional schematic diagram of an electrostatic discharge protection device according to another embodiment of the present invention and a schematic diagram of an equivalent circuit thereof. The structure of the electrostatic discharge protection device 300 is similar to that of the electrostatic discharge protection device shown in FIG. 1A 100, except that a part of the first doped region 311 is located in the first well region 102, another part of the first doped region 311 is located in the third well region 104, and the second doped region 313 and the third doped region 321 They are directly connected to each other to form a junction 316 . The first doping region 311 , the second doping region 313 and the third doping region 321 are similar to the first doping region 111 , the second doping region 113 and the third doping region 121 .

In the ESD protection device 300 , there are two diodes connected in parallel, which are coupled by the first well region 102 and the third well region 104 to form a diode 312 , and the first doped region 311 is used to form a diode 312 . and the third well region 104 is coupled to form another diode 314, thereby increasing the effective circuit path of electrostatic discharge. In addition, after removing the spacer between the second well region 103 and the third well region 104, the second doping region 313 and the third doping region 321 are directly connected to each other to form a junction 316, thereby reducing electrostatic discharge The protection device 300 occupies a larger layout space to reduce the overall layout size of the integrated circuit.

In addition, when ESD stress is applied to the internal circuit protected by the ESD protection device 300 , the ESD current not only flows into the diode strings 312 , 314 , and 116 , but also can be separated from the pad 106 via the first doped region 311 . into the first well region 102 and the third well region 104 , wherein the first well region 102 , the third well region 104 , the second well region 103 and the fourth doped region 123 constitute a first branch of a parasitic silicon controlled rectifier 318 , and the first doping region 311, the third well region 104, the second well region 103 and the fourth doping region 123 constitute the second branch of the parasitic silicon-controlled rectifier 318, the first branch is connected in parallel with the second branch, Further, the effective circuit path of the electrostatic discharge is increased, and then the electrostatic discharge current is introduced into the bonding pad 109 through the fourth doping region 123 .

Referring to FIG. 4, the comparative example does not have the third well region 104 coupled between the first well region 102 and the second well region 103, and the second doped region 313 and A junction 316 is not formed in the third doped region 321, although a parasitic silicon controlled rectifier 418 (P+/N-well/P-well/N-well) can be formed in the semiconductor substrate of the comparative example, but One of the diodes (P+/N-Well) is not the base-emitter of the NPN transistor (N-well/P-well/N-well) in the parasitic silicon-controlled rectifier 418, so when the diode string When 414 (P+/N-well and another P+/N-well) are turned on, the parasitic silicon-controlled rectifier 418 cannot be turned on smoothly. In this embodiment, a parasitic silicon-controlled rectifier 318 with two shunts is formed in the semiconductor substrate 101 (P-well/N-well/P-well/N+ and P+/N-well/P-well). /N+), and the parasitic silicon-controlled rectifier 318 is connected in parallel with the diode strings 312, 314, 116 to provide two or more electrostatic discharge paths, which improves the current shunt capability, increases the effective circuit path of electrostatic discharge, and protects against electrostatic discharge. The effective resistance of the device 300 is reduced, and there is no need to additionally provide another ESD protection element that occupies a larger layout space, thereby reducing the overall layout size of the integrated circuit.

To sum up, although the present invention has been disclosed by the above embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

100: Electrostatic discharge protection device

101: Semiconductor substrates

101a: Deep N-well area

101b: N-well area

101c: N-well area

102: The first well area

103: The second well area

104: The third well area

106, 109: Solder pads

107: Isolator

111: the first doping region

113: the second doping region

115: Metal Wire

121: the third doping region

123: the fourth doped region

Claims (10)

An electrostatic discharge protection device, comprising: a semiconductor substrate; a first well region with a first electrical property; a second well region with the first electrical property; a third well region with a second electrical property and the first well region, the second well region and the third well region are located in the semiconductor substrate, and the third well region is directly coupled between the first well region and the second well region ; a first doped region with the first electrical property and located in the first well region; a second doped region with the second electrical property located in the third well region and the The first doped region and the second doped region are isolated from each other; a third doped region with the first electrical property is located in the second well region, wherein the second doped region and the third doped region The impurity region is electrically coupled; and a fourth doping region with the second electrical property is located in the second well region and isolated from the third doping region; wherein, the first well region, the first well region, the third doping region The second well region, the third well region and the fourth doped region form a parasitic silicon controlled rectifier, wherein the first well region and the third well region are directly connected and in contact with each other to form a first diode, the The second well region and the fourth doped region are directly connected and in contact with each other to form a second diode, and the first diode and the second diode form a diode string. The protection device of claim 1, wherein the first doped region is an anode of the parasitic silicon-controlled rectifier, and the fourth doped region is a cathode of the parasitic silicon-controlled rectifier. The protection device of claim 1, wherein the parasitic silicon-controlled rectifier comprises a PNP bipolar transistor parasitic circuit formed by the first well region, the third well region and the second well region and a parasitic circuit formed by the third well region An NPN bipolar transistor parasitic circuit formed by the well region, the second well region and the fourth doped region. The protection device of claim 1, wherein the parasitic silicon-controlled rectifier is connected in series and parallel to the diode. The protection device of claim 1, wherein a part of the first doped region is located in the first well region, and another part of the first doped region is located in the third well region. The protection device of claim 5, wherein the first well region, the second well region, the third well region and the fourth doped region constitute a first shunt of the parasitic silicon controlled rectifier, the first well region A doping region, the third well region, the second well region and the fourth doping region constitute a second branch of the parasitic silicon-controlled rectifier, and the first branch is connected in parallel with the second branch. The protection device of claim 5, wherein the first well region and the third well region are coupled to form the first diode, and the first doped region and the third well region are coupled to form the The other diode is connected in parallel with the first diode. The protection device of claim 7, wherein the parasitic silicon-controlled rectifier is connected in parallel with the two diodes. The protection device of claim 1, wherein the second doped region and the third doped region are directly connected to each other to form a junction. An operation method of an electrostatic discharge protection device, comprising: providing the electrostatic discharge protection device according to claim 1, the electrostatic discharge protection device is electrically connected with an internal circuit, the electrostatic discharge protection device comprises a parasitic silicon controlled rectifier and a The diode strings are connected to each other; and when an electrostatic discharge stress is applied to the internal circuit, the electrostatic discharge current is guided from one pad to another by the electrostatic discharge protection device.

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