TW201336072A - High voltage semiconductor element and operating method thereof - Google Patents

Abstract

A high voltage semiconductor element and an operating method thereof are provided. The high voltage semiconductor element includes a high voltage metal-oxide-semiconductor transistor (HVMOS) and a NPN type electro-static discharge bipolar transistor (ESD BJT). The HVMOS has a drain and a source. The NPN type ESD BJT has a collector and an emitter. The collector is electronically connected to the drain. The emitter is electronically connected to the source.

Description

High voltage semiconductor component and method of operating same

The present invention relates to a semiconductor device and a method of operating the same, and more particularly to a high voltage semiconductor device and method of operation thereof.

With the development of semiconductor technology, a power integrated circuit process integration technology (Bipolar CMOS DMOS, BCD) has been widely used in high voltage semiconductor components. In the power integrated circuit process integration technology (BCD) process, the operating voltage is getting higher and higher, and the electrostatic-static discharge (ESD) on the wafer becomes quite important.

High voltage semiconductor components typically have low on-state resistance (Rdson) characteristics. Therefore, in the event of an electrostatic event, the electrostatic current tends to concentrate on the surface or the edge of the source. High currents and high electric fields will cause physical damage to the surface of the junction region.

Also, based on the electrical requirements of low on-resistance. High voltage semiconductor components cannot add surface or sidewalls. Therefore, how to design a better electrostatic protection structure is a severe challenge.

Further, another characteristic of the high voltage semiconductor element is that the breakdown voltage of the high voltage semiconductor element is always higher than the operation voltage. The trigger voltage (Vt1) is usually higher than the breakdown voltage. Therefore, during an electrostatic event, the protection component or internal circuitry is typically at risk of damage before the high voltage semiconductor component initiates electrostatic protection. In order to reduce the trigger voltage, an additional electrostatic protection circuit is usually required.

Furthermore, high voltage semiconductor components typically have a low holding voltage. High voltage components can be triggered by unwanted noise, power-on peak voltage or serge voltage, and latch-up occurs during normal operation.

Moreover, high voltage semiconductor components typically have a field plate effect. The electric field distribution is easily broken. Therefore, in an electrostatic event, the electrostatic current tends to concentrate on the surface or the edge of the drain.

There are some electrostatic protection practices, but these add extra reticle and process steps. Another method of electrostatic protection of high voltage semiconductor components is to add additional components that are only used for electrostatic protection. Such additional components are typically large-sized diodes, metal oxide semiconductor transistors (MOS) or silicon-controlled rectifiers (SCRs) that add surface or sidewalls. Among them, the controlled rectifier has the characteristics of low holding voltage, so the latch-up effect is easy to occur during normal operation.

Based on the above various phenomena, high-voltage semiconductor components have formed a bottleneck in the development of technology in terms of electrostatic protection measures, and it is urgent for researchers to break through this technical difficulty.

The present invention relates to a high voltage semiconductor device and a method of operating the same, which utilizes a high voltage metal-oxide-semiconductor transistor (HVMOS) and an electro-static discharge bipolar transistor (ESD). BJT) technology that integrates into a single component not only avoids latch-up, but also does not increase the mask and process steps, nor does it add excessive volume.

According to an aspect of the invention, a high voltage semiconductor component is proposed. The high voltage semiconductor device includes a high voltage metal-oxide-semiconductor transistor (HVMOS) and an NPN type electrostatic-electrostatic bipolar transistor (ESD BJT). The high voltage MOS transistor has a drain and a source. The NPN type electrostatic protection bipolar transistor has a first collector and a first emitter (Emitter). The first epipolar is electrically connected to the bungee. The first emitter is electrically connected to the source.

According to another aspect of the present invention, a method of operating a high voltage semiconductor device is presented. The method of operating a high voltage semiconductor device includes the following steps. A high voltage semiconductor component is provided. The high voltage semiconductor device includes a high voltage metal-oxide-semiconductor transistor (HVMOS) and an NPN type electrostatic-electrostatic bipolar transistor (ESD BJT). The high voltage MOS transistor has a drain, a source, and a gate. The NPN type electrostatic protection bipolar transistor has a first collector and a first emitter (Emitter). The first epipolar is electrically connected to the bungee. The first emitter is electrically connected to the source. When the high voltage MOS semi-transistor is driven, an operating current flows through the high voltage MOS semi-transistor. When the high voltage MOS transistor is turned off and an electrostatic event occurs, an electrostatic current flows through the NPN type electrostatic protection bipolar transistor.

In order to make the above-mentioned contents of the present invention more comprehensible, various embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

In the following, various embodiments are described in detail, which are integrated with a high voltage metal-oxide-semiconductor transistor (HVMOS) and an electro-static discharge bipolar transistor (ESD BJT). The single-element technology not only avoids the latch-up, but also increases the mask and process steps, and does not add excessive volume. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. Further, the drawings in the embodiments are omitted to partially illustrate the technical features of the present invention.

First embodiment

Referring to FIG. 1, a circuit diagram of the high voltage semiconductor device 100 of the first embodiment is shown. The high voltage semiconductor device 100 includes a high voltage MOSMOS 110 and an NPN type electrostatic protection bipolar transistor (ESD BJT) 120. The high voltage MOS transistor 110 acts as a high voltage current switch. The high voltage MOS transistor 110 has a drain D0, a source S0, a gate G0, and a base B0. The gate G0 is electrically connected to an internal circuit 900. When the input voltage of the gate G0 is higher than a driving voltage (Trigger Voltage), the high voltage MOS transistor 110 is driven.

The NPN type electrostatic protection bipolar transistor 120 is used to absorb unnecessary electrostatic current to prevent the electrostatic current from damaging the high voltage MOS transistor 110. The NPN type electrostatic protection bipolar transistor 120 has a collector C1, an emitter E1 and a base B1, and the collector C1 is electrically connected to the drain D0, and the emitter E1 is electrically. Connected to source S0.

In this embodiment, the high voltage MOS transistor 110 and the NPN type electrostatic protection bipolar transistor 120 can be integrated into a single component through a power integrated circuit process integration technology (Bipolar CMOS DMOS, BCD). Closely connected and share part of the structure. Since the high voltage semiconductor device 100 of the present embodiment can be fabricated using Power Integrated Circuit Process Integration Technology (BCD), no additional mask or process steps are required.

As for the method of operating the high voltage semiconductor device 100, the high voltage semiconductor device 100 is first provided. Then, when the high voltage MOS transistor 110 is driven, since the high voltage MOS transistor 110 has a low on-state resistance (Rdson) and a high breakdown voltage, the operating current I0 flows through The high voltage MOS transistor 110 does not flow through the NPN type electrostatic protection bipolar transistor 120. As a result, the high voltage MOS transistor 110 is normally operated.

When the high voltage MOS transistor 110 is turned off and an electrostatic event occurs, the NPN type electrostatic protection bipolar transistor 120 is more easily activated than the high voltage MOS transistor 110, and the electrostatic current I1 flows through the NPN type electrostatic protection pair. The polar transistor 120 does not flow through the high voltage MOS transistor 110. As a result, the high voltage MOS transistor 110 is not damaged.

Referring to FIG. 2, a schematic diagram of the high voltage semiconductor device 100 of the first embodiment is shown. The high voltage semiconductor device 100 includes a P-type substrate PS, at least one N-type barrier layer NBL, at least one N-type well NW, at least one P-type well PW, at least one P-type doped region PR, and a plurality of N-type heavily doped regions. Zones N1, N2, N3, a plurality of P-type heavily doped regions P1, P2, a plurality of insulating layers FO and a plurality of electrode layers EL.

The P-type substrate PS, the N-type well NW, the P-type doped region PR, the N-type heavily doped region N1, the N2, the P-type heavily doped region P1, and the electrode layer EL constitute a high voltage MOS semi-transistor 110. The N-type heavily doped region N1 is the source S0, the N-type heavily doped region N2 is the drain D0, the P-type heavily doped region P1 is the base B0, and the electrode layer EL is the gate G0.

N-type well NW, P-type well PW, N-type heavily doped area N2, N3 and P-type heavily doped area P2 constitute NPN type electrostatic protection bipolar transistor 120. The N-type heavily doped region N2 is the collector C1, the N-type heavily doped region N3 is the emitter E1, and the P-type heavily doped region P2 is the base B1.

As shown in Fig. 2, the high voltage MOS semi-transistor 110 and the NPN-type electrostatic protection bipolar transistor 120 are integrated in the same N-type well NW, and the high-voltage MOS semi-transistor 110 has a drain D0 and an NPN type electrostatic protection. The collector C1 of the bipolar transistor 120 is the same N-type heavily doped region N2. That is to say, the high voltage MOS transistor 110 and the NPN type electrostatic protection bipolar transistor 120 not only share the same N-type well NW, but also share the same N-type heavily doped region N2. The wires between the high voltage MOS transistor 110 and the NPN type electrostatic protection bipolar transistor 120 can be minimized to avoid any unnecessary electrostatic current I1 (shown in Figure 1).

In addition, please refer to Figure 2, N-well NW, P-well PW, N-doped region N3, P-type heavily doped region P2 and N-type barrier layer NBL also form another NPN-type electrostatic protection bipolar Crystal 180. A plurality of NPN-type electrostatic protection bipolar transistors 120 and 180 are formed in this region, and the electrostatic protection capability can be effectively improved.

In the present embodiment, the high voltage semiconductor device 100 is electrostatically protected by the NPN type electrostatic protection bipolar transistors 120 and 180, instead of using a Silicon Controlled Rectifier (SCR) for electrostatic protection, so that the high voltage MOS transistor 110 is able to have a higher holding voltage to avoid latch-up.

In addition, the present embodiment integrates the high voltage MOS transistor 110 and the NPN type electrostatic protection bipolar transistor 120 into a single component as compared with the external component or the design of increasing the contact area, which can greatly reduce the volume of the high voltage semiconductor component 100. .

Second embodiment

Referring to FIG. 3, a circuit diagram of the high voltage semiconductor device 200 of the second embodiment is shown. The high voltage semiconductor device 200 of the present embodiment and the method of operating the same are different from the high voltage semiconductor device 100 of the first embodiment and the method of operating the same. The high voltage semiconductor device 200 further includes a PNP type electrostatic protection bipolar transistor 230, and the rest are the same and will not be repeatedly described.

As shown in FIG. 3, the PNP type electrostatic protection bipolar transistor 230 is connected in parallel with the NPN type electrostatic protection bipolar transistor 120. The PNP type electrostatic protection bipolar transistor 230 has a collector C2, an emitter E2 and a base B2. The emitter E2 is electrically connected to the drain D0 and the collector C1, and the collector C2 is electrically connected to the source S0. And the emitter E1.

In this embodiment, the high voltage MOS transistor 110, the NPN type electrostatic protection bipolar transistor 120, and the PNP type electrostatic protection bipolar transistor 230 can be integrated into a single unit through a power integrated circuit process integration technology (BCD). In the component. The three are closely connected and share part of the structure. Since the high voltage semiconductor device 200 of the present embodiment can be fabricated using Power Integrated Circuit Process Integration Technology (BCD), no additional mask or process steps are required.

In the operation method of the high-voltage semiconductor device 200 of the present embodiment, in the event of an electrostatic event, the electrostatic current I1 can flow through the NPN-type electrostatic protection bipolar transistor 120, and can also flow through the PNP-type electrostatic protection bipolar battery. The crystal 230 is not passed through the high voltage MOS transistor 110. As a result, the high voltage MOS transistor 110 is not damaged.

Referring to FIG. 4, a schematic diagram of the high voltage semiconductor device 200 of the second embodiment is shown. In the present embodiment, the N-type heavily doped region N2 (shown in FIG. 2) shared by the first embodiment is divided into an N-type heavily doped region N3 and an N-type heavily doped region N4. An adjacent P-type heavily doped region P3 is added between the two.

The N-well NW, the P-well PW, the P-type heavily doped region P2, P3, and the N-type heavily doped region N4 constitute a PNP-type electrostatic protection bipolar transistor 230. The P-type heavily doped region P3 is the emitter E2, the N-type heavily doped region N4 is the base B2, and the P-type heavily doped region P2 is the collector C2.

As shown in FIG. 4, the high voltage MOS transistor 110, the NPN type electrostatic protection bipolar transistor 120, and the PNP type electrostatic protection bipolar transistor 230 are disposed in the same N-type well NW. The emitter E2 of the PNP type electrostatic protection bipolar transistor 230, the base B2 and the collector C1 of the NPN type electrostatic protection bipolar transistor 120 are disposed in the same N-type well NW. The collector C2 of the PNP type electrostatic protection bipolar transistor 230 and the base B1 and the emitter E1 of the NPN type electrostatic protection bipolar transistor 120 are disposed in the same P-type well PW.

That is to say, the NPN type electrostatic protection bipolar transistor 120 and the PNP type electrostatic protection bipolar transistor 230 share the same N-type well NW, and also share the same N-type heavily doped area N4, and also share the same P-type weight. Doped region P3. The wire between the high voltage MOS transistor 110, the NPN type electrostatic protection bipolar transistor 120 and the PNP type electrostatic protection bipolar transistor 230 can be minimized to avoid any unnecessary electrostatic current I1 (shown in Figure 1).

In the present embodiment, the high voltage semiconductor element 200 is electrostatically protected by an NPN type electrostatic protection bipolar transistor 120 and a PNP type electrostatic protection bipolar transistor 230 instead of using a voltage controlled rectifier (SCR) for electrostatic protection, so that the high voltage gold The oxygen semiconductor 110 has a higher holding voltage to avoid latch-up effects.

In addition, the present embodiment integrates the high voltage MOS transistor 110, the NPN type electrostatic protection bipolar transistor 120, 180, and the PNP type electrostatic protection bipolar transistor 230 into a single device as compared with the external component or the design of increasing the contact area. Within the device, the volume of the high voltage semiconductor device 200 can be greatly reduced.

In view of the above, the present invention has been disclosed in various embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100, 200. . . High voltage semiconductor component

110. . . High voltage gold oxide semi-transistor

120, 180. . . NPN type electrostatic protection bipolar transistor

230. . . PNP type electrostatic protection bipolar transistor

900. . . Internal circuit

B0, B1, B2. . . Base

C1, C2. . . Collector

D0. . . Bungee

E1, E2. . . Emitter

F0. . . Insulation

G0. . . Gate

I0. . . Operating current

I1. . . Electrostatic current

N1, N2, N3, N4. . . N heavy doped area

NBL. . . N-type barrier layer

NW. . . N-type well

P1, P2, P3. . . P-type heavily doped region

PR. . . P-doped region

PS. . . P-type substrate

PW. . . P-well

S0. . . Source

Fig. 1 is a circuit diagram showing a high voltage semiconductor device of the first embodiment.

Fig. 2 is a schematic view showing the high voltage semiconductor device of the first embodiment.

Fig. 3 is a circuit diagram showing the high voltage semiconductor device of the second embodiment.

4 is a schematic view showing the high voltage semiconductor device of the second embodiment.

100. . . High voltage semiconductor component

110. . . High voltage gold oxide semi-transistor

120. . . NPN type electrostatic protection bipolar transistor

900. . . Internal circuit

B0, B1. . . Base

C1. . . Collector

D0. . . Bungee

E1. . . Emitter

G0. . . Gate

I0. . . Operating current

I1. . . Electrostatic current

S0. . . Source

Claims (10)

A high voltage semiconductor component comprising:
a high voltage metal-oxide-semiconductor transistor (HVMOS) having a drain (Drain) and a source (Source); and an NPN-type electrostatic protection bipolar transistor (electro-static discharge) The bipolar transistor (ESD BJT) has a first collector and a first emitter. The first collector is electrically connected to the drain, and the first emitter is electrically connected to the source. pole. The high voltage semiconductor device according to claim 1, wherein the high voltage MOS transistor and the NPN type electrostatic protection bipolar transistor are disposed in the same N-well. The high voltage semiconductor device of claim 1, wherein the drain of the high voltage MOS transistor and the first set of the NPN type electrostatic protection bipolar transistor are substantially the same N-type heavily doped region. The high voltage semiconductor component as described in claim 1 of the patent scope further includes:
A PNP type electrostatic protection bipolar transistor is connected in parallel with the NPN type electrostatic protection bipolar transistor. The high-voltage semiconductor device of claim 4, wherein the PNP-type electrostatic protection bipolar transistor has a second emitter and a second collector, and the second emitter is electrically connected to the drain and The first collector is electrically connected to the source and the first emitter. The high voltage semiconductor device according to claim 4, wherein the high voltage MOS transistor, the NPN type electrostatic protection bipolar transistor, and the PNP type electrostatic protection bipolar transistor are disposed in the same N-type well (well) )in. The high voltage semiconductor device of claim 4, wherein the PNP type electrostatic protection bipolar transistor has a second emitter, and the second emitter is disposed in the same N-type well as the first collector. The high voltage semiconductor device of claim 4, wherein the PNP type electrostatic protection bipolar transistor has a second collector, and the second collector and the first emitter are disposed in the same P-type well. A method of operating a high voltage semiconductor device, comprising:
Providing a high voltage semiconductor device comprising a high voltage metal-oxide-semiconductor transistor (HVMOS) and an NPN type electrostatic discharge bipolar transistor (ESD BJT) The high-voltage MOS transistor has a drain, a source, and a gate. The NPN-type electrostatic protection bipolar transistor has a first collector and a collector. a first emitter (Emitter), the first collector is electrically connected to the drain, and the first emitter is electrically connected to the source;
When the high voltage MOS transistor is driven, an operating current flows through the high voltage MOS transistor; and when the high voltage MOS transistor is turned off and an electrostatic event occurs, an electrostatic current flows through the NPN type static electricity. Protect the bipolar transistor. The method of operating a high voltage semiconductor device according to claim 9, wherein in the step of providing the high voltage semiconductor device, the high voltage semiconductor device further comprises a PNP type electrostatic protection bipolar transistor, the PNP type electrostatic protection double The polar crystal is connected in parallel with the NPN type electrostatic protection bipolar transistor;
In the step of generating an electrostatic event, the electrostatic current flows through the PNP type electrostatic protection bipolar transistor.