TW201301512A - High voltage semiconductor device - Google Patents

Abstract

The present invention provides a high voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high voltage well, a second doped region disposed in the high voltage well, a first gate structure disposed on the high voltage well between the second doped region and the first doped region, a doped channel region disposed in the high voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high voltage well. The high voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type.

Description

High voltage semiconductor component

The present invention relates to a high voltage semiconductor component, and more particularly to a high voltage semiconductor component incorporating a high voltage MOS transistor and an ESD protection component.

At present, the power supplied by the general power system is mostly an AC voltage source having a frequency of 50 Hz or 60 Hz and a voltage ranging from 100 V to 240 V, and the operating voltage and frequency are different depending on the electronic product. Therefore, in order to make the voltage supplied to the electronic product conform to the operating voltage range, a power conversion circuit is generally disposed in the electronic product or connected to the power system through an external power conversion circuit, so that the high voltage generated by the power system can be powered by the power supply. The conversion circuit is reduced to an operating voltage range that conforms to the internal circuitry of the electronic product.

Since the input end of the power conversion circuit needs to be directly electrically connected to the power system, the components directly connected to the power system in the power conversion circuit must withstand AC voltages ranging from 100V to 240V. High-voltage semiconductor components can be directly connected to the power system components in the power conversion circuit because they can withstand the high voltage provided by the general power system and have the characteristics of switches. They have been widely used in central power supply (CPU power supply). ), power management systems, DC/AC converters, LCD and plasma TV drivers, automotive electronics, computer peripherals, small-sized DC motor controllers, and lighting systems The power conversion circuit of the product. However, when the power conversion circuit is directly connected to the input end of the power system, electrostatic discharge is likely to occur, and static electricity enters the internal circuit through the power conversion circuit, causing the internal circuit to be damaged by electrostatic discharge, thereby causing the electronic product to be unusable.

In view of this, it is the industry's goal to avoid the destruction of the internal circuits of electronic products caused by the electrostatic discharge generated at the input end.

One of the main objects of the present invention is to provide a high voltage semiconductor component that prevents internal circuitry from being damaged by electrostatic discharge generated at the input.

To achieve the above object, the present invention provides a high voltage semiconductor device. The high voltage semiconductor device includes a substrate, a deep well region, a first doped region, a high voltage well region, a second doped region, a first gate structure, a doped channel region, and a third doped region. The substrate has a first conductivity type. The deep well region is disposed in the substrate and has a second conductivity type different from one of the first conductivity types. The first doped region is disposed in the deep well region and has a second conductivity type. The high voltage well region is disposed in the substrate and has a first conductivity type. The second doped region is disposed in the high voltage well region and has a second conductivity type. The first gate structure is disposed on the high voltage well region between the second doped region and the first doped region. The doped channel region is disposed in the high voltage well region and is in contact with the second doped region and the deep well region, and the doped channel region has a second conductivity type. The third doped region is disposed in the high voltage well region and has a second conductivity type.

To achieve the above object, the present invention further provides a high voltage semiconductor device. The high voltage semiconductor device includes a depletion type high voltage MOS transistor and an electrostatic discharge protection element. The depletion type high voltage MOS transistor has a first source and a first drain, wherein the first drain is electrically connected to a high voltage source, and the first source is electrically connected to an internal circuit. The ESD protection component is electrically connected between the first source and a ground to provide an electrostatic discharge path between the first source and the ground.

The high voltage semiconductor component of the present invention integrates the electrostatic discharge protection component with the depletion type high voltage MOS transistor to effectively guide the electrostatic discharge generated from the first drain to the ground to electrically connect to the first The internal circuitry of the source is protected. Moreover, the second doping region of the high voltage semiconductor device of the present invention can simultaneously serve as the second drain and the first source, which can effectively save the cost of manufacturing the electrostatic discharge protection component.

The present invention will be further understood by the following detailed description of the preferred embodiments of the invention. efficacy.

Please refer to FIG. 1. FIG. 1 is a circuit diagram of a high voltage semiconductor device according to a first preferred embodiment of the present invention. As shown in FIG. 1, the high voltage semiconductor device 100 includes a high-voltage metal-oxide-semiconductor (HV MOS) transistor 102 and an electrostatic discharge protection element 104. The HV MOS transistor 102 has a first gate 102a, a first source 102b, a first drain 102c, and a first base 102d. The first drain 102c is electrically connected to a high voltage source 106. For example, an ultra high voltage source of 500 volts to 800 volts, and the first source 102b is electrically coupled to an internal circuit 108 for providing a regulated voltage, for example, 7.5 volts, to the internal circuit 108. The first gate 102a is electrically connected to a control circuit 110, such as a low dropout regulator, to control the switching of the HV MOS transistor 102, but is not limited thereto. The ESD protection device 104 is electrically connected between the first source 102b and a ground terminal 112 to provide an electrostatic discharge path between the first source and the ground to discharge the static electricity of the first source 102b to the ground. End 112. It should be noted that the HV MOS transistor 102 of the present invention is a depletion mode HV MOS transistor, so when the first drain 102c is electrically connected to the high voltage source 106, at this time, the HV MOS transistor 102 A voltage difference is not provided between the first gate 102a and the first source 102b, and the HV MOS transistor 102 can still be in an on state, so that the high voltage provided by the high voltage source 106 can be stepped down through the HV MOS transistor 102. A stable voltage is supplied to the internal circuit 108 at the first source 102b. In addition, when the first drain 102c or the high voltage source 106 generates an electrostatic discharge, the static electricity flows through the HV MOS transistor 102 to the first source 102b, and the electrostatic discharge protection element 104 is triggered by the static electricity to be turned on. The static electricity of the first source 102b is released to the ground terminal 112.

In the present embodiment, the HV MOS transistor 102 is an N-type HV MOS (HV NMOS) transistor, and the ESD protection device 104 is an N-type metal oxide semiconductor (NMOS) transistor, but is not limited thereto. The HV MOS transistor of the present invention may also be a P-type HV MOS (HV PMOS) transistor, and the ESD protection device may also be a P-type metal oxide semiconductor (PMOS) transistor. The NMOS transistor 104 has a second gate 104a, a second source 104b, a second drain 104c and a second base 104d, and the second gate 104a and the second source 104b are electrically connected to the ground. At terminal 112, NMOS transistor 104 is a gate-grounded NMOS transistor (GGNMOS). The second base 104d and the first base 102d are also electrically connected to the ground end 112, and the second drain 104c is electrically connected to the first source 102b. Thereby, when the first drain 102c and the high voltage source 106 do not generate electrostatic discharge, the NMOS transistor 104 is in a closed state due to the grounding of the second gate 104a, so that the first source 102b can provide a stable voltage to the internal circuit 108. . When the first drain 102c or the high voltage source 106 generates an electrostatic discharge, the static electricity is guided to the first source 102b and the second drain 104c, and the static electricity triggers the NMOS transistor 104, and the NMOS transistor 104 is turned on. Static electricity can therefore be directed from the first source 102b to the second source 104b and the ground terminal 112.

The structure of the high voltage semiconductor element in which the depletion type HV NMOS transistor and the NMOS transistor are integrated in the present embodiment will be further described below. Please refer to Figure 2, and please refer to Figure 1 together. Fig. 2 is a schematic cross-sectional view showing a high voltage semiconductor device according to a first preferred embodiment of the present invention. As shown in FIGS. 1 and 2, the high voltage semiconductor device 100 is fabricated on a substrate 202, such as a germanium substrate, and the substrate 202 has a first conductivity type, such as a P-type. Moreover, the high voltage semiconductor device 100 is separated from the adjacent other electronic components by at least one isolation structure 204, such as a field oxide layer or at least one shallow trench isolation, and the isolation structure 204 is disposed between the high voltage semiconductor device 100 and other electronic components. On the substrate 202. The high voltage semiconductor device 100 includes a deep well region 206, a first doped region 208, a high voltage well region 210, a second doped region 212, a first gate structure 214, a doped channel region 218, and a fourth The doped region 220 and a withstand voltage structure 222. The high-voltage well region 210 and the fourth doping region 220 have a first conductivity type, and the deep well region 206, the first doping region 208, the second doping region 212, and the doping channel region 218 have one of different types from the first conductivity type. The second conductivity type, for example, N-type, but is not limited thereto, the first conductivity type and the second conductivity type of the present invention are also interchangeable. Moreover, the first doping region 208 and the second doping region 212 having the second conductivity type may be respectively composed of a heavily doped region and a gradient region, and the heavily doped region is located in the gradient region, but is not limited thereto.

In this embodiment, the N-type deep well region 206, the N-type first doped region 208, the P-type high-voltage well region 210, the N-type second doped region 212, the N-type doped channel region 218, and the first gate structure The 214 and the withstand voltage structure 222 constitute a depletion type HV NMOS transistor 102. The N-type deep well region 206 is disposed in the P-type substrate 202 and serves as the first drain 102c. The N-type first doped region 208 is disposed in the N-type deep well region 206 for electrically connecting the N-type deep well region 206 to a drain pad 224, that is, for electrically connecting to one of the high voltage sources 106. Input pad. The P-type high pressure well region 210 is disposed in the N-type deep well region 206 between the N-type first doped region 208 and the isolation structure 204, and the N-type deep well region 206 surrounds the P-type high pressure well region 210. Also, the P-type high voltage well region 210 serves as the first base 102d. The N-type second doping region 212 is disposed in the P-type high voltage well region 210 adjacent to the N-type first doping region 208, and serves as the first source 102b and is electrically connected to a source pad 226. The P-type fourth doping region 220 is disposed in the P-type high-voltage well region 210 between the N-type second doping region 212 and the isolation structure 204 for electrically connecting the P-type high-voltage well region 210 to the outside. The first gate structure 214 is formed by a first gate dielectric layer 215 and a first gate electrode 216 , and is disposed between the N-type first doping region 208 and the N-type second doping region 212 . The P-type high pressure well region 210. The first gate electrode 216 is disposed on the first gate dielectric layer 215 as the first gate 102a and electrically connected to a gate pad 228. The N-type doped channel region 218 is disposed in the P-type high voltage well region 210 adjacent to the first gate structure 214, and the N-type doped channel region 218 is associated with the N-type second doping region 212 and the N-type deep well region 206. Contact to serve as a channel region for the depleted HV NMOS transistor 102. It should be noted that the N-type doped channel region 218 is in contact with the N-type second doping region 212 as the first source 102b and the N-type deep well region 206 as the first drain 102c, so that the depletion HV NMOS is made. The transistor 102 can still be in an on state when the first gate 102a is not providing a voltage. The manner in which the N-type first doped region 208 of the present invention is electrically connected to the drain pad 224, the manner in which the N-type second doped region 212 is electrically connected to the source pad 226, and the first gate electrode 216 are electrically The manner of connecting to the gate pad 228 can be achieved by means of a metal interconnect structure. Since the metal interconnect structure is well known to those skilled in the art and will be described in detail, it will not be repeated here.

In addition, the withstand voltage structure 222 is disposed between the N-type first doping region 208 and the P-type high-voltage well region 210, and includes a plurality of polycrystalline field plates 230, a plurality of metal field plates 231, At least one of a first insulating layer 232 and a P-type fifth doped region 234, or a combination thereof. The first insulating layer 232 is disposed on a portion of the N-type deep well region 206 between the N-type first doped region 208 and the P-type high voltage well region 210, and can be used to isolate the high electric field from the N-type first doped region 208. To avoid damaging the first gate dielectric layer 215. Also, the first gate structure 214 may extend onto a portion of the first insulating layer 232. The P-type fifth doped region 234 is disposed in the N-type deep well region 206 and is in contact with the first insulating layer 232 and extends into contact with the first gate dielectric layer 214. In this embodiment, a portion of the N-type deep well region 206 is still located between the P-type fifth doped region 234 and the P-type high-voltage well region 210 and is in contact with the first gate structure 214. Each of the polysilicon field electrodes 230 is disposed on the first insulating layer 232 and sequentially arranged from one side adjacent to the first gate electrode 216 to adjacent to the N-type first doping region 208. Moreover, the polysilicon field electrode 230 and the first gate electrode 216 can be formed by etching the same polysilicon layer by the same etching process, but are not limited thereto. The metal field electrodes 231 are disposed on the polysilicon field electrodes 230 and are electrically isolated from each other by at least one insulating layer. In this embodiment, the polysilicon field electrode 230 closest to the N-type first doping region 208 is electrically connected to the N-type first doping region 208, and the other polysilicon field electrode 230 and the metal field electrode 231 are in a floating state. However, the present invention is not limited thereto, and the electrical connection state of the polysilicon field electrode 230 and the metal field electrode 231 may be adjusted according to the actual withstand voltage conditions required. Thereby, when the first drain 102c of the depletion HV NMOS transistor 102 is connected with a high voltage, the withstand voltage structure 222 can withstand the high electric field generated from the N-type first doping region 208, so that the junction structures are not A collapse occurs, so the first drain 102c can be used to directly electrically connect to the power system. Moreover, the first insulating layer 232 may be a field oxide layer, but is not limited thereto, and may also be at least one shallow trench isolation structure.

In addition, the high voltage semiconductor device 100 further includes a second gate structure 236 and an N-type third doping region 240, and an N-type second doping region 212, an N-type third doping region 240, and a P-type high-voltage well region. 210 and the second gate structure 236 may constitute the NMOS transistor 104 as an electrostatic discharge protection element. The N-type third doping region 240 is disposed in the P-type high voltage well region 210 between the N-type second doping region 212 and the P-type fourth doping region 220, and serves as a second source of the NMOS transistor 104. Pole 104b. The N-type second doping region 212 serves as the second drain 104c of the NMOS transistor 104. Therefore, the first source 104b and the second drain 104c share the N-type second doping region 212, so that the first source 104b Electrically connected to the second drain 104c. The second gate structure 236 can be formed by a second gate dielectric layer 237 and a second gate electrode 238, and is disposed between the N-type second doping region 212 and the N-type third doping region 240. The high voltage well region 210 is formed, whereby the second gate electrode 238 can serve as the second gate 104a of the NMOS transistor 104. Moreover, the P-type high-voltage well region 210 can be used not only as the first base 102d of the vacant HV NMOS transistor 102, but also as the second base 104d of the NMOS transistor 104, so that the first base 102d is electrically connected to the first Two bases 104d. In addition, the P-type fourth doping region 220, the N-type third doping region 240, and the second gate electrode 238 are electrically connected to the same conductive layer 242 by different contact plugs, thereby being electrically connected to each other, so the NMOS The transistor 104 becomes an NMOS transistor whose gate is grounded. Moreover, the conductive layer 242 can also be electrically connected to one of the P-type sixth doping regions 244 located in the P-type substrate 202 by a contact plug to be electrically connected to the P-type substrate 202 to be the first base 102d. The P-type high voltage well region 210 with the second base 104d may be at the same voltage level as the P-type substrate 202, but is not limited thereto.

It can be seen that when the drain pad 224 or the high voltage source 106 generates an electrostatic discharge, the static electricity is first guided through the N-type first doping region 208, the N-type deep well region 206, and the N-type doping channel region 218. To the N-type second doping region 212. Then, the gate ground NMOS transistor 104 is electrostatically triggered, so that static electricity can be directed to the ground terminal 112 through the P-type high voltage well region 210 and the N-type third doping region 240. Therefore, the internal circuit 108 electrically connected to the first source 102b can be protected from electrostatic discharge generated by the drain pad 224 or the high voltage source 106 to effectively protect the internal circuit 108 having various semiconductor elements. Moreover, the high voltage semiconductor device 200 of the present embodiment utilizes the N-type second doping region 212 as the second drain 104c of the NMOS transistor 104 and the first source 102b of the depletion HV MOS transistor 102, so that only By additionally adding the second gate dielectric layer 236, the second gate electrode 238, and the N-type third doping region 240, the NMOS transistor 104 and the depletion HV MOS transistor 102 can be integrated, which is more effective. Save on the cost of making ESD protection components.

The high voltage semiconductor device of the present invention is not limited to the above embodiment. The other embodiments and variations of the present invention are described in the following, and the same reference numerals will be used to refer to the same elements, and the repeated parts will not be described again.

The P-type high-pressure well region of the present invention is not limited to being disposed in the N-type deep well region. Please refer to FIG. 3, which is a cross-sectional view of a high voltage semiconductor device according to a second preferred embodiment of the present invention. As shown in FIG. 3, in comparison with the first embodiment, the P-type high voltage well region 302 of the high voltage semiconductor device 300 of the present embodiment is disposed in the P-type substrate 202 and is in contact with the P-type substrate 202, and N. The deep well region 304 is not in contact with the P-type high pressure well region 302, but is only in contact with the N-type doped channel region 218.

In addition, the electrostatic discharge protection component of the present invention is not limited to an MOS transistor, and may be other types of electrostatic discharge protection components, such as a bipolar junction transistor (BJT) or a silicon controlled rectifier (silicon- Controlled rectifier, SCR). Please refer to FIG. 4, which is a circuit diagram of a high voltage semiconductor device according to a third preferred embodiment of the present invention. As shown in FIG. 4, compared with the first embodiment, the electrostatic discharge protection component of the high voltage semiconductor device 400 of the present embodiment is an NPN type bipolar junction transistor 402, but is not limited thereto, when HV MOS When the transistor can also be a P-type HV MOS transistor, the electrostatic discharge protection component can also be a PNP type double carrier junction transistor. In this embodiment, the NPN-type bipolar junction transistor 402 has an emitter 402a, a third base 402b, and a collector 402c. The emitter 402a and the third base 402b are electrically connected to the ground. 112, and the collector 402c is electrically connected to the first source 102b.

The structure of the high voltage semiconductor element in which the depletion type HV NMOS transistor and the NMOS transistor are integrated in the third embodiment will be further described below. Please refer to Figure 5 and refer to Figure 4 together. Figure 5 is a cross-sectional view showing a high voltage semiconductor device in accordance with a third preferred embodiment of the present invention. As shown in FIG. 4 and FIG. 5, the high voltage semiconductor device 400 of the present embodiment is not provided with the second gate structure, and further includes a second insulating layer 404 disposed on the N type. The P-type high voltage well region 210 between the second doping region 212 and the N-type third doping region 240 electrically isolates the N-type second doping region 212 from the N-type third doping region 240. In the present embodiment, the N-type second doping region 212, the N-type third doping region 240, and the P-type high-voltage well region 210 constitute an NPN-type bipolar junction transistor. The N-type second doped region 212 serves as the collector 402c, the P-type high-voltage well region 210 serves as the third base 402b, and the N-type third doped region 240 serves as the emitter 402a. In addition, the N-type third doping region 240 is not necessarily disposed between the P-type fourth doping region 220 and the N-type second doping region 212. In other embodiments of the invention, the locations of the P-type fourth doped region 220 and the N-type third doped region 240 are also interchangeable.

In summary, the high voltage semiconductor component of the present invention integrates the ESD protection component with the depletion HV MOS transistor electrically connected to the power system to effectively direct the electrostatic discharge generated from the first drain to The ground terminal protects the internal circuit electrically connected to the first source. Moreover, the N-type second doping region of the high voltage semiconductor device of the present invention can simultaneously serve as the second drain and the first source, so that only the N-type third doping region and the second insulating layer or the N-type are additionally required. The three-doped region, the gate dielectric layer and the gate electrode can integrate the ESD protection component with the depleted HV MOS transistor, and the cost of manufacturing the ESD protection component can be effectively saved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100. . . High voltage semiconductor component

102. . . High voltage MOS transistor

102a. . . First gate

102b. . . First source

102c. . . First bungee

102d. . . First base

104. . . Metal oxide semiconductor transistor

104a. . . Second gate

104b. . . Second source

104c. . . Second bungee

104d. . . Second base

106. . . High voltage source

108. . . Internal circuit

110. . . Control circuit

112. . . Ground terminal

202. . . Base

204. . . Isolation structure

206. . . Deep well area

208. . . First doped region

210. . . High pressure well area

212. . . Second doped region

214. . . First gate structure

215. . . First gate dielectric layer

216. . . First gate electrode

218. . . Doped channel region

220. . . Fourth doped region

222. . . Pressure resistant structure

224. . . Bungee pad

226. . . Source pad

228. . . Gate pad

230. . . Polycrystalline field electrode

231. . . Metal field electrode

232. . . First insulating layer

234. . . Fifth doped region

236. . . Second gate structure

237. . . Second gate dielectric layer

238. . . Second gate electrode

240. . . Third doped region

242. . . Conductive layer

244. . . Sixth doping zone

300. . . High voltage semiconductor component

302. . . High pressure well area

304. . . Deep well area

400. . . High voltage semiconductor component

402. . . Double carrier junction transistor

402a. . . Emitter

402b. . . Third base

402c. . . Collector

404. . . Second insulating layer

Fig. 1 is a circuit diagram showing a high voltage semiconductor device according to a first preferred embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view showing a high voltage semiconductor device according to a first preferred embodiment of the present invention.

Figure 3 is a cross-sectional view showing a high voltage semiconductor device in accordance with a second preferred embodiment of the present invention.

Fig. 4 is a circuit diagram showing a high voltage semiconductor device according to a third preferred embodiment of the present invention.

Figure 5 is a cross-sectional view showing a high voltage semiconductor device in accordance with a third preferred embodiment of the present invention.

100. . . High voltage semiconductor component

202. . . Base

204. . . Isolation structure

206. . . Deep well area

208. . . First doped region

210. . . High pressure well area

212. . . Second doped region

214. . . First gate structure

215. . . First gate dielectric layer

216. . . First gate electrode

218. . . Doped channel region

220. . . Fourth doped region

222. . . Pressure resistant structure

224. . . Bungee pad

226. . . Source pad

228. . . Gate pad

230. . . Polycrystalline field electrode

231. . . Metal field electrode

232. . . First insulating layer

234. . . Fifth doped region

236. . . Second gate structure

237. . . Second gate dielectric layer

238. . . Second gate electrode

240. . . Third doped region

242. . . Conductive layer

244. . . Sixth doping zone

Claims (19)

A high voltage semiconductor device comprising: a substrate having a first conductivity type; a deep well region disposed in the substrate and having a second conductivity type different from the first conductivity type; a first doped region Provided in the deep well region and having the second conductivity type; a high voltage well region disposed in the substrate and having the first conductivity type; and a second doped region disposed in the high voltage well region And having the second conductivity type; a first gate structure disposed on the high voltage well region between the second doped region and the first doped region; a doped channel region disposed in the high voltage well And in the region, the second doped region is in contact with the deep well region, and the doped channel region has the second conductivity type; and a third doped region is disposed in the high voltage well region and has the The second conductivity type. The high voltage semiconductor device of claim 1, further comprising a fourth doping region disposed in the high voltage well region and having the first conductivity type, wherein the fourth doping region is electrically connected to the third doping region Miscellaneous area. The high voltage semiconductor device of claim 2, wherein the third doped region is disposed between the fourth doped region and the second doped region. The high voltage semiconductor device of claim 2, wherein the third doped region and the fourth doped region are electrically connected to the substrate. The high voltage semiconductor device of claim 1, further comprising a withstand voltage structure disposed between the first doped region and the high voltage well region. The high voltage semiconductor device of claim 5, wherein the deep well region, the first doped region, the high voltage well region, the second doped region, the gate structure, and the doped channel region constitute a high voltage of a depletion region Gold oxide semiconductor transistor. The high voltage semiconductor device of claim 5, wherein the voltage withstand structure comprises a first insulating layer disposed on the deep well region between the first doped region and the high voltage well region. The high voltage semiconductor device of claim 7, wherein the voltage withstand structure further comprises a plurality of field electrodes disposed on the first insulating layer. The high voltage semiconductor device of claim 7, wherein the voltage withstand structure further comprises a fifth doped region disposed in the deep well region and in contact with the first insulating layer and having the first conductivity type. The high voltage semiconductor device of claim 7, wherein the first gate structure extends onto the first insulating layer. The high voltage semiconductor device of claim 1, further comprising a second gate structure disposed on the high voltage well region between the second doped region and the third doped region, and the second gate The structure includes a second gate electrode electrically connected to the third doped region. The high voltage semiconductor device of claim 11, wherein the second doped region, the third doped region, the high voltage well region, and the second gate structure constitute a MOS transistor. The high voltage semiconductor device of claim 1, wherein the second doped region, the third doped region, and the high voltage well region constitute a dual carrier junction transistor. The high voltage semiconductor device of claim 1, further comprising a second insulating layer disposed between the second doped region and the third doped region. The high voltage semiconductor component of claim 1, wherein the high voltage well region is disposed in the deep well region, and the deep well region surrounds the high voltage well region. A high voltage semiconductor device comprising: a depletion type high voltage MOS transistor having a first source and a first drain, wherein the first drain is electrically connected to a high voltage source, and the first The source is electrically connected to an internal circuit; and an ESD protection component is electrically connected between the first source and a ground to provide an electrostatic discharge path between the first source and the ground . The high voltage semiconductor device of claim 16, wherein the electrostatic discharge protection component is a MOS transistor having a second gate, a second source, and a second drain, the second gate And the second source is electrically connected to the ground, and the first source is electrically connected to the second drain. The high voltage semiconductor device of claim 17, wherein the depletion type high voltage MOS transistor further has a first base, the MOS transistor further has a second base, and the first base The second base is electrically connected to the ground. The high voltage semiconductor device of claim 16, wherein the electrostatic discharge protection component is a double carrier junction transistor having an emitter, a third base, and a collector, the emitter and the third The base is electrically connected to the ground, and the collector is electrically connected to the first source.