JP2012174740A - Esd protection circuit of semiconductor integrated circuit and esd protection element thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the holding voltage Vh to a proper voltage equal to or higher than the power supply voltage without causing significant decrease of the protection capability by suppressing increase in the layout area when compared with a conventional structure.SOLUTION: The ESD protection element 21 includes an SCR element as a snapback characteristic element having the snapback characteristics, and a diode 13 connected with the SCR element as a voltage addition element for adding the snapback start voltage Vt1 by an amount of the element voltage and bringing the hold voltage Vh twice as high as the element voltage. The hold voltage Vh is adjusted between the power supply voltage Vcc and the withstand voltage of a protected element by adjusting the element voltage of the diode 13.

Description

  The present invention relates to an ESD protection circuit for a semiconductor integrated circuit having a snapback characteristic in which a current flows when a breakdown starts due to a surge voltage, and the voltage rapidly decreases, and performs ESD protection on a protected element, and its ESD protection It relates to an element.

  In a conventional semiconductor device having a semiconductor element, the ESD protection element of the semiconductor integrated circuit and its ESD protection circuit are used to protect the semiconductor element from electrostatic discharge (hereinafter referred to as ESD: Electro Static Discharge) due to external static electricity. It has been.

  In general, an ESD protection element is a gate grounded NMOS (ggNMOS) transistor in which the gate and source of an NMOS transistor are connected to a ground potential (GND), or an ESD protection element using a snapback phenomenon by a bipolar transistor operation such as an SCR. It is done. For example, in a ggNMOS structure ESD protection element, when a positive surge voltage is applied to a terminal connected to the drain with reference to the ground potential, the drain end of the NMOS transistor breaks down. When the product of the avalanche current generated by the breakdown and the substrate resistance exceeds the diffusion barrier voltage (about 0.6 V) of the PN junction, the parasitic NPN bipolar transistor operates. Due to the operation of the parasitic bipolar transistor, a low-impedance current path is formed between the drain and source, current flows, and drops to a holding voltage Vh determined by the product of the collector-emitter resistance and the collector current. This is called a snapback phenomenon. Thereafter, both the current and voltage between the collector and the emitter rise, a large current flows, and when the heat generation inside the silicon reaches 1420 degrees Celsius, which is the melting point of silicon, the device is destroyed (breakdown voltage Vt2, breakdown current It2).

  In an SCR (Silicon Controlled Rectifier) structure ESD protection element, when a positive surge voltage is applied to a terminal connected to an anode with a ground potential as a reference, a PN junction between a low-concentration N-type impurity diffusion layer and a P-type silicon substrate is formed. Break down. When the product of the avalanche current generated by the breakdown and the resistance of the low-concentration N-type impurity diffusion layer exceeds the diffusion barrier voltage (about 0.6 V) of the PN junction, the PNP bipolar transistor is turned on. Further, the collector current of the PNP bipolar transistor becomes the base current of the NPN bipolar transistor, and the NPN bipolar transistor is subsequently turned on.

Further, when the product of the avalanche current and the resistance of the P-type silicon substrate or the low-concentration P-type impurity diffusion layer forming the base of the NPN bipolar transistor exceeds the diffusion barrier voltage (about 0.6 V) of the PN junction. However, the collector current of the NPN bipolar transistor becomes the base current of the PNP bipolar transistor, and the PNP bipolar transistor is subsequently turned on. By such an operation of the bipolar transistor, a low impedance current path is formed between the anode and the cathode, current flows, and the voltage drops to the holding voltage Vh. Thereafter, both the current and voltage between the anode and the cathode increase, a large current flows, and the device breaks down when the heat generation inside the silicon reaches 1420 ° C., which is the melting point of silicon (breakdown voltage Vt2, breakdown current It2).
An ESD protection element using such a snapback phenomenon is very effective as a protection element for a low breakdown voltage circuit, but the following problems arise when it is used as a protection element for a high breakdown voltage circuit.

  There is a problem that an ESD protection element constituted by a high voltage ggNMOS transistor constituted by a high voltage MOS transistor is very easily broken. The gate electrode end portion is disposed on a thick oxide film such as a LOCOS (local oxidation of silicon) oxide film, and the thick oxide film end portion at the gate electrode end portion becomes a high electric field, thereby causing a defect in the thick oxide film end portion. A large amount of electrons are trapped in the layer, causing local leakage and destruction, and the device is destroyed immediately after the snapback phenomenon. Even if the element does not break down immediately after the snapback phenomenon, the drain-source impedance rapidly decreases due to the operation of the parasitic bipolar transistor, and the voltage applied to the protective element drops to the holding voltage Vh. At this time, the holding voltage Vh is lowered to the maximum operating voltage or less, an excessive current flows from the power supply of the internal circuit to the protection element, and the element is destroyed due to heat generation inside the protection element.

  Similarly, in the SCR structure ESD protection element, the holding voltage Vh is lowered to the maximum operating voltage or less, an excessive current flows from the power supply of the internal circuit to the protection element, and the element is destroyed due to heat generation inside the protection element.

  Furthermore, a diode may be used as an ESD protection element that does not use the snapback phenomenon. However, when a diode is used as a protection element, the on-resistance during operation is very large, so that the internal circuit is protected. However, if a sufficient current is supplied, a very large layout area is required.

  In order to solve such problems, the following Patent Documents 1 and 2 have been proposed.

  FIG. 18 is a longitudinal sectional view of a main part schematically showing a conventional high voltage ESD protection element structure disclosed in Patent Document 1. As shown in FIG.

  As shown in FIG. 18, in the bipolar transistor type ESD protection element 100, the collector N-type epitaxial layer 102 formed on the P-type substrate 101 and the low and high concentrations of the base formed in the N-type epitaxial layer 102. The P-type diffusion layers 103 and 104, the emitter N-type diffusion layer 105 formed in the high-concentration P-type diffusion layer 104, and the collector contact region 106 of the N-type epitaxial layer 102 are shallower and lower than the N-type epitaxial layer 102. A high concentration N type sink layer 107 formed deeper than the concentration P type diffusion layer 103 and a field oxide film 108 formed on the surface of the N type epitaxial layer 102 between the low concentration P type diffusion layer 103 and the collector contact region 106. The high-concentration N-type sink layer 107 is a field from the collector contact region 106. Monolayer 108 is extended to the area below.

  Thus, the conventional high breakdown voltage ESD protection element structure extends the high concentration N-type sink layer 107, which is a high concentration fourth diffusion layer, from the collector contact region 106 to the region under the field oxide film 108, which is an insulating film. That is, by increasing the width X of the region of the high-concentration N-type sink layer 107 under the field oxide film 108, a built-in resistor of the high-concentration high-concentration N-type sink layer 107 is formed, causing a voltage drop. The holding voltage Vh can be increased as compared with the case where there is no region of the high-concentration N-type sink layer 107 under the oxide film 108.

  FIG. 19 is a circuit diagram of a conventional ESD protection circuit disclosed in Patent Document 2. In FIG.

  As shown in FIG. 19, in the ESD protection circuit 200, the drain D1 is connected to the first potential Vo via the load 201, the gate G1 is connected to the drive circuit 202, and the source S1 is connected to the second potential GND. The first MOS transistor M1, the collector C1 is connected to the first potential Vo through the load 201, the bipolar transistor Q1 with the base B1 open, the drain D2 is connected to the emitter E1 of the bipolar transistor Q1, and the gate G2 is the source And an electrostatic protection circuit 203 having a second MOS transistor M2 connected to S2 and having a source S2 connected to the second potential GND.

  The breakdown voltage of the electrostatic protection circuit 203 is the sum of the breakdown voltages of the bipolar transistor Q1 and the second MOS transistor M2, and a breakdown voltage smaller than the breakdown voltage of the first MOS transistor M1 and larger than the maximum operating voltage can be obtained. it can.

  As described above, in the ESD protection circuit 200, the bipolar transistor Q1 and the second MOS transistor M2 are connected in series to control the breakdown voltage. This breakdown voltage is the sum of the breakdown voltage of the bipolar transistor Q1 and the second MOS transistor M2.

  Here, an ESD protection element having a general SCR structure in which a PNP bipolar and an NPN bipolar are combined is also shown.

JP 2007-242923 A JP 2007-227697 A

  Due to the above snapback characteristics, when breakdown starts with a surge voltage, a large current flows from the holding voltage to the protective element after the voltage suddenly drops at the snapback operation starting voltage. When the voltage is lower than the power supply voltage, a large current flows from the power supply side to the protection element side, leading to element destruction.

  In Patent Document 1, as shown in the surge current / surge voltage characteristics of FIG. 20, by increasing the width X of the region of the high-concentration N-type sink layer 107 under the field oxide film 108, the holding voltage Vh3 is changed from the holding voltage Vh1. High voltage can be realized. However, in Patent Document 1, the high-concentration N-type sink layer 107 that is a high-concentration fourth diffusion layer is expanded from the collector contact region 106 to a region under the field oxide film 108 that is an insulating film (enlargement of X size). Since a series resistance is added to the collector and the holding voltage Vh1 is increased to the holding voltage Vh2 and holding voltage Vh3 so as to be higher than the power supply voltage, the characteristic straight line in FIG. When the width X of the region of the concentration N-type sink layer 107 is increased, the characteristic straight line in FIG. 20 is inclined to reduce the protection capability, and even if a surge current sufficient to protect the internal circuit is applied, a high concentration N-type sink is provided. The layout area of the ESD protection element is increased depending on the width X of the region of the layer 107.

  In Patent Document 2, two devices are connected in series for controlling the breakdown voltage. As shown in the surge current / surge voltage characteristics of FIG. 21, for example, the breakdown start voltage of the device is 10 V, and the snap When the back operation start voltage is 11 V, the holding voltage is 9 V, and the slope of the characteristic line is α, when two elements are connected in series, the value is doubled, the breakdown start voltage is 20 V, and the snap The back operation start voltage is 22 V, the holding voltage is 18 V, and the slope of the characteristic line is smaller than the slope α. As a result, a high holding voltage Vh can be ensured, but the size of the ESD protection element region is doubled, leading to an increase in the ESD protection element region, leading to an increase in cost, and the characteristic straight line in FIG. (Ability to flow current) decreases.

  The present invention solves the above-described conventional problems, and suppresses an increase in layout area as compared with the conventional structure, and the holding voltage Vh is set to an appropriate voltage that is equal to or higher than the power supply voltage without causing a significant decrease in protection capability. An object of the present invention is to provide an ESD protection circuit for a semiconductor integrated circuit that can be controlled and an ESD protection element thereof.

  An ESD protection circuit of a semiconductor integrated circuit according to the present invention includes a snapback characteristic element having a snapback characteristic in which a large current flows after a breakdown is started due to a surge voltage and the voltage rapidly decreases from a snapback start voltage to a holding voltage; A voltage adding element connected to the snapback characteristic element for adding the snapback start voltage by an amount corresponding to the element voltage and making the holding voltage higher than the power supply voltage, and adjusting the element voltage of the voltage adding element Then, the holding voltage is adjusted to be equal to or higher than the power supply voltage and lower than the withstand voltage of the protected element, whereby the above object is achieved.

  Preferably, the voltage adding element in the ESD protection circuit of the semiconductor integrated circuit of the present invention makes the holding voltage twice as high as the element voltage.

  Further preferably, the snapback characteristic element in the ESD protection circuit of the semiconductor integrated circuit of the present invention is any one of a thyristor element, a bipolar transistor and a MOS transistor.

  Further preferably, the voltage adding element in the ESD protection circuit of the semiconductor integrated circuit of the present invention is one or a plurality of diode elements or one or a plurality of transistors having a control terminal connected to the output terminal.

  Further preferably, in the ESD protection circuit of the semiconductor integrated circuit according to the present invention, the high potential terminal is connected to the emitter of the PNP bipolar transistor, and the base of the PNP bipolar transistor and the NPN bipolar transistor are connected via the first resistor. The low potential terminal is connected to the collector of the NPN bipolar transistor via the diode element in the forward direction, and connected to the collector of the PNP bipolar transistor and the base of the NPN bipolar transistor via the second resistor. It is connected.

  Further preferably, in the ESD protection circuit of the semiconductor integrated circuit according to the present invention, the high potential terminal is connected to the emitter of the PNP bipolar transistor through the diode element in the reverse direction, and the PNP bipolar is connected through the first resistor. The base of the transistor is connected to the collector of the NPN bipolar transistor, and the low potential terminal is connected to the emitter of the NPN bipolar transistor and to the collector of the PNP bipolar transistor and the base of the NPN bipolar transistor through a second resistor. Has been.

  Further preferably, in the ESD protection circuit of the semiconductor integrated circuit of the present invention, the high potential terminal is connected to the emitter of the NPN bipolar transistor, and the base of the NPN bipolar transistor and the PNP bipolar transistor are connected via the first resistor. The low potential terminal is connected to the collector of the PNP bipolar transistor via a diode element in the forward direction, and connected to the collector of the NPN bipolar transistor and the base of the PNP bipolar transistor via a second resistor. It is connected.

  Further preferably, in the ESD protection circuit of the semiconductor integrated circuit of the present invention, the high potential terminal is connected to the emitter of the NPN bipolar transistor through the diode element in the reverse direction, and the NPN bipolar is connected through the first resistor. The base of the transistor is connected to the collector of the PNP bipolar transistor, and the low potential terminal is connected to the emitter of the PNP bipolar transistor and connected to the collector of the NPN bipolar transistor and the base of the PNP bipolar transistor through a second resistor. Has been.

  Further preferably, in the ESD protection circuit of the semiconductor integrated circuit according to the present invention, the collector of the NPN bipolar transistor is connected to the high potential terminal, and the base of the NPN bipolar transistor is connected to the low potential terminal via the first resistor. The emitter of the NPN bipolar transistor is connected to the cathode of the diode element, and the anode of the diode element is connected to the low potential terminal.

  Further preferably, in the ESD protection circuit of the semiconductor integrated circuit of the present invention, the collector of the PNP bipolar transistor is connected to the high potential terminal, and the base of the PNP bipolar transistor is connected to the low potential terminal through the first resistor. The emitter of the PNP bipolar transistor is connected to the cathode of the diode element, and the anode of the diode element is connected to the low potential terminal.

  Further preferably, in the ESD protection circuit of the semiconductor integrated circuit of the present invention, the drain of the MOS transistor is connected to the high potential terminal, the body of the MOS transistor is connected to the low potential terminal through the first resistor, The gate of the MOS transistor is connected to the low potential terminal, the source of the MOS transistor is connected to the cathode of the diode element, and the anode of the diode is connected to the low potential terminal.

  Still preferably, in an ESD protection circuit of a semiconductor integrated circuit according to the present invention, the element voltage is a reverse junction breakdown voltage of the diode element.

  The ESD protection element of the semiconductor integrated circuit of the present invention is composed of the ESD protection circuit of the semiconductor integrated circuit of the present invention, and thereby the above object is achieved.

  Preferably, the ESD protection element of the semiconductor integrated circuit comprises the ESD protection circuit of the semiconductor integrated circuit of the present invention, wherein a diffusion layer forming an emitter of the NPN bipolar transistor and a cathode of the diode element are formed. The diffusion layer is common.

  Furthermore, it is preferable that the ESD protection element of the semiconductor integrated circuit comprises the ESD protection circuit of the semiconductor integrated circuit of the present invention, wherein a diffusion layer forming an emitter of the PNP bipolar transistor and a cathode of the diode element are formed. The diffusion layer is common.

  Still preferably, in an ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit of the present invention, a diffusion layer forming an emitter of the PNP bipolar transistor and an anode of the diode element are formed. The diffusion layer is common.

  Still preferably, in an ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit of the present invention, a diffusion layer forming an emitter of the NPN bipolar transistor and an anode of the diode element are formed. The diffusion layer is common.

  Furthermore, it is preferable that the ESD protection element of the semiconductor integrated circuit includes the ESD protection circuit of the semiconductor integrated circuit according to the present invention, wherein the diffusion layer forms the source of the MOS transistor and the diffusion forms the cathode of the diode element. The layer is common.

  Further preferably, an ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit of the present invention, comprising: a base of the PNP bipolar transistor; an emitter of the NPN bipolar transistor; and a cathode of the diode element. Are formed at the same time.

  Further preferably, an ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit of the present invention, comprising: a base of the NPN bipolar transistor; an emitter of the PNP bipolar transistor; and a cathode of the diode element. Are formed at the same time.

  Further preferably, the ESD protection element of the semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit of the present invention, comprising: a collector of the NPN bipolar transistor; an emitter of the NPN bipolar transistor; and a cathode of the diode element. Are formed at the same time.

  Further preferably, the ESD protection element of the semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit of the present invention, comprising: a collector of the PNP bipolar transistor; an emitter of the PNP bipolar transistor; and a cathode of the diode element. Are formed at the same time.

  Furthermore, it is preferable that the ESD protection element of the semiconductor integrated circuit comprises the ESD protection circuit of the semiconductor integrated circuit according to the present invention, wherein the drain of the MOS transistor, the source of the MOS transistor, and the cathode of the diode element are simultaneously provided. Is formed.

  With the above configuration, the operation of the present invention will be described below.

  In the present invention, a snapback characteristic element having a snapback characteristic in which a large current flows after a breakdown is started due to a surge voltage and a voltage rapidly decreases from the snapback start voltage to the holding voltage, and is connected to the snapback characteristic element. A voltage adding element for adding the snapback start voltage by the element voltage and making the holding voltage twice as high as the element voltage, and adjusting the element voltage of the voltage adding element so that the holding voltage is equal to or higher than the power supply voltage. Adjust to the withstand voltage of the protected element or less.

  As a result, the voltage adding element adds the snapback start voltage by the element voltage and makes the holding voltage twice as high as the element voltage. Therefore, compared to the conventional structure, the increase in layout area is suppressed and the protection capability is greatly increased. The holding voltage Vh can be controlled to an appropriate voltage equal to or higher than the power supply voltage without causing a decrease.

  As described above, according to the present invention, the voltage adding element adds the snapback start voltage by the element voltage and makes the holding voltage twice as high as the element voltage. Thus, the holding voltage Vh can be controlled to an appropriate voltage that is equal to or higher than the power supply voltage without causing a significant decrease in the protection capability.

It is a circuit diagram which shows the structural example of the ESD protection circuit of the semiconductor integrated circuit in Embodiment 1 of this invention. FIG. 2 is a longitudinal sectional view of an ESD protection element of a semiconductor integrated circuit corresponding to the ESD protection circuit of the semiconductor integrated circuit of FIG. 1. It is a figure which shows the surge current and surge voltage characteristic in the ESD protection circuit of the semiconductor integrated circuit of FIG. It is a circuit diagram which shows a thyristor structure roughly. FIG. 5 is a longitudinal sectional view of a thyristor element corresponding to the thyristor structure of FIG. 4. FIG. 2 is a circuit diagram illustrating an example in which each resistor is omitted from the ESD protection circuit of the semiconductor integrated circuit of FIG. 1. It is a longitudinal cross-sectional view which shows an example of the ESD protection element of the semiconductor integrated circuit corresponding to the circuit of FIG. FIG. 7 is a circuit diagram of a circuit in which only the NPN bipolar transistor and the diode of FIG. 6 are extracted. It is a figure which shows the surge current and surge voltage characteristic in the ESD protection circuit of the conventional semiconductor integrated circuit, and the surge current and surge voltage characteristic in the ESD protection circuit of the semiconductor integrated circuit of FIG. FIG. 3 is a longitudinal sectional view of an ESD protection element in which an interlayer insulating film, an anode terminal, and a cathode terminal are formed on the ESD protection element configuration of FIG. 2. It is a longitudinal cross-sectional view of the ESD protection element of a semiconductor integrated circuit for demonstrating simplification of manufacture of the ESD protection circuit of the semiconductor integrated circuit in Embodiment 2 of this invention. It is a longitudinal cross-sectional view of the ESD protection element which comprises the ESD protection circuit of the semiconductor integrated circuit in Embodiment 3 of this invention. It is a longitudinal cross-sectional view of the ESD protection element which comprises the ESD protection circuit of the semiconductor integrated circuit in Embodiment 4 of this invention. It is a longitudinal cross-sectional view of the ESD protection element of a semiconductor integrated circuit for demonstrating simplification of manufacture of the ESD protection circuit of the semiconductor integrated circuit in Embodiment 5 of this invention. It is a longitudinal cross-sectional view of the ESD protection element which comprises the ESD protection circuit of the semiconductor integrated circuit in Embodiment 6 of this invention. It is a longitudinal cross-sectional view of the ESD protection element which comprises the ESD protection circuit of the semiconductor integrated circuit in Embodiment 6 of this invention. It is a circuit diagram of the transistor used instead of the diode of the ESD protection circuit of the semiconductor integrated circuit of this invention. It is a principal part longitudinal cross-sectional view which shows typically the conventional high voltage | pressure-resistant ESD protection element structure currently disclosed by patent document 1. FIG. FIG. 10 is a circuit diagram of a conventional ESD protection circuit disclosed in Patent Document 2. It is a figure which shows the surge current and surge voltage characteristic in the conventional high voltage | pressure-resistant ESD protection element structure of FIG. It is a figure which shows the surge current and surge voltage characteristic in the conventional ESD protection circuit of FIG.

  Embodiments 1 to 7 of the ESD protection circuit of the semiconductor integrated circuit and the ESD protection element of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a circuit diagram showing a configuration example of an ESD protection circuit of a semiconductor integrated circuit according to Embodiment 1 of the present invention.

  In FIG. 1, the ESD protection circuit 11 of the semiconductor integrated circuit according to the first embodiment includes a resistor R1, an NPN bipolar transistor 12 and a reverse-connected diode 13 in series between an anode terminal A and a cathode terminal C, and a PNP bipolar circuit. A series circuit of the transistor 14 and the resistor R2 is connected in parallel, and the base of the NPN bipolar transistor 12 is formed at the connection point between the resistor R2 and the PNP bipolar transistor 14, and the base of the PNP bipolar transistor 14 is the resistor R1 and the NPN. It is configured at a connection point with the bipolar transistor 12. The ESD protection circuit 11 of the semiconductor integrated circuit is connected in parallel to the protected element, and protects the protected element by ESD.

  That is, in the ESD protection circuit 11 of the semiconductor integrated circuit according to the first embodiment, the anode terminal A as the high potential terminal is connected to the emitter of the PNP bipolar transistor 14 and the PNP is connected via the resistor R1 as the first resistor. The base of the bipolar transistor 14 and the collector of the NPN bipolar transistor 12 are connected, and the cathode terminal C as a low potential terminal is connected to the emitter of the NPN bipolar transistor 12 through the diode 13 (diode element) in the forward direction. It is connected to the collector of the PNP bipolar transistor 14 and the base of the NPN bipolar transistor 12 through a resistor R2 as a two-resistor.

  In short, the ESD protection circuit 11 of the semiconductor integrated circuit according to the first embodiment has a snapback characteristic in which a large current flows after a breakdown starts due to a surge voltage and the voltage rapidly decreases from the snapback start voltage to the holding voltage. The buck characteristic element and the snap back characteristic element are connected, and the snapback start voltage Vt1 is added by the element voltage (diode reverse junction breakdown voltage), and the holding voltage Vh is 2 of the element voltage (diode reverse junction breakdown voltage). A voltage adding element that is increased by a factor of two, and adjusting the element voltage of the voltage adding element to adjust the holding voltage Vh above the power supply voltage and below the withstand voltage of the protected element.

  In the first embodiment, the snapback characteristic element is a thyristor element (SCR), and the voltage adding element corresponds to the diode 13. The thyristor element includes a PNP bipolar transistor 14, an NPN bipolar transistor 12, and resistors R1 and R2.

  FIG. 2 is a longitudinal sectional view of the ESD protection circuit of the semiconductor integrated circuit corresponding to the ESD protection circuit of the semiconductor integrated circuit of FIG.

  In FIG. 2, an ESD protection element 21 constituting the ESD protection circuit 11 of the semiconductor integrated circuit according to the first embodiment is a second conductivity type formed on a first conductivity type (here, P type) semiconductor substrate 1. A low-concentration diffusion layer 4, a first-conductivity-type high-concentration diffusion layer 3 and a second-conductivity-type (N-type) high-concentration diffusion layer 5 formed on the surface side of the low-concentration diffusion layer 4; The first conductivity type semiconductor is adjacent to the second conductivity type low concentration diffusion layer 4 at a position opposite to the second conductivity type high concentration diffusion layer 5 with respect to the one conductivity type high concentration diffusion layer 3. First conductivity type low concentration diffusion layer 2 formed on substrate 1, second conductivity type diffusion layer 6 formed on the surface side of first conductivity type low concentration diffusion layer 2, and second conductivity type A high-concentration diffusion layer 3 of the first conductivity type formed at a position opposite to the low-concentration diffusion layer 4 with respect to the diffusion layer 6 of the second conductivity type, And a high-concentration diffusion layer 3 of the first conductivity type formed on the surface side of the goldenrod 6. The ESD protection element 21 includes a PNP bipolar 14 having the first conductivity type high concentration diffusion layer 3, the second conductivity type low concentration diffusion layer 4, and the first conductivity type low concentration diffusion layer 2, and a second conductivity type. An NPN bipolar 12 having a conductivity type low concentration diffusion layer 4, a first conductivity type low concentration diffusion layer 2 and a second conductivity type diffusion layer 6, and a second conductivity type diffusion layer 6 and a first conductivity type high concentration. And a diode 13 made of the concentration diffusion layer 3.

  The emitter of the PNP bipolar transistor 14 is connected to the high potential terminal (anode terminal A), the base of the PNP bipolar transistor 14 is connected to the collector of the NPN bipolar transistor 12, the base of the PNP bipolar transistor 14 and the collector of the NPN bipolar transistor 12 Is connected to the high potential terminal (anode terminal A) via the first resistor R1 made of the resistance component of the low-concentration diffusion layer 4 of the second conductivity type. The collector of the PNP bipolar transistor 14 is connected to the base of the NPN bipolar transistor 12, and the collector of the PNP bipolar transistor 14 and the base of the NPN bipolar transistor 12 are the first conductive type semiconductor substrate 1 and the first conductive type low concentration. It is connected to a low potential terminal (cathode terminal C) via a second resistor R2 made of a resistance component of the diffusion layer 2. Further, the emitter of the NPN bipolar transistor 12 is connected to the cathode of the diode 13, and the anode of the diode 13 is connected to the low potential terminal (cathode terminal C). The NPN bipolar transistor 12 and the PNP bipolar transistor 14 have a thyristor structure, and a diode 13 is reversely connected to the thyristor structure to constitute an ESD protection element 21 utilizing a bipolar operation.

  FIG. 3 is a diagram showing surge current / surge voltage characteristics in the ESD protection circuit of the semiconductor integrated circuit of FIG. FIG. 4 is a circuit diagram schematically showing a thyristor structure. FIG. 5 is a longitudinal sectional view of a thyristor element corresponding to the thyristor structure of FIG. FIG. 6 is a circuit diagram illustrating an example in which the resistors R1 and R2 are omitted from the ESD protection circuit 11 of the semiconductor integrated circuit of FIG. FIG. 7 is a longitudinal sectional view showing an example of the ESD protection element 21 of the semiconductor integrated circuit corresponding to the circuit of FIG.

  As shown in FIG. 3, due to the snapback characteristic, when breakdown starts with a surge voltage, the current increases from the snapback operation start voltage (snapback operation voltage Vt1), and then from the holding voltage Vh after the voltage suddenly decreases. A large current flows through the ESD protection element 21. The dotted line is the ESD protection element having the conventional structure, and the solid line is the ESD protection element 21 having the structure of the present invention. As described above, the diode 13 as a voltage adding element is added as shown in FIGS. 6 and 7 of the structure of the present invention to the ESD protection element of the thyristor structure of FIGS. The start voltage Vt1 is added by the element voltage (diode reverse junction withstand voltage) and the holding voltage Vh is twice the element voltage (diode reverse junction withstand voltage) compared to the ESD protection elements of FIGS. 4 and 5 having the conventional structure. Can be high.

Thus, by adding the diode 13 as shown in FIGS. 6 and 7 between the emitter and the low potential terminal (cathode terminal C) of the NPN bipolar transistor 12 having the thyristor structure shown in FIGS. As shown in FIG. 1, the snapback voltage can be increased by the reverse junction breakdown voltage of the diode 13.
Vsn = Vsn′−VB (Formula 1)
Vsn: Snapback voltage Vsn ′ of the first embodiment: Snapback voltage of conventional structure (snapback voltage: snapback operating voltage Vt1−holding voltage Vh)
VB: Reverse junction withstand voltage of diode 13 Further, as shown in Equation 2, the snapback operating voltage also increases by the diode reverse junction withstand voltage in the same manner as the snapback voltage.
Vt1 = Vt1 ′ + VB (Formula 2)
Vt1: Snapback operating voltage Vt1 ′ of the first embodiment: Snapback operating voltage VB of conventional structure VB: Due to the reverse junction breakdown voltage of the diode 13, the holding voltage Vh of the first embodiment is given by the above formulas 1 and 2. As shown in the following Expression 3, the voltage can be increased by twice the reverse junction breakdown voltage of the diode 13 with respect to the holding voltage Vh ′ of the conventional structure.
Vh = Vt1-Vsn
= (Vt1 '+ VB)-(Vsn'-VB)
= Vt1′−Vsn ′ + 2 × VB (Formula 3)
Here, as described above repeatedly, by adding the diode 13 as a voltage adding element, the snapback start voltage Vt1 is added by the element voltage (diode reverse junction breakdown voltage) and the holding voltage Vh is added to the element voltage (diode reverse voltage). The point that it can be made higher than the ESD protection element of the conventional structure by twice as much as the direction junction breakdown voltage) will be described more specifically.

  FIG. 8 is a circuit diagram of a circuit in which only the NPN bipolar transistor 12 and the diode 13 in FIG. 6 are taken out. FIG. 9 is a diagram showing surge current / surge voltage characteristics in an ESD protection circuit of a conventional semiconductor integrated circuit and surge current / surge voltage characteristics in an ESD protection circuit of the semiconductor integrated circuit of FIG.

  As shown in FIG. 8, when 0.6V is applied between the base and emitter of the NPN bipolar transistor 12, the transistor is turned on, but when a diode 13 having a forward voltage of 10V is applied to the emitter side of the NPN bipolar transistor 12, It is turned on when a voltage of 10.6 V is applied to the base of the NPN bipolar transistor 12. That is, the NPN bipolar transistor 12 is not turned on unless the voltage is increased by 10 V including the diode 13. Therefore, as shown in FIG. 9, the snapback operation start voltage (snapback operation voltage Vt1) is increased by 10 V from the breakdown start voltage as compared with the conventional structure. Further, the holding voltage Vh is higher by 10V than that of the conventional structure, and is increased by 2 × 10V. Since the ESD protection element 21 must operate until the protected element is destroyed, it is necessary to control the holding voltage Vh to a voltage not lower than the power supply voltage and not higher than the withstand voltage of the protected element.

  In this way, the holding voltage Vh can be controlled by controlling the reverse junction withstand voltage of the diode 13. With respect to the control of the reverse junction withstand voltage of the diode 13, the distance A shown in FIG. It can be freely controlled by the diffusion concentration of the conductive type diffusion layer 6.

  Further, the problem that the layout area of the ESD protection element increases as the holding voltage Vh of Patent Document 1 increases does not occur in the present invention.

  As described above, according to the first embodiment, the ESD protection element 21 is connected to the SCR element as the snapback characteristic element having the snapback characteristic, and the snapback start voltage Vt1 is equal to the element voltage ( Diode reverse junction breakdown voltage) and a diode 13 as a voltage adding element for increasing the holding voltage Vh twice as high as the element voltage, and adjusting the element voltage of the diode 13 so that the holding voltage Vh is the power supply voltage. Adjust to Vcc or higher and withstand voltage of the protected element.

  As a result, the increase in layout area is suppressed, and the slope of the characteristic line is not significantly reduced by the addition of the diode 13 as compared with the conventional structure, and is maintained without causing a significant decrease in the protection capability as compared with the conventional structure. The voltage Vh can be controlled to an appropriate voltage equal to or higher than the power supply voltage.

  As shown in FIG. 10, an interlayer insulating film 8 is formed on the configuration of FIG. 2, and an anode terminal 9 and a cathode terminal 10 are formed on the interlayer insulating film 8. Reference numeral 7 denotes an element isolation insulating film.

(Embodiment 2)
In the first embodiment, the ion implantation process for the second conductivity type (N-type) diffusion layer 6 is performed separately. In the second embodiment, the ion implantation process for the second conductivity type (N-type) diffusion layer 6 is performed. The case where the ion implantation process of the second conductivity type (N-type) diffusion layer 6 is not required separately by performing the ion implantation process of the second conductivity type (N-type) low-concentration diffusion layer 4 will be described. .

  FIG. 11 is a vertical cross-sectional view of an ESD protection element of a semiconductor integrated circuit for explaining the simplification of the production of the ESD protection circuit of the semiconductor integrated circuit in Embodiment 2 of the present invention. In FIG. 11, members having the same functions and effects as those in FIG. 2 are denoted by the same reference numerals and description thereof is omitted.

  11, the ESD protection element 21A of the semiconductor integrated circuit according to the second embodiment includes the first conductivity type low-concentration diffusion layer 2 immediately below the second conductivity type (here, N type) diffusion layer 6 of FIG. The second conductivity type low-concentration diffusion layer 4 is formed in the region where the second conductivity type diffusion layer 6 is formed without forming the second conductivity type (N type) diffusion layer 6. By simultaneously performing the ion implantation step of the second conductivity type (N-type) low-concentration diffusion layer 4, it is possible to simplify the manufacture of the ESD protection element 21A corresponding to the ESD protection circuit 11 of the semiconductor integrated circuit.

  Even with such a structure, the holding voltage Vh shown in the first embodiment can be controlled, and the same effect as shown in the first embodiment can be obtained. The control of the reverse junction breakdown voltage (added voltage) of the diode 13 can be freely controlled by the distance A shown in FIG. In addition, since the second conductivity type diffusion layer 6 shown in the first embodiment is not necessary, it can be realized only by a process necessary for manufacturing a conventional semiconductor substrate, and the manufacturing of the ESD protection element 21A can be simplified. Can be planned.

  In the first and second embodiments, the P-type semiconductor substrate 1 is used in the ESD protection circuit 11 of the semiconductor integrated circuit, the high potential terminal (anode terminal A) is connected to the emitter of the PNP bipolar transistor 14, and the first One resistor R1 is connected to the base of the PNP bipolar transistor 14 and the collector of the NPN bipolar transistor 12, and the low potential terminal (cathode terminal C) is connected to the emitter of the NPN bipolar transistor 12 through the diode 13 in the forward direction. In addition, the case where the PNP bipolar transistor 14 is connected to the collector of the PNP bipolar transistor 14 and the base of the NPN bipolar transistor 12 via the second resistor R2 has been described. However, the present invention is not limited thereto, and the ESD protection circuit 11 of the semiconductor integrated circuit is modified. When an N-type semiconductor substrate is used as an example, The potential terminal (anode terminal A) is connected to the emitter of the NPN bipolar transistor, and is connected to the base of the NPN bipolar transistor and the collector of the PNP bipolar transistor via the first resistor R1, and the low potential terminal (cathode terminal C). May be connected to the emitter of the PNP bipolar transistor via the diode 13 in the forward direction, and may be connected to the collector of the NPN bipolar transistor and the base of the PNP bipolar transistor via the second resistor R2.

(Embodiment 3)
In the first embodiment, the case where the cathode terminal C as the low potential terminal is connected to the emitter of the NPN bipolar transistor 12 through the diode 13 (diode element) in the forward direction has been described. In the third embodiment, a case where the anode terminal A as a high potential terminal is connected to the emitter of the PNP bipolar transistor 14 through the diode 13 (diode element) in the reverse direction will be described.

  FIG. 12 is a longitudinal sectional view of an ESD protection element constituting the ESD protection circuit of the semiconductor integrated circuit according to Embodiment 3 of the present invention. In FIG. 12, members having the same effects as the members in FIG.

  In FIG. 12, the ESD protection element 21B of the semiconductor integrated circuit according to the third embodiment is a low-conductivity type (here, N-type) low-resistance formed on the first-conductivity-type (here, P-type) semiconductor substrate 1. The concentration diffusion layer 4, the second conductivity type high concentration diffusion layer 5 and the first conductivity type diffusion layer 6B formed on the surface side of the low concentration diffusion layer 4, and the surface of the first conductivity type diffusion layer 6B The second conductivity type high concentration diffusion layer 5 formed on the surface of the second conductivity type low concentration diffusion layer 4 with respect to the formed second conductivity type high concentration diffusion layer 5 and the first conductivity type diffusion layer 6B. A first conductivity type low concentration diffusion layer 2 formed on the first conductivity type semiconductor substrate 1 adjacent to the second conductivity type low concentration diffusion layer 4 at a position opposite to the diffusion layer 5; A second conductivity type high concentration diffusion layer 5 formed on the surface of the one conductivity type low concentration diffusion layer 2 and a shape formed on the surface of the first conductivity type low concentration diffusion layer 2. The first conductivity type high concentration diffusion layer 3 formed at a position opposite to the second conductivity type low concentration diffusion layer 4 with respect to the second conductivity type high concentration diffusion layer 5. ing.

  The ESD protection element 21B includes a first conductivity type diffusion layer 6B, a PNP bipolar layer 14 composed of the second conductivity type low concentration diffusion layer 4 and the first conductivity type low concentration diffusion layer 2, and a second conductivity type low concentration layer. An NPN bipolar 12 comprising a concentration diffusion layer 4, a first conductivity type low concentration diffusion layer 2 and a second conductivity type high concentration diffusion layer 5, a first conductivity type diffusion layer 6B and a second conductivity type high concentration diffusion. And a diode 13 composed of the layer 5.

In the ESD protection circuit 11B of the semiconductor integrated circuit, the emitter of the NPN bipolar transistor 12 is connected to the low potential terminal (cathode terminal C), the base of the NPN bipolar transistor 12 is connected to the collector of the PNP bipolar transistor 14, and the NPN bipolar transistor The bases of 12 and the collector of the PNP bipolar transistor 14 are connected to a low potential terminal (cathode terminal) via a second resistor R2 made of resistance components of the first conductive type semiconductor substrate 1 and the first conductive type low concentration diffusion layer 2. C), and the collector of the NPN bipolar transistor 12 and the base of the PNP bipolar transistor 14 are connected to the high potential terminal (anode terminal) via the first resistor R1 made of the resistance component of the low-concentration diffusion layer 4 of the second conductivity type. A) connected to the PNP bipo The emitter of La transistor 14 is connected to the anode of the diode 13, the cathode of the diode 13 is connected to the high potential terminal (anode terminal A).
About the IV characteristic and effect at the time of the surge current application in the ESD protection element 21B of this Embodiment 3, it is the same as that of the said Embodiment 1, About the control of the reverse junction withstand voltage (voltage addition part) of the diode 13. The distance A in FIG. 2 and the diffusion concentration of the second conductivity type diffusion layer 6B can be freely controlled.

  The effect of increasing the holding voltage Vh can be doubled by combining the diode 13 of the first or second embodiment and the diode 13 of the third embodiment.

  In the third embodiment, in the ESD protection circuit 11B of the semiconductor integrated circuit, the P-type semiconductor substrate 1 is used, and the high potential terminal (anode terminal A) is connected to the emitter of the PNP bipolar transistor 14 through the diode 13 in the reverse direction. As well as being connected to the base of the PNP bipolar transistor 14 and the collector of the NPN bipolar transistor 12 via the first resistor R1, the low potential terminal (cathode terminal C) is connected to the emitter of the NPN bipolar transistor 12. The case where the collector of the PNP bipolar transistor 14 and the base of the NPN bipolar transistor 12 are connected via the second resistor R2 has been described. However, the present invention is not limited to this, and as a modified example of the ESD protection circuit 11B of the semiconductor integrated circuit, High potential terminal using N-type semiconductor substrate The anode terminal A) is connected to the emitter of the NPN bipolar transistor via the diode 13 in the reverse direction, and is connected to the base of the NPN bipolar transistor and the collector of the PNP bipolar transistor via the first resistor R1. (Cathode terminal C) may be connected to the emitter of the PNP bipolar transistor and may be connected to the collector of the NPN bipolar transistor and the base of the PNP bipolar transistor via the second resistor R2.

(Embodiment 4)
In the first to third embodiments, the case where a thyristor element (SCR) is used as a snapback characteristic element and a diode element is used as a voltage adding element has been described. In the fourth embodiment, a bipolar transistor is used as a snapback characteristic element. A case where a diode element is used as the voltage adding element will be described.

  FIG. 13 is a longitudinal sectional view of an ESD protection element constituting the ESD protection circuit of the semiconductor integrated circuit according to Embodiment 4 of the present invention. In FIG. 13, members having the same effects as those of the member of FIG.

  In FIG. 13, the ESD protection element 21 </ b> C of the semiconductor integrated circuit according to the fourth embodiment is a second conductivity type (here, N type) low-resistance formed on a first conductivity type (here, P type) semiconductor substrate 1. The first conductivity type semiconductor adjacent to the concentration diffusion layer 4, the second conductivity type high concentration diffusion layer 5 formed on the surface side of the low concentration diffusion layer 4, and the second conductivity type low concentration diffusion layer 4. A first conductivity type low concentration diffusion layer 2 formed on the substrate 1, a second conductivity type diffusion layer 6 formed on the surface of the first conductivity type low concentration diffusion layer 2, and a second conductivity type The first conductivity type high concentration diffusion layer 3 formed at a position opposite to the low concentration diffusion layer 4 with respect to the diffusion layer 6 and the second conductivity type diffusion layer 6 formed on the surface of the diffusion layer 6. 1 conductivity type high concentration diffusion layer 3.

The ESD protection element 21C of the semiconductor integrated circuit according to the fourth embodiment includes an NPN bipolar transistor including a second conductivity type low concentration diffusion layer 4, a first conductivity type low concentration diffusion layer 2, and a first conductivity type diffusion layer 6. 15 and a diode 13 composed of the first conductivity type diffusion layer 6 and the first conductivity type high-concentration diffusion layer 3.
The collector of the NPN bipolar transistor 15 is connected to the high potential terminal, and the base of the NPN bipolar transistor 15 is composed of the first conductive type semiconductor substrate 1 and the first conductive type low concentration diffusion layer 2 and the first resistor R1. Is connected to the low potential terminal, the emitter of the NPN bipolar transistor 15 is connected to the cathode of the diode 13, the anode of the diode 13 is connected to the low potential terminal, and an ESD protection element utilizing bipolar operation is configured. Yes.

  As described above, according to the ESD protection element 21 </ b> C of the semiconductor integrated circuit of the fourth embodiment, the IV characteristics and effects at the time of applying the surge current are the same as those in the first embodiment, and the reverse direction of the diode 13. The control of the junction breakdown voltage can be freely controlled by the distance A shown in FIG. 13 and the diffusion concentration of the diffusion layer 6 of the first conductivity type.

  In the fourth embodiment, in the ESD protection element 21C of the semiconductor integrated circuit, the collector of the NPN bipolar transistor 15 is connected to the high potential terminal using the P-type semiconductor substrate 1, and the base of the NPN bipolar transistor 15 is the first resistor. Although the case where the NPN bipolar transistor 15 is connected to the low potential terminal via the body R1, the emitter of the NPN bipolar transistor 15 is connected to the cathode of the diode 13, and the anode of the diode 13 is connected to the low potential terminal has been described. When an N-type semiconductor substrate is used as a modification of the ESD protection element 21C of the semiconductor integrated circuit, the collector of the PNP bipolar transistor is connected to the high potential terminal, and the base of the PNP bipolar transistor is connected via the first resistor R1. Connected to a low potential terminal, the PNP bipolar transistor The emitter is connected to the cathode of the diode 13, the anode of the diode 13 may be connected to the low potential terminal.

(Embodiment 5)
In the fourth embodiment, the ion implantation process for the second conductivity type (N-type) diffusion layer 6 is performed separately. In the fifth embodiment, the ion implantation process for the second conductivity type (N-type) diffusion layer 6 is performed. The case where the ion implantation process of the second conductivity type (N-type) diffusion layer 6 is not required separately by performing the ion implantation process of the second conductivity type (N-type) low-concentration diffusion layer 4 will be described. .

  FIG. 14 is a vertical cross-sectional view of an ESD protection element of a semiconductor integrated circuit for explaining the simplification of the manufacture of the ESD protection circuit of the semiconductor integrated circuit in Embodiment 5 of the present invention. In FIG. 14, members having the same effects as those of the members in FIG.

  In FIG. 14, the ESD protection element 21D of the semiconductor integrated circuit according to the fifth embodiment includes the first-conductivity-type low-concentration diffusion layer 2 directly below the second-conductivity-type (here, N-type) diffusion layer 6 in FIG. The second conductivity type low-concentration diffusion layer 4 is formed in the region where the second conductivity type diffusion layer 6 is formed without forming the second conductivity type (N type) diffusion layer 6. By simultaneously performing the ion implantation step of the second conductivity type (N-type) low-concentration diffusion layer 4, manufacturing can be simplified in the manufacture of the ESD protection element 21D corresponding to the ESD protection circuit 11D of the semiconductor integrated circuit. it can.

  Even with such a structure, the holding voltage Vh shown in the first embodiment can be controlled, and the same effect as in the first embodiment can be obtained. The control of the reverse junction withstand voltage of the diode can be freely controlled by the distance A shown in FIG. In addition, since the second conductivity type diffusion layer 6 shown in the fifth embodiment is not necessary, it can be realized only by a process necessary for manufacturing a conventional semiconductor substrate.

(Embodiment 6)
In the first to third embodiments, a thyristor element (SCR) is used as the snapback characteristic element. In the fourth and fifth embodiments, the bipolar transistor 15 is used as the snapback characteristic element. In the sixth embodiment, the snapback characteristic element is used. A case where a MOS transistor is used as the characteristic element and a diode element is used as the voltage adding element will be described.

  FIG. 15 is a longitudinal sectional view of an ESD protection element constituting an ESD protection circuit of a semiconductor integrated circuit according to Embodiment 6 of the present invention. In FIG. 15, members having the same effects as those of the member of FIG.

  In FIG. 15, the ESD protection element 21E of the semiconductor integrated circuit according to the sixth embodiment is a low-conductivity type (here, N-type) low-level semiconductor substrate 1 formed on a first-conductivity-type (here, P-type) semiconductor substrate 1. The first conductivity type semiconductor adjacent to the concentration diffusion layer 4, the second conductivity type high concentration diffusion layer 5 formed on the surface side of the low concentration diffusion layer 4, and the second conductivity type low concentration diffusion layer 4. A first conductivity type low concentration diffusion layer 2 formed on the substrate 1, a second conductivity type diffusion layer 6 formed on the surface of the first conductivity type low concentration diffusion layer 2, and a second conductivity type The first conductivity type high concentration diffusion layer 3 formed at a position opposite to the low concentration diffusion layer 4 with respect to the diffusion layer 6 and the second conductivity type diffusion layer 6 formed on the surface of the diffusion layer 6. High conductivity diffusion layer 3 of one conductivity type, part of low concentration diffusion layer 4 of second conductivity type, part of diffusion layer 6 of second conductivity type, and low concentration of second conductivity type A gate electrode 18 formed via a gate oxide film 17 on the surface side of the first conductivity type low concentration diffusion layer 2 formed in a region sandwiched between the diffusion layer 4 and the second conductivity type diffusion layer 6. Have.

The ESD protection element 21E of the semiconductor integrated circuit according to the sixth embodiment includes a second conductivity type low concentration diffusion layer 4, a first conductivity type low concentration diffusion layer 2, a first conductivity type diffusion layer 6, and a gate electrode 8. And a diode 13 having a first conductivity type diffusion layer 6 and a first conductivity type high-concentration diffusion layer 3.
In the ESD protection circuit 11E of the semiconductor integrated circuit according to the sixth embodiment, the drain of the MOS transistor 16 is connected to the high potential terminal, and the body of the MOS transistor 16 has the first conductivity type semiconductor substrate 1 and the first conductivity type low concentration. The first resistor R1 made of the resistance component of the diffusion layer 2 is connected to the low potential terminal, the source of the MOS transistor 16 is connected to the cathode of the diode 13, and the anode of the diode 13 is connected to the low potential terminal. . The ESD protection element 21E of the semiconductor integrated circuit is an ESD protection element using the parasitic bipolar operation of the MOS transistor 16.

  As described above, according to the ESD protection element 21E of the semiconductor integrated circuit of the sixth embodiment, the IV characteristics and effects at the time of applying the surge current are the same as those in the first embodiment, and the reverse direction of the diode 13 The control of the junction breakdown voltage can be freely controlled by the distance A shown in FIG. 15 and the diffusion concentration of the diffusion layer 6 of the first conductivity type.

(Embodiment 7)
In the sixth embodiment, the ion implantation process for the second conductivity type (N-type) diffusion layer 6 is performed separately. In the seventh embodiment, the ion implantation process for the second conductivity type (N-type) diffusion layer 6 is performed. The case where the ion implantation process of the second conductivity type (N-type) diffusion layer 6 is not required separately by performing the ion implantation process of the second conductivity type (N-type) low-concentration diffusion layer 4 will be described. .

  FIG. 16 is a vertical cross-sectional view of an ESD protection element of a semiconductor integrated circuit for explaining the simplification of the production of the ESD protection circuit of the semiconductor integrated circuit in Embodiment 7 of the present invention. In FIG. 16, members having the same functions and effects as those in FIG. 15 are denoted by the same reference numerals.

  In FIG. 16, the ESD protection element 21F of the semiconductor integrated circuit according to the seventh embodiment includes the first conductivity type low-concentration diffusion layer 2 immediately below the second conductivity type (N type) diffusion layer 6 in FIG. The second conductivity type low-concentration diffusion layer 4 is formed in the region where the second conductivity type diffusion layer 6 is formed without forming the second conductivity type (N type) diffusion layer 6. By simultaneously performing the ion implantation step of the second conductivity type (N-type) low-concentration diffusion layer 4, manufacturing can be simplified in the manufacture of the ESD protection element 21F corresponding to the ESD protection circuit 11F of the semiconductor integrated circuit. it can.

  Even with such a structure, the holding voltage Vh shown in the first embodiment can be controlled, and the same effect as in the first embodiment can be obtained. The control of the reverse junction breakdown voltage of the diode can be freely controlled by the distance A shown in FIG. Further, since the second conductivity type diffusion layer 6 shown in the sixth embodiment is not necessary, it can be realized only by a process necessary for manufacturing a conventional semiconductor substrate.

  As described above, according to the first to seventh embodiments, the reverse junction withstand voltage of the diode 13 suppresses an increase in layout area as compared with the conventional structure, and does not cause a significant decrease in protection capability. Can be easily controlled to an appropriate voltage, and an ESD protection element optimal for various power supply voltages can be realized.

  In the first to seventh embodiments, the diode 13 is used as the voltage adding element that adds the snapback start voltage Vt1 by the element voltage and raises the holding voltage twice as much as the element voltage. As shown in FIG. 17, instead of one or more diodes 13, one or more transistors 19 having a control terminal (gate or base) connected to an output terminal (source or drain terminal or collector or emitter terminal). Can also be used. In this case, the holding voltage is twice as high as the element voltage (for example, source-drain voltage).

  As mentioned above, although this invention has been illustrated using preferable Embodiment 1-7 of this invention, this invention should not be limited and limited to this Embodiment 1-7. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range based on the description of the present invention and the common general technical knowledge from the description of specific preferred embodiments 1 to 7 of the present invention. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to an ESD protection circuit for a semiconductor integrated circuit having a snapback characteristic in which a current flows when a breakdown starts due to a surge voltage, and the voltage rapidly decreases, and performs ESD protection on a protected element, and its ESD protection In the element field, the voltage adding element adds the snapback start voltage by the element voltage and makes the holding voltage twice as high as the element voltage, thereby suppressing an increase in layout area and protecting capability compared to the conventional structure. The holding voltage Vh can be controlled to an appropriate voltage equal to or higher than the power supply voltage without causing a significant decrease.

DESCRIPTION OF SYMBOLS 1 1st conductivity type semiconductor substrate 2 1st conductivity type low concentration diffusion layer 3 1st conductivity type high concentration diffusion layer 4 2nd conductivity type low concentration diffusion layer 5 2nd conductivity type high concentration diffusion layer 6 1st 2 conductivity type diffusion layer 7 element isolation insulating film 8 interlayer insulating film 9 anode terminal (high potential terminal)
10 Cathode terminal (low potential terminal)
11, 11B, 11E Semiconductor integrated circuit ESD protection circuit 12 NPN bipolar transistor 13 Diode (diode element)
DESCRIPTION OF SYMBOLS 14 PNP bipolar transistor 15 NPN bipolar transistor 16 MOS transistor part 17 Gate oxide film 18 Gate electrode 19 Transistor 21, 21A-21F ESD protection element VB Reverse junction breakdown voltage (element voltage)
A Anode terminal (high potential terminal)
C Cathode terminal (low potential terminal)
R1, R2 resistance Vt1 Snapback start voltage (Snapback operating voltage)
Vh holding voltage

Claims (23)

  A snapback characteristic element having a snapback characteristic in which a large current flows after the breakdown starts due to a surge voltage and the voltage suddenly drops from the snapback start voltage to the holding voltage; and the snapback characteristic element is connected to the snapback characteristic element. A voltage adding element for adding the back start voltage by the element voltage and making the holding voltage higher than the power supply voltage; adjusting the element voltage of the voltage adding element; An ESD protection circuit for a semiconductor integrated circuit, which is adjusted to be equal to or lower than a withstand voltage of a protection element.   The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the voltage adding element makes the holding voltage twice as high as the element voltage.   2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the snapback characteristic element is any one of a thyristor element, a bipolar transistor, and a MOS transistor.   2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the voltage adding element is one or a plurality of diode elements or one or a plurality of transistors having a control terminal connected to an output terminal.   The high potential terminal is connected to the emitter of the PNP bipolar transistor, and is connected to the base of the PNP bipolar transistor and the collector of the NPN bipolar transistor via the first resistor, and the low potential terminal is connected to the diode element in the forward direction. 2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the ESD protection circuit is connected to an emitter of the NPN bipolar transistor and is connected to a collector of the PNP bipolar transistor and a base of the NPN bipolar transistor through a second resistor.   The high potential terminal is connected to the emitter of the PNP bipolar transistor through the diode element in the reverse direction, and is connected to the base of the PNP bipolar transistor and the collector of the NPN bipolar transistor through the first resistor. 2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the ESD protection circuit is connected to an emitter of the NPN bipolar transistor and is connected to a collector of the PNP bipolar transistor and a base of the NPN bipolar transistor through a second resistor.   The high potential terminal is connected to the emitter of the NPN bipolar transistor, and is connected to the base of the NPN bipolar transistor and the collector of the PNP bipolar transistor through the first resistor, and the low potential terminal is connected to the diode element in the forward direction. 2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the ESD protection circuit is connected to an emitter of the PNP bipolar transistor and is connected to a collector of the NPN bipolar transistor and a base of the PNP bipolar transistor through a second resistor.   The high potential terminal is connected to the emitter of the NPN bipolar transistor via the diode element in the reverse direction, and is connected to the base of the NPN bipolar transistor and the collector of the PNP bipolar transistor via the first resistor. 2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the ESD protection circuit is connected to an emitter of the PNP bipolar transistor and is connected to a collector of the NPN bipolar transistor and a base of the PNP bipolar transistor through a second resistor.   The collector of the NPN bipolar transistor is connected to the high potential terminal, the base of the NPN bipolar transistor is connected to the low potential terminal through the first resistor, the emitter of the NPN bipolar transistor is connected to the cathode of the diode element, 2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein an anode of a diode element is connected to the low potential terminal.   The collector of the PNP bipolar transistor is connected to the high potential terminal, the base of the PNP bipolar transistor is connected to the low potential terminal through the first resistor, the emitter of the PNP bipolar transistor is connected to the cathode of the diode element, 2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein an anode of a diode element is connected to the low potential terminal.   The drain of the MOS transistor is connected to the high potential terminal, the body of the MOS transistor is connected to the low potential terminal via the first resistor, the gate of the MOS transistor is connected to the low potential terminal, and the source of the MOS transistor 2. The ESD protection circuit for a semiconductor integrated circuit according to claim 1, wherein the diode is connected to a cathode of a diode element, and an anode of the diode is connected to the low potential terminal. The ESD protection circuit for a semiconductor integrated circuit according to claim 4, wherein the element voltage is a reverse junction breakdown voltage of the diode element. An ESD protection element for a semiconductor integrated circuit, comprising the ESD protection circuit for a semiconductor integrated circuit according to claim 1. An ESD protection element for a semiconductor integrated circuit comprising the ESD protection circuit for a semiconductor integrated circuit according to claim 5 or 9,
An ESD protection element of a semiconductor integrated circuit, wherein a diffusion layer forming an emitter of the NPN bipolar transistor and a diffusion layer forming a cathode of the diode element are common. An ESD protection element for a semiconductor integrated circuit comprising the ESD protection circuit for a semiconductor integrated circuit according to claim 7 or 10,
An ESD protection element of a semiconductor integrated circuit, wherein a diffusion layer forming an emitter of the PNP bipolar transistor and a diffusion layer forming a cathode of the diode element are common. An ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit according to claim 6,
An ESD protection element of a semiconductor integrated circuit, wherein a diffusion layer forming an emitter of the PNP bipolar transistor and a diffusion layer forming an anode of the diode element are common. An ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit according to claim 8,
An ESD protection element of a semiconductor integrated circuit, wherein a diffusion layer forming an emitter of the NPN bipolar transistor and a diffusion layer forming an anode of the diode element are common. An ESD protection element for a semiconductor integrated circuit comprising the ESD protection circuit for a semiconductor integrated circuit according to claim 11,
An ESD protection element of a semiconductor integrated circuit, wherein a diffusion layer forming a source of the MOS transistor and a diffusion layer forming a cathode of the diode element are common. An ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit according to claim 5,
An ESD protection element for a semiconductor integrated circuit, wherein a base of the PNP bipolar transistor, an emitter of the NPN bipolar transistor, and a cathode of the diode element are formed simultaneously. An ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit according to claim 7,
An ESD protection element for a semiconductor integrated circuit, wherein a base of the NPN bipolar transistor and an emitter of the PNP bipolar transistor and a cathode of the diode element are formed simultaneously. An ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit according to claim 9,
An ESD protection element for a semiconductor integrated circuit, wherein a collector of the NPN bipolar transistor, an emitter of the NPN bipolar transistor, and a cathode of the diode element are formed simultaneously. An ESD protection element of a semiconductor integrated circuit comprising the ESD protection circuit of the semiconductor integrated circuit according to claim 10,
An ESD protection element for a semiconductor integrated circuit, wherein a collector of the PNP bipolar transistor, an emitter of the PNP bipolar transistor, and a cathode of the diode element are formed simultaneously. An ESD protection element for a semiconductor integrated circuit comprising the ESD protection circuit for a semiconductor integrated circuit according to claim 11,
An ESD protection element of a semiconductor integrated circuit, wherein the drain of the MOS transistor, the source of the MOS transistor, and the cathode of the diode element are formed simultaneously.