JP2011176091A - Protective circuit for semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protective circuit for a semiconductor element capable of suppressing an influence of an increase of a circuit element size or a variation of an element in manufacturing without deteriorating characteristics of a lateral double-diffused MOS transistor (LDMOS). <P>SOLUTION: An output of a back gate of LDMOS 110 is used as a trigger, and an ESD surge applied to an output terminal 120 connected to the drain of LDMOS is made to flow to a ground terminal 122 via a high withstand voltage MOS 140 and a low withstand voltage MOS 142 connected in series. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a protection circuit for a semiconductor device, and more particularly to a circuit for protecting a lateral double diffused MOS transistor (LDMOS) used as an output transistor.

  With reference to FIG. 7, a description will be given of a high voltage MOS (HVMOS) that can be used even in a circuit having a power supply voltage of 10 V or more. FIG. 7 is a schematic diagram for explaining the HVMOS, and shows a cut end face of a main part.

  An N-type buried layer 25 is formed on a P-type silicon substrate 20, and an N-type epitaxial layer 30 is formed on the silicon substrate 20 on which the N-type buried layer 25 is formed. A P-type well 32 is formed in the N-type epitaxial layer 30. A field oxide film 40 is formed on the P-type well 32 and defines a gate region 42, a drain region 44 and a source region 46.

  In the gate region 42, a gate oxide film 52 and a gate electrode 54 are sequentially formed on the N-type epitaxial layer 30.

  In the drain region 44 and the source region 46, N-type diffusion layers 34 and 36 are formed. Further, in order to relax the electric field of the diffusion layer (drain) 34 in the drain region 44, between the gate region 42 and the drain region 44 and between the gate region 42 and the source region 46, below the field oxide film 40. N-type low concentration diffusion layers 35 and 37 are formed.

  In the HVMOS 10, by increasing the gate length, the depletion layer is prevented from reaching the diffusion layer (source) 36 in the source region 46 from the drain 34, thereby ensuring the drain breakdown voltage. In the HVMOS 10, the gate length is long to secure the drain breakdown voltage, and the low-concentration diffusion layers 35 and 37 are provided, so that the on-resistance is high.

  On the other hand, the LDMOS has a high breakdown voltage similar to that of the HVMOS, but can be easily reduced in on-resistance. For this reason, the LDMOS is used for a Power MOS device such as a DC / DC converter or a switching element. The LDMOS will be described with reference to FIG. FIG. 8 is a schematic diagram for explaining an LDMOS, and shows a cut end face of a main part.

  An N-type buried layer 25 is formed on a P-type silicon substrate 20, and an N-type epitaxial layer 30 is formed on the silicon substrate 20 on which the N-type buried layer 25 is formed. A field oxide film 60 is formed on the N type epitaxial layer 30 to define a drain region 62 and a source region 64.

  A gate oxide film 52 and a gate electrode 54 are sequentially formed on the N type epitaxial layer 30 on the drain region 62 side of the source region 64. In the source region 64, the P-type body 33 is formed in a region 66 where the gate electrode 54 is not formed, and a partial region below the gate electrode 54 and the field oxide film 60 adjacent to the region 66. ing. The P-type body 33 is formed with a source 38 which is an N-type diffusion layer and a P-type contact 39 for taking out the potential of the P-type body 33. In the drain region 62, a drain 34 that is an N-type diffusion layer is formed.

  In the LDMOS 11, a channel is formed by utilizing a difference in spread due to diffusion of the P-type body 33 and the source 38. For this reason, a short channel can be formed, and it is easy to reduce the on-resistance.

  Further, in the LDMOS 11, the portion of the N-type epitaxial layer 30 relaxes the electric field of the drain, similarly to the low concentration diffusion layers 35 and 37 of the HVMOS 10. The impurity concentration of the N-type epitaxial layer 30 is about the same as that of the low-concentration diffusion layers 35 and 37 of the HVMOS 10, but the thickness of the N-type epitaxial layer 30 is about several μm to several tens of μm. The resistance value is suppressed lower than that of the layers 35 and 37.

  In LDMOS, a large gate width of 5000 μm to 30000 μm is often used for large current driving and low on-resistance. In addition, by reducing the active margin to the minimum value of the design standard, the portion that becomes parasitic resistance is reduced, and the on-resistance is reduced.

  However, LDMOS has a disadvantage that it has a low electrostatic discharge (ESD) resistance even when the gate width is increased to 5000 μm to 30000 μm. With reference to FIGS. 9A and 9B, a relationship between a human body model (HBM) tolerance and a gate width will be described as an example of an ESD tolerance. FIG. 9B is an enlarged view of the portion of FIG. 9A where the gate width W is 2000 μm or less.

  9A and 9B, the horizontal axis indicates the gate width W [μm], and the vertical axis indicates the HBM tolerance [V]. Here, the HBM tolerance is a voltage when leakage occurs between the drain and the source or when the drain and the source are short-circuited in the HBM test. 9 (A) and 9 (B), the LDMOS HBM tolerance (indicated by ■ in FIG. 9) and the low breakdown voltage MOS (LVMOS) HBM tolerance (in FIG. 9, the applied voltage is 6V or less). Indicated by ●.

  LVMOS (●) has a large dependence on the gate width W of the HBM resistance, and is about 470 V / 100 μm. For this reason, if the gate width W is increased, the HBM resistance is improved.

  On the other hand, in LDMOS (■), the dependency of the HBM resistance on the gate width W is small and is about 4 V / 100 μm. For this reason, it is difficult to improve the ESD tolerance by increasing the gate width W. Therefore, when LDMOS is used, a protection element is generally added to improve ESD tolerance (see, for example, Patent Documents 1 and 2).

  With reference to FIG. 10, a structure disclosed in Patent Document 1 for improving ESD resistance by incorporating a thyristor into an LDMOS will be described as a configuration in which a protection element is added. FIG. 10 is a schematic diagram for explaining a configuration in which a thyristor is incorporated in an LDMOS, and shows a cut end surface of a main part.

  In the conventional LDMOS described with reference to FIG. 8, when an ESD surge is applied, a parasitic NPN composed of the drain 34-P-type body 33-source 38 is turned on. After the parasitic NPN is turned on, local electric field concentration occurs at the end of the drain 34, and current concentration occurs in that portion. For this reason, the dependence of the ESD tolerance on the gate width is reduced, and it is difficult to obtain a desired ESD tolerance.

  In contrast, the structure shown in FIG. 10 has a structure in which a so-called thyristor is incorporated in the drain region 62 by providing a P-type region that becomes the anode 31 of the thyristor. In the LDMOS 12 incorporating this thyristor, when the parasitic NPN is turned on, the thyristor is turned on. As a result, since a large current can be passed, the ESD tolerance is improved.

  With reference to FIG. 11, a structure in which an NMOS (protective NMOS) is added as a protective element will be described. FIG. 11 is a circuit diagram for explaining a configuration in which a protective NMOS is added to an LDMOS.

  The protective NMOS 107 is provided in parallel with the LDMOS 110 between the output terminal 120 connected to the drain of the LDMOS 110 which is an output transistor and the ground terminal 122 connected to the source of the LDMOS 110. In this structure, the LDMOS 110 and the protection NMOS 107 are configured to be separated from each other and are connected by metal wiring.

  With reference to FIG. 12, the operation in the configuration in which a protective NMOS is added to the LDMOS described with reference to FIG. 11 will be described. FIG. 12 is a current-voltage (IV) characteristic diagram for explaining the operation in the configuration in which the protective NMOS is added to the LDMOS. In FIG. 12, the horizontal axis represents the voltage [V] applied to the output terminal, and the vertical axis represents LDMOS (indicated by ▪ in FIG. 12) or protective NMOS (indicated by ◆ in FIG. 12). The flowing current [A] is shown.

  In this case, if the parasitic bipolar operating point voltage Vt1 of the protective NMOS is set higher than the maximum value VDDMAX of the power supply voltage and lower than the bipolar operating point voltage Vt3 of the LDMOS, it is lower than the maximum value VDDMAX of the power supply voltage. When a high ESD voltage is applied to the output terminal 120, the protective NMOS 107 starts the bipolar operation before the LDMOS 110 starts the bipolar operation, so that the destruction of the LDMOS 110 can be prevented.

  A structure using a thyristor and a trigger element disclosed in Patent Document 2 will be described with reference to FIG. FIG. 13 is a circuit diagram for explaining a structure using thyristors and trigger elements.

  In this structure, the resistance element 106 is provided between the source of the output transistor 111 and the ground terminal (GND) 122. When a current flows between the drain and the source, the potential of the source increases by the amount of voltage drop at the resistance element 106. As the source potential rises, the trigger element 108 is turned on, whereby the thyristor 109 is triggered. As a result, the output transistor 111 is protected.

JP 2001-320047 A JP 2009-123751 A

  However, the prior art configurations described with reference to FIGS. 10, 11 and 13 each have problems to be solved.

  With reference to FIGS. 14A and 14B, the element area of the LDMOS will be described. FIGS. 14A and 14B are top views for explaining the element area of the LDMOS. 14A corresponds to the LDMOS described with reference to FIG. 8, and FIG. 14B corresponds to the LDMOS described with reference to FIG.

  In the configuration shown in FIG. 14B, the element area of the LDMOS increases as compared with the configuration shown in FIG. 14A by adding the anode 31 for thyristor operation to the drain region. The anode 31 is the same size as the drain 34. Therefore, in the LDMOS having a large gate width, the influence of the increase in the element area due to the addition of the anode 31 is increased.

  In the configuration described with reference to FIG. 11, the bipolar operating point voltage Vt1 of the protection NMOS 107 needs to be within an ESD design window (EDW: ESD Design Window). Here, EDW indicates a range that can be taken by the bipolar operating point voltage Vt1 of the protective NMOS, and is a range that is not less than the maximum value VDDMAX of the power supply voltage and not more than the bipolar operating point voltage Vt3 of the LDMOS.

  When the bipolar operating point voltage Vt1 is smaller than the maximum value VDDMAX of the power supply voltage, when the voltage is raised to the vicinity of the maximum value VDDMAX of the power supply voltage, the protective NMOS causes a bipolar operation and applies an appropriate voltage to other elements. It may not be possible. On the other hand, if the bipolar operating point voltage Vt1 is larger than the bipolar operating point voltage Vt3 of the LDMOS 110, the LDMOS 110 starts the bipolar operation in response to the ESD surge before the protective NMOS 107 starts the bipolar operation. It will cause destruction. For this reason, the bipolar operating point voltage Vt1 of the protection NMOS 107 needs to be stored in the EDW.

  Here, for example, by increasing the impurity concentration of the N-type epitaxial layer 30, the on-resistance of the LDMOS can be lowered. In this case, the drain breakdown voltage Vt2 is also lowered. Therefore, when a low on-resistance is required, such as when an LDMOS is used as an output transistor, the drain withstand voltage Vt2 should be as small as possible. For this reason, the width of the EDW may be about 3 to 4V.

  However, EDW needs to be about 10V in order to absorb the variations that occur during manufacturing of the bipolar operating point voltage Vt1 of the protective NMOS 107 and the bipolar operating point voltage Vt3 of the LDMOS 110.

  Therefore, it is difficult to adopt the configuration described with reference to FIG.

  In the configuration described with reference to FIG. 13, the resistor element 106 is inserted between the source of the output transistor 111 and the ground terminal 122 in order to trigger the thyristor 109.

  However, when an LDMOS characterized by low on-resistance is used as an output transistor, the on-resistance is increased by a resistance element provided between the source and ground terminal of the LDMOS, which is not realistic.

  The present invention has been made in view of the above-mentioned problems, and an object of the present invention is an LDMOS protection circuit used as an output transistor, which does not deteriorate the characteristics of the LDMOS and is a circuit element. An object of the present invention is to provide a semiconductor element protection circuit capable of suppressing the influence of an increase in size and variations in manufacturing of each element.

  In order to achieve the above object, the protection circuit of the present invention is applied to the output terminal connected to the first main electrode region (drain) of the LDMOS using the LDMOS substrate current (back gate output) as a trigger. The ESD surge is caused to flow to the ground terminal through the high voltage MOS and the low voltage MOS connected in series.

  For this purpose, the protection circuit according to the first invention is provided in parallel with the LDMOS between the output terminal connected to the drain of the LDMOS and the ground terminal connected to the second main electrode region (source) of the LDMOS. A high breakdown voltage MOS, a low breakdown voltage MOS, and a resistance element.

  The drain of the high voltage MOS is connected to the output terminal, the source and the back gate are connected to the drain of the low voltage MOS, and the control electrode (gate) is connected to the ground terminal via the resistance element. The source, gate, and back gate of the low breakdown voltage MOS are connected to the ground terminal, and the back gate of the LDMOS is connected to the gate of the high breakdown voltage MOS.

  According to the preferred embodiment of the protection circuit described above, the drain of the high voltage MOS is preferably connected to a virtual output terminal connected to the output terminal via a diode.

  The protection circuit according to the second aspect of the present invention is provided in parallel with the LDMOS between the output terminal connected to the drain of the LDMOS and the ground terminal connected to the source of the LDMOS. It comprises a breakdown voltage MOS, a low breakdown voltage MOS and a resistance element.

  The drain of the high voltage MOS is connected to the output terminal, the source and the back gate are connected to the drain of the low voltage MOS, and the gate is connected to the ground terminal via the resistance element. The source, gate and back gate of the low breakdown voltage MOS are connected to the ground terminal, the drain of the trigger LDMOS is connected to the output terminal, and the back gate of the trigger LDMOS is connected to the gate of the high breakdown voltage MOS.

  According to the preferred embodiment of the protection circuit described above, the drain of the high voltage MOS and the drain of the trigger LDMOS are preferably connected to a virtual output terminal connected to the output terminal via a diode.

  According to the protection circuit for protecting an LDMOS of the present invention, it is possible to suppress the influence of an increase in circuit element size and variations in manufacturing of each element without deteriorating the characteristics of the LDMOS.

It is a circuit diagram of the protection circuit of 1st Embodiment. It is a circuit diagram of the protection circuit of 2nd Embodiment. It is a circuit diagram of the protection circuit of 3rd Embodiment. It is a circuit diagram of the protection circuit of 4th Embodiment. It is a circuit diagram of the protection circuit of 5th Embodiment. It is a circuit diagram of the protection circuit of 6th Embodiment. It is the schematic for demonstrating HVMOS. It is the schematic for demonstrating LDMOS. It is the schematic for demonstrating the relationship between HBM tolerance and gate width as an example of ESD tolerance. It is the schematic for demonstrating the structure which incorporates a thyristor in LDMOS. It is the schematic for demonstrating the structure which adds protection NMOS to LDMOS. It is a characteristic view for demonstrating operation | movement by the structure which added protection NMOS to LDMOS. It is a characteristic view for demonstrating the structure using a thyristor and a trigger element. It is a top view for demonstrating the element area of LDMOS.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the shape, size, and arrangement relationship of each component are merely schematically shown to the extent that the present invention can be understood. In the following, a preferred configuration example of the present invention will be described. However, the material and numerical conditions of each component are merely preferred examples. Therefore, the present invention is not limited to the following embodiments, and many changes or modifications that can achieve the effects of the present invention can be made without departing from the scope of the configuration of the present invention.

(First embodiment)
A circuit for protecting an LDMOS used as an output transistor will be described as a protection circuit of the first embodiment with reference to FIG. FIG. 1 is a circuit diagram of a protection circuit according to the first embodiment.

  The protection circuit 130 of the first embodiment is provided in parallel with the LDMOS 110 between the output terminal 120 connected to the drain of the LDMOS 110 and the ground terminal 122 connected to the source of the LDMOS 110.

  The protection circuit 130 includes a high voltage MOS (HVMOS) 140, a low voltage MOS (LVMOS) 142, and a resistance element 144. The HVMOS 140 and the LVMOS 142 are provided in series between the output terminal 120 and the ground terminal 122. That is, the drain that is the first main electrode region of the HVMOS 140 is connected to the output terminal 120, the source that is the second main electrode region of the HVMOS 140 is connected to the drain of the LVMOS 142, and the source of the LVMOS 142 is connected to the ground terminal 122. .

  A gate which is a control electrode of the HVMOS 140 is connected to the ground terminal 122 through the resistance element 144. Further, the back gate of the HVMOS 140 is connected to the source of the HVMOS 140. That is, the source and back gate of the HVMOS 140 are connected to the drain of the LVMOS 142. Here, the back gate is an electrode (substrate electrode) for extracting a substrate current.

  The gate and back gate of the LVMOS 142 are connected to the source of the LVMOS 142. That is, the source, gate, and back gate of the LVMOS 142 are connected to the ground terminal 122.

  The maximum voltage applied to the LDMOS 110 is assumed to be VDDMAX. The drain breakdown voltage of the LDMOS 110 is Vt2, and the bipolar operating point voltage is Vt3. When VDDMAX is about 24V, Vt2 and Vt3 are set to 32V and 40V, respectively.

  Here, an operation when an ESD voltage exceeding VDDMAX is applied to the output terminal 120 in the case where the protection circuit 130 is not provided in the LDMOS 110 will be described. When the applied voltage exceeds the drain breakdown voltage Vt2 of the LDMOS 110, a current flows from the drain toward the back gate or the like. Further, when the voltage applied to the output terminal 120 reaches the bipolar operating point voltage Vt3, the parasitic bipolar of the LDMOS 110 is turned on. Here, when the parasitic bipolar of the LDMOS is turned on and an ESD surge flows thereby, local current concentration occurs at the end of the drain, leading to destruction of the LDMOS 110.

  In contrast, in this embodiment, when a voltage equal to or higher than a predetermined voltage is applied to the output terminal 120, the LDMOS 110 is protected by causing an ESD surge to flow to the ground terminal 122 through the protection circuit 130.

  Here, the sum of the breakdown voltages of the HVMOS 140 and the LVMOS 142 is set to be higher than VDDMAX. With this setting, no current flows through the protection circuit 130 during normal operation.

  With this configuration, when a voltage exceeding the drain breakdown voltage Vt2 of the LDMOS 110 is applied to the output terminal 120, a current flows from the drain of the LDMOS 110 toward the back gate. This current is sent to the ground terminal 122 through the resistance element 144. Since the back gate of the LDMOS 110 is connected to the gate of the HVMOS 140, when a current flows through the back gate, the potential of the gate of the HVMOS 140 increases by the amount of the voltage drop in the resistance element 144.

  For example, when the resistance value of the resistance element 144 is 10 kΩ, the potential of the gate of the HVMOS 140 becomes 1V when the current flowing through the back gate is 100 μA. Therefore, if the threshold voltage of the HVMOS 140 is 1V, the HVMOS 140 is turned on.

  When the HVMOS 140 is turned on due to the rise in the gate potential, the potential between the output terminal 120 and the ground terminal 122 is applied between the drain and source of the LVMOS 142. As a result, the parasitic NPN of the LVMOS 142 is turned on, and the ESD current flows to the ground terminal 122 through the LVMOS 142.

  According to the protection circuit of the first embodiment, it is possible to protect the LDMOS as an output transistor without deteriorating the characteristics of the LDMOS and suppressing the influence of an increase in circuit element size and variations in manufacturing of each element. Can do.

(Second Embodiment)
With reference to FIG. 2, a circuit for protecting an LDMOS used as an output transistor will be described as a protection circuit of the second embodiment. FIG. 2 is a circuit diagram of the protection circuit of the second embodiment.

  The protection circuit 131 of the second embodiment is different from the protection circuit of the first embodiment in that it further includes a trigger LDMOS 146. Since the connection relationship between the HVMOS 140, the LVMOS 142, and the resistance element 144 and the respective configurations are the same as those in the first embodiment, the description thereof is omitted.

  The drain of the trigger LDMOS 146 is connected to the output terminal 120, and the back gate of the trigger LDMOS 146 is connected to the gate of the HVMOS 140. The source and gate of the trigger LDMOS 146 are connected to the gate of the HVMOS 140.

  The output transistor LDMOS (output LDMOS) 110 and the trigger LDMOS 146 can be configured in the same manner, but the drain breakdown voltage of the trigger LDMOS 146 is higher than VDDMAX and is higher than the drain breakdown voltage Vt2 of the output LDMOS 110. It is set low.

  With this configuration, when an ESD surge is applied to the output terminal, a current flows through the back gate of the trigger LDMOS 146 before the output LDMOS 110 operates against the applied ESD surge. Similar to the embodiment, the gate potential of the HVMOS 140 increases. Due to this rise in the gate potential, the HVMOS 140 is turned on, and then the parasitic NPN of the LVMOS 142 is turned on, so that the ESD current flows to the ground terminal 122 through the protection circuit 131.

  In this configuration, the drain breakdown voltage of the trigger LDMOS 146 needs to be within the EDW. However, since the trigger LDMOS 146 and the output LDMOS 110 have the same configuration, they are similarly subjected to variations during manufacturing. That is, when the breakdown voltage of the trigger LDMOS is lower than a set value, the breakdown voltage of the output LDMOS is generally lowered to the same extent. Therefore, the drain withstand voltage may be designed in consideration of variations in manufacturing the trigger LDMOS.

  According to the protection circuit of the second embodiment, the same effect as that of the protection circuit of the first embodiment can be obtained. Further, since the operation is performed at a voltage lower than the drain withstand voltage Vt2 of the output LDMOS, it is possible to prevent the output LDMOS from being destroyed.

(Third embodiment)
With reference to FIG. 3, a circuit for protecting an LDMOS used as an output transistor will be described as a protection circuit of the third embodiment. FIG. 3 is a circuit diagram of the protection circuit of the third embodiment.

  The protection circuit 132 according to the third embodiment is different from the second embodiment in that the source and gate of the trigger LDMOS 146 are connected to the ground terminal 122 via different resistance elements 148 and 150, respectively. That is, in the third embodiment, separate resistance elements 144, 148, and 150 are provided independently for the gate, source, and back gate of the trigger LDMOS 146, respectively. In this configuration, resistance elements having appropriate resistance values can be provided for the gate, source, and back gate of the trigger LDMOS.

  For example, the back gate of the trigger LDMOS 146 is connected to the ground terminal 122 via a 100Ω resistive element 144. The source of the trigger LDMOS 146 is connected to the ground terminal 122 via a 1 kΩ resistance element 148. The gate of the trigger LDMOS 146 is connected to the ground terminal 122 via a 1 kΩ resistance element 150.

  As described above, when the resistance value of the resistance elements 148 and 150 connected to the source and the gate is made larger than the resistance value of the resistance element 144 connected to the back gate, the trigger LDMOS 146 operates against the ESD surge. In addition, most of the ESD surge current flows to the back gate, and the current flowing to the source and gate becomes small. As a result, it is possible to prevent the trigger LDMOS 146 from being damaged by the ESD surge.

  In general, the drain breakdown voltage of the LDMOS is larger than the gate film breakdown voltage. For this reason, when the electric field due to the ESD surge exceeds the drain breakdown voltage, the gate oxide film may be destroyed. However, the resistance value of the resistance element connected to the source is made larger than the resistance value of the resistance element connected to the back gate, and the resistance value of the resistance element connected to the gate is further increased, whereby the gate oxide film Destruction can be prevented.

(Fourth embodiment)
With reference to FIG. 4, a circuit for protecting an LDMOS used as an output transistor will be described as a protection circuit of the fourth embodiment. FIG. 4 is a circuit diagram of a protection circuit according to the fourth embodiment.

  The protection circuit 133 according to the fourth embodiment is different from the protection circuits according to the second and third embodiments in that the source and gate of the trigger LDMOS are connected to each other. Since the connection relationship between the HVMOS 140, the LVMOS 142, and the resistance element 144 and the respective configurations are the same as those in the first to third embodiments, the description thereof is omitted.

  In this configuration, when an ESD surge is applied to the trigger LDMOS 146, the diode operates in the reverse direction withstand voltage between the drain and the back gate. In this case, since the reverse current of the diode turns on the HVMOS 140, it is possible to prevent the trigger LDMOS from being destroyed by an ESD surge, such as the gate oxide film. In addition, since the resistance elements provided at the source and the gate are not required as compared with the protection circuit of the third embodiment, the area of the protection circuit can be reduced.

(Fifth embodiment)
With reference to FIG. 5, a circuit for protecting an LDMOS used as an output transistor will be described as a protection circuit of a fifth embodiment. FIG. 5 is a circuit diagram for explaining the protection circuit of the fifth embodiment.

  The protection circuit 130 of the fifth embodiment is configured in the same manner as the protection circuit of the first embodiment, except that the drain of the HVMOS 140 is connected to the virtual output terminal 124 via the resistance element 128. . The virtual output terminal 124 is connected to the output terminal 120 via a diode 126. In this diode 126, the direction from the output terminal 120 toward the virtual output terminal 124 is the forward direction.

  When an ESD voltage is applied to the output terminal 120, a current flows in the forward direction of the diode 126, and the virtual output terminal 124 has the same potential as the ESD voltage. The subsequent operation is the same as in the first embodiment.

  If comprised in this way, it can be set as the structure which provides one protection circuit with respect to the circuit provided with several LDMOS, and connects the drain of each LDMOS to a virtual output terminal via a diode.

  A modification of the protection circuit of the fifth embodiment will be described with reference to FIG. FIG. 6 is a circuit diagram for explaining a modification of the fifth embodiment.

  In this configuration, the drains of the plurality of LDMOSs 110a and 110b are connected to the output terminals 120a and 120b, respectively. Each output terminal 120a and 120b is connected to one virtual output terminal 124 via diodes 126a and 126b, respectively. One protection circuit 130 is provided for the two LDMOSs 110a and 110b. According to this configuration, the protection circuit 130 operates even when an ESD voltage is applied to either of the output terminals 120a and 120b.

  Therefore, according to the configuration of the fifth embodiment, it is sufficient to prepare one protection circuit for a plurality of LDMOS, and the chip size can be reduced. In addition, although the example of a structure provided with the protection circuit of 1st Embodiment demonstrated with reference to FIG. 1 as a protection circuit was demonstrated here, it is not limited to this. As the protection circuit, the protection circuits of the second to fourth embodiments may be used.

10 HVMOS
11, 12, 110 LDMOS
20 Silicon substrate
25 N-type buried layer
30 N-type epitaxial layer 31 Anode
32 P-type well 33 P-type body 34 Diffusion layer (drain)
35, 37 Low-concentration diffusion layer 36, 38 Diffusion layer (source)
39 P-type contact 40, 60 Field oxide film 42 Gate region 44, 62 Drain region 46, 64 Source region 52 Gate oxide film 54 Gate electrode 66 Region 106, 128, 144, 148, 150 Resistance element 107 Protection NMOS
108 Trigger Element 109 Thyristor 111 Output Transistor 120 Output Terminal 122 Ground Terminal 124 Virtual Output Terminal 126 Diode 130, 131, 132, 133 Protection Circuit 140 HVMOS
142 LVMOS
146 LDMOS for trigger

Claims (11)

Between the output terminal connected to the first main electrode region of the lateral double diffusion MOS transistor and the ground terminal connected to the second main electrode region of the lateral double diffusion MOS transistor, A protection circuit provided in parallel with the double diffusion MOS transistor,
High breakdown voltage MOS transistor, low breakdown voltage MOS transistor and resistance element,
A first main electrode region of the high voltage MOS transistor is connected to the output terminal;
A second main electrode region and a substrate electrode of the high voltage MOS transistor are connected to the first main electrode region of the low voltage MOS transistor;
The control electrode of the high voltage MOS transistor is connected to a ground terminal through the resistance element,
A second main electrode region, a control electrode and a substrate electrode of the low breakdown voltage MOS transistor are connected to a ground terminal;
A protection circuit, wherein a substrate electrode of the lateral double diffusion MOS transistor is connected to a control electrode of the high voltage MOS transistor. Between the output terminal connected to the first main electrode region of the lateral double diffusion MOS transistor and the ground terminal connected to the second main electrode region of the lateral double diffusion MOS transistor, A protection circuit provided in parallel with the double diffusion MOS transistor,
It has a lateral double diffusion MOS transistor for trigger, a high voltage MOS transistor, a low voltage MOS transistor and a resistance element,
A first main electrode region of the high voltage MOS transistor is connected to the output terminal;
A second main electrode region and a substrate electrode of the high voltage MOS transistor are connected to the first main electrode region of the low voltage MOS transistor;
The control electrode of the high voltage MOS transistor is connected to a ground terminal through the resistance element,
A second main electrode region, a control electrode and a substrate electrode of the low breakdown voltage MOS transistor are connected to a ground terminal;
A first main electrode region of the trigger lateral double diffusion MOS transistor is connected to the output terminal;
A protection circuit, wherein a substrate electrode of the trigger lateral double diffusion MOS transistor is connected to a control electrode of the high voltage MOS transistor. The protection circuit according to claim 2, wherein the second main electrode region and the control electrode of the lateral double diffusion MOS transistor for trigger are connected to the control electrode of the high voltage MOS transistor. 3. The protection circuit according to claim 2, wherein the second main electrode region and the control electrode of the lateral double-diffused MOS transistor for trigger are connected to the ground terminal through different resistance elements. 3. The protection circuit according to claim 2, wherein the second main electrode region and the control electrode of the trigger lateral double diffusion MOS transistor are connected to each other. Between the output terminal connected to the first main electrode region of the lateral double diffusion MOS transistor and the ground terminal connected to the second main electrode region of the lateral double diffusion MOS transistor, A protection circuit provided in parallel with the double diffusion MOS transistor,
High breakdown voltage MOS transistor, low breakdown voltage MOS transistor and resistance element,
The first main electrode region of the high voltage MOS transistor is a virtual output terminal, and is connected to the virtual output terminal connected to the output terminal via a diode,
A second main electrode region and a substrate electrode of the high voltage MOS transistor are connected to the first main electrode region of the low voltage MOS transistor;
The control electrode of the high voltage MOS transistor is connected to a ground terminal through the resistance element,
A second main electrode region, a control electrode and a substrate electrode of the low breakdown voltage MOS transistor are connected to a ground terminal;
A protection circuit, wherein a substrate electrode of the lateral double diffusion MOS transistor is connected to a control electrode of the high voltage MOS transistor. Between the output terminal connected to the first main electrode region of the lateral double diffusion MOS transistor and the ground terminal connected to the second main electrode region of the lateral double diffusion MOS transistor, A protection circuit provided in parallel with the double diffusion MOS transistor,
It has a lateral double diffusion MOS transistor for trigger, a high voltage MOS transistor, a low voltage MOS transistor and a resistance element,
The first main electrode region of the high voltage MOS transistor is a virtual output terminal, and is connected to the virtual output terminal connected to the output terminal via a diode,
A second main electrode region and a substrate electrode of the high voltage MOS transistor are connected to the first main electrode region of the low voltage MOS transistor;
The control electrode of the high voltage MOS transistor is connected to a ground terminal through the resistance element,
A second main electrode region, a control electrode and a substrate electrode of the low breakdown voltage MOS transistor are connected to a ground terminal;
A first main electrode region of the trigger lateral double diffusion MOS transistor is connected to the virtual output terminal;
A protection circuit, wherein a substrate electrode of the trigger lateral double diffusion MOS transistor is connected to a control electrode of the high voltage MOS transistor. 8. The protection circuit according to claim 7, wherein the second main electrode region and the control electrode of the lateral double diffusion MOS transistor for trigger are connected to the control electrode of the high voltage MOS transistor. 8. The protection circuit according to claim 7, wherein the second main electrode region and the control electrode of the lateral double diffusion MOS transistor for trigger are connected to the ground terminal through different resistance elements. 8. The protection circuit according to claim 7, wherein the second main electrode region and the control electrode of the trigger lateral double diffusion MOS transistor are connected to each other. A plurality of the output terminals respectively connected to the lateral double-diffused MOS transistor and the first main electrode region of the lateral double-diffused MOS transistor;
The protection circuit according to claim 6, wherein each of the plurality of output terminals is connected to one virtual output terminal via a diode.

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