JPS5879749A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5879749A
JPS5879749A JP17803681A JP17803681A JPS5879749A JP S5879749 A JPS5879749 A JP S5879749A JP 17803681 A JP17803681 A JP 17803681A JP 17803681 A JP17803681 A JP 17803681A JP S5879749 A JPS5879749 A JP S5879749A
Authority
JP
Japan
Prior art keywords
voltage
diode
transistor
zener diode
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17803681A
Other languages
Japanese (ja)
Inventor
Takashi Fuji
藤 隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP17803681A priority Critical patent/JPS5879749A/en
Publication of JPS5879749A publication Critical patent/JPS5879749A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

PURPOSE:To obtain a protective circuit with voltage limiting effect both in the positive and negative directions by a method wherein two diodes are connected in series in the transistor circuit connecting Zener diode between collector and base. CONSTITUTION:One end of Zener diode 6, collector of transistor 7 and one end of diode 8 are connected to terminal 1 while emitter of transistor 7 and the other end of diode 8 are connected to terminal 2. Then the other end of Zener diode 6 and the base of transistor 7 are connected to constitute a protective circuit. When said circuit is connected to an element 3 to be protected, and the terminal 1 is supplied with positive surge voltage, the voltage between the terminal 1 and 2 is limited by the Zener voltage of Zener diode 6 and the voltage between emitter and base of transistor, while if the terminal 1 is supplied with negative surge voltage, the voltage between the terminals 1 and 2 may be limited by the voltage in the forward direction of the diode 8 protecting the element 3.

Description

【発明の詳細な説明】 本発明れ集積回路をサージ電圧あるいは静電気から保護
する保護回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a protection circuit for protecting an integrated circuit from surge voltage or static electricity.

集積回路の検査工程あるいは組立時に加わる静電気によ
り集積回路の内部素子の破壊が生じることがある。従来
この静電気による破壊に対する保護対策として、集積回
路の内部素子に直列に保護抵抗を挿入するかあるいは並
列にダイオードを挿入することにより集積回路内部素子
に加わる静電エネルギーを制限して保護していた。しか
しながら、保護抵抗の抵抗値はあまり大きくできず、電
界により破壊する素子の保護効果は少く、又保護ダイオ
ードでは耐圧の小さい素子の保護はできずこのため、十
分な保護効果社期待できなかった。
Static electricity applied during the testing process or assembly of integrated circuits can cause damage to internal elements of the integrated circuit. Conventionally, as a measure to protect against damage caused by static electricity, the electrostatic energy applied to the internal elements of an integrated circuit was limited and protected by inserting a protective resistor in series with the internal elements of the integrated circuit or by inserting a diode in parallel. . However, the resistance value of the protective resistor cannot be made very large, so the protective effect on elements destroyed by electric fields is small, and the protective diode cannot protect elements with low withstand voltage, so a sufficient protective effect cannot be expected.

本発明の目的は端子に加わる過大入力から内部回路を保
護する十分な保護機能をもった保護回路を備えた集積回
路を受ることにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit equipped with a protection circuit having sufficient protection functions to protect internal circuits from excessive inputs applied to terminals.

本発明によれば、端子にツェナーダイオードとトランジ
スタのコレクタとダイオードとを接続しツェナーダイオ
ードの他端はトランジスタのベースに接続されており、
トランジスタのエミッタとダイオードの他端とを基準電
位端子に接続した保護回路を備える半導体集積回路を得
る。
According to the present invention, the Zener diode, the collector of the transistor, and the diode are connected to the terminal, and the other end of the Zener diode is connected to the base of the transistor,
A semiconductor integrated circuit is obtained which includes a protection circuit in which the emitter of a transistor and the other end of a diode are connected to a reference potential terminal.

次に図面を参照して本発明をより詳細に説明する。Next, the present invention will be explained in more detail with reference to the drawings.

第1図、第2図は端子1−2間に過大な静電圧が加わっ
た場合の従来の保護回路の構成例を示すもので、第1図
の場合は、保護抵抗4により内部素子3を流れる電流を
制限し、また第2図の場合は保護ダイオード5の降イK
により内部素子3に加わる電圧を制限することにより、
それぞれ内部素子3に加わる静電エネルギーを制限して
、その保護を行っている。
Figures 1 and 2 show examples of the configuration of conventional protection circuits when excessive static voltage is applied between terminals 1 and 2. In the case of Figure 1, internal element 3 is protected by protective resistor 4. It limits the flowing current, and in the case of Fig. 2, the voltage drop of the protection diode 5 is
By limiting the voltage applied to the internal element 3,
The electrostatic energy applied to each internal element 3 is limited to protect it.

第1図の抵抗4による保護では、特性上の制約により、
抵抗値を大きくできない場合や、内部素子が、酸化膜コ
ンデンサーや、シlットキーバリアダイオードの逆方向
の様に電界により破壊する素子に対しては、保護できな
い場合がある欠点を有する。
In the protection by resistor 4 in Fig. 1, due to characteristic restrictions,
It has the disadvantage that it may not be able to protect internal elements that are destroyed by electric fields, such as oxide film capacitors and reverse Schittky barrier diodes, or when the resistance value cannot be increased.

また、第2図のダイオードによる保護では、保護ダイオ
ード5を基板および絶縁層とエピタキシャル層で構成す
るかあるいはエピタキシャル層とベース拡散層で構成す
ると逆方向ブレイクダウン電圧が高いため端子1に正の
静電気あるいはサージ電圧が加わった場合には、エミッ
ターベース接合の様に耐圧の低い内部素子に対しては、
電圧制限効果がなく、破壊する場合がある欠点を有する
In addition, in the diode protection shown in Fig. 2, if the protection diode 5 is composed of a substrate, an insulating layer, and an epitaxial layer, or an epitaxial layer and a base diffusion layer, the reverse breakdown voltage is high, so a positive static electricity is generated at the terminal 1. Or, if a surge voltage is applied, internal elements with low withstand voltage such as emitter base junctions may be
It has the disadvantage that it has no voltage limiting effect and may be destroyed.

また第2図の保護ダイオードを絶縁層とエミッタ拡散層
、あるいはベース拡散層と工肴ツタ拡散層のツェナーダ
イオードで構成すると上記欠点はある程度解消するが、
サージ電圧あるいは静電気印加時のツェナーダイオード
の破壊強度を確保するためおよび、内部素子の電圧を制
限するために動作抵抗を小さく設計する必要がある。し
たがって高濃度のPN接合面積を大きくせねばならず、
端子1−2間の寄生容量が大きくなるので、高周波回路
あるいは高インピーダンス回路に適用できない場合があ
る欠点を有する。
Furthermore, if the protection diode shown in Fig. 2 is constructed of a Zener diode with an insulating layer and an emitter diffusion layer, or a base diffusion layer and an ivy diffusion layer, the above drawbacks can be overcome to some extent;
In order to ensure the breakdown strength of the Zener diode when a surge voltage or static electricity is applied, and to limit the voltage of internal elements, it is necessary to design the operating resistance to be small. Therefore, the area of the high concentration PN junction must be increased,
Since the parasitic capacitance between terminals 1 and 2 becomes large, this method has a drawback that it may not be applicable to high frequency circuits or high impedance circuits.

本発明は従来の構造のもつこの様な欠点を解消するもの
である。
The present invention overcomes these drawbacks of conventional structures.

第3図は本発明の一実施例による保護回路の等価回路で
ある。端子1に正の静電気あるいはサージ電圧が加わっ
た場合は端子1−2間の電圧はツェナーダイオード6の
ツェナー電圧とトランジスタ7の工之ツタΦベース間電
圧の和で制限され、端子2に負の静電気あるいはサージ
電圧が加わった場合は端子1−2間の電圧はダイオード
8の順方向電圧で制限されるので正および負の静電気あ
るいはサージ電圧に対し電圧制限効果を有する。
FIG. 3 is an equivalent circuit of a protection circuit according to an embodiment of the present invention. When positive static electricity or surge voltage is applied to terminal 1, the voltage between terminals 1 and 2 is limited by the sum of the Zener voltage of Zener diode 6 and the voltage between the base of transistor 7, and a negative voltage is applied to terminal 2. When static electricity or surge voltage is applied, the voltage between terminals 1 and 2 is limited by the forward voltage of diode 8, which has a voltage limiting effect on positive and negative static electricity or surge voltage.

また第2図で保護ダイオード5をツェナーダイオードで
構成した場合に比べ、第3図ではツェナーダイオード6
の電流値は、トランジスタ70ベース電流のみを供給す
るので、トランジスタ7の1/hFIif倍に減少する
ため、動作抵抗はhrr+倍まで許容できツェナーダイ
オードの接合面積を小さくすることができる。これはツ
ェナーダイオード6の耐圧を下げるために高濃度接合と
しても、小さな接合面積で十分な動作可能なことを示し
ている。
Also, compared to the case where the protection diode 5 is configured with a Zener diode in Figure 2, the Zener diode 6 is configured in Figure 3.
Since only the base current of the transistor 70 is supplied, the current value is reduced to 1/hFIif times that of the transistor 7. Therefore, the operating resistance can be tolerated up to hrr+ times, and the junction area of the Zener diode can be reduced. This shows that even if a high concentration junction is used to lower the withstand voltage of the Zener diode 6, sufficient operation is possible with a small junction area.

第4図は第3図の保護回路を半導体基板上に構成した時
の断面構造図である。第3図の内部素子3は任意の素子
を想定しており、特定できないので第4図では省略しで
ある。第4図において半導体基板aに埋込み層すを拡散
し、エピタキシャル層を形成した後、絶縁拡散層Cによ
り単独に絶縁されたエピタキシャル層dを得る。エピタ
キシャル層dにベース拡散工程でベース領域eを、エミ
ッタ拡散工稈でツェナーダイオード用高濃度領域f、エ
ミッタ領域gを拡散形成する。第4図でエミッタ領域g
、ベース領域・、エピタキシャル層dおよびツェナーダ
イオード用高濃度領域fは第3図のトランジスタ7を構
成しそれぞれエミッタ・ベース、コレクタに相当する。
FIG. 4 is a cross-sectional structural diagram when the protection circuit of FIG. 3 is constructed on a semiconductor substrate. The internal element 3 in FIG. 3 is assumed to be an arbitrary element and cannot be specified, so it is omitted in FIG. 4. In FIG. 4, after a buried layer (a) is diffused into a semiconductor substrate (a) to form an epitaxial layer, an epitaxial layer (d) isolated by an insulating diffusion layer (C) is obtained. A base region e is formed in the epitaxial layer d by a base diffusion process, and a high concentration region f for a Zener diode and an emitter region g are formed by diffusion in an emitter diffusion process. In Figure 4, emitter area g
, a base region, an epitaxial layer d, and a high concentration region f for a Zener diode constitute the transistor 7 shown in FIG. 3, and correspond to the emitter, base, and collector, respectively.

またツェナーダイオード用高濃度領域fおよびベース領
域・でツェナーダイオード6を構成し、半導体基板aお
よび分離拡散領域Cとエピタキシャル層dおよびツェナ
ーダイオード用高濃度領域fでダイオード8を構成して
いる。これらは集積回路の通常のトランジスタの製造工
程と同じでよい。第4図の様に第3図の保護回路を1つ
の島に構成し、かつトランジスタ7のコレクタとツェナ
ーダイオード8のカソードとまたトランジスタ70ベー
スとツェナーダイオード8のコレクタを共通とすること
により、ペレット占有面積を小さくでき寄生容量を減ら
すことができる。
A Zener diode 6 is constituted by the Zener diode high concentration region f and the base region, and a diode 8 is constituted by the semiconductor substrate a, the isolation diffusion region C, the epitaxial layer d, and the Zener diode high concentration region f. These steps may be the same as those for manufacturing normal transistors of integrated circuits. As shown in FIG. 4, by configuring the protection circuit of FIG. 3 into one island, and by making the collector of the transistor 7, the cathode of the Zener diode 8, and the base of the transistor 70 and the collector of the Zener diode 8 common, the pellet The occupied area can be reduced and parasitic capacitance can be reduced.

以上の説明では集積回路のグランド端子と他の端子に加
わるサージ電圧あるいは静電気に対する破壊についての
み述べたがグランド端子以外の任意の端子闇についても
、それぞれの端子に本発明を適用すれは、グランド端子
に対して、正負両方向の電圧制限効果をもっているため
、任意の2端子間の電圧制限ができ、任意の2端子間の
保護として使用できる。
In the above explanation, only damage caused by surge voltage or static electricity applied to the ground terminal and other terminals of an integrated circuit has been described, but if the present invention is applied to any terminal other than the ground terminal, the ground terminal However, since it has a voltage limiting effect in both positive and negative directions, it is possible to limit the voltage between any two terminals, and it can be used as protection between any two terminals.

また第3図の保護回路にさらに保護抵抗を追加しても本
発明の効果かあることは明らかである。
Furthermore, it is clear that the effect of the present invention can be obtained even if a protective resistor is further added to the protective circuit shown in FIG.

以上説明した様に、本発明によれば、製造方法を変更す
ることなく、集積回路のグランド端子と他の端子に対し
て正負両方向電圧制限ができ、かつ寄生容量の少い保護
回路を実現できる。
As explained above, according to the present invention, it is possible to limit voltages in both the positive and negative directions for the ground terminal and other terminals of an integrated circuit without changing the manufacturing method, and to realize a protection circuit with low parasitic capacitance. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はそれぞれ従来の保護回路の例を示す回
路図、第3図は本発明の一実施例による保護回路の等価
回路図、第4図は本発明の一実施例による保諸回路の構
造例を示す断面構造図である。 1・・・・・・集積回路の任意の端子、2・・・・・・
グランド端子、3・・・・・・保護すべき内部素子、4
・・・・・・原論抵抗、5・・・・・・保護ダイオード
、6・・・・・・ツェナーダイオード、7・・・・・・
トランジスタ、8・・・・・・ダイオード、a・・・・
・・半導体基板、b・・・・・・埋込み層、C・・・・
・・絶縁類L d・・・・・・エピタキシャル層、e・
・・・・・ヘース領域、f・・・・・・エミッタ領域、
g・・・・・・ツェナーダイオード用高濃度領域。
1 and 2 are circuit diagrams showing examples of conventional protection circuits, FIG. 3 is an equivalent circuit diagram of a protection circuit according to an embodiment of the present invention, and FIG. 4 is a circuit diagram showing an example of a protection circuit according to an embodiment of the present invention. FIG. 3 is a cross-sectional structural diagram showing an example of the structure of various circuits. 1... Any terminal of the integrated circuit, 2...
Ground terminal, 3...Internal element to be protected, 4
...Principle resistance, 5...Protection diode, 6...Zener diode, 7...
Transistor, 8...Diode, a...
...Semiconductor substrate, b...Buried layer, C...
・Insulation L d・・・Epitaxial layer, e・
... Heath region, f ... Emitter region,
g...High concentration area for Zener diode.

Claims (1)

【特許請求の範囲】 1)、保護すべき端子間の一方にトランジスタのコレク
タおよびツェナーダイオードのカソード。 および″ダイオードのカソードを接続し、上記ト記トラ
ンジスタの工之ツタおよびダイオードのアノードを接続
することを特徴とする半導体集積回路。 2)、前記保護回路は単独に絶縁したエピタキシャル層
の一つの島領域に形成された前記トランジスタと、前記
トランジスタのコレクタコンタクト領域とペース層とで
形成したツェーダイオードと、前記エピタキシャル層の
島領域と少くとも絶縁分離領域との接合で構成されるダ
イオードとで構成したことを特徴とする特許請求の範囲
第1項記載の半導体集積回路。
[Claims] 1) The collector of the transistor and the cathode of the Zener diode on one side between the terminals to be protected. and ``a semiconductor integrated circuit, characterized in that the cathode of the diode is connected, and the ivy of the transistor described above and the anode of the diode are connected. 2) The protection circuit is an island of an epitaxial layer independently insulated a Tze diode formed by a collector contact region of the transistor and a space layer; and a diode formed by a junction between an island region of the epitaxial layer and at least an insulating isolation region. A semiconductor integrated circuit according to claim 1, characterized in that:
JP17803681A 1981-11-06 1981-11-06 Semiconductor integrated circuit Pending JPS5879749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17803681A JPS5879749A (en) 1981-11-06 1981-11-06 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17803681A JPS5879749A (en) 1981-11-06 1981-11-06 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5879749A true JPS5879749A (en) 1983-05-13

Family

ID=16041458

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17803681A Pending JPS5879749A (en) 1981-11-06 1981-11-06 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5879749A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097671A (en) * 1983-11-01 1985-05-31 Matsushita Electronics Corp Composite semiconductor device
JPS6359348U (en) * 1986-10-07 1988-04-20
JPH01320746A (en) * 1988-06-22 1989-12-26 Nec Corp Fluorescent display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4881490A (en) * 1972-01-27 1973-10-31
JPS5017974A (en) * 1973-06-18 1975-02-25
JPS5358777A (en) * 1976-11-06 1978-05-26 Mitsubishi Electric Corp Semiconductor device
JPS55115066A (en) * 1979-02-23 1980-09-04 Savin Business Machines Corp Developing method and copier
JPS5690553A (en) * 1979-12-21 1981-07-22 Nec Corp Preventive circuit for electrostatic breakdown

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4881490A (en) * 1972-01-27 1973-10-31
JPS5017974A (en) * 1973-06-18 1975-02-25
JPS5358777A (en) * 1976-11-06 1978-05-26 Mitsubishi Electric Corp Semiconductor device
JPS55115066A (en) * 1979-02-23 1980-09-04 Savin Business Machines Corp Developing method and copier
JPS5690553A (en) * 1979-12-21 1981-07-22 Nec Corp Preventive circuit for electrostatic breakdown

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6097671A (en) * 1983-11-01 1985-05-31 Matsushita Electronics Corp Composite semiconductor device
JPS6359348U (en) * 1986-10-07 1988-04-20
JPH01320746A (en) * 1988-06-22 1989-12-26 Nec Corp Fluorescent display device

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