JPS5916364A - Signal input circuit of mis type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the withstand strength against the input signal including an abnormal high voltage such as surge by a method wherein an input signal attenuation circuit which attenuates the input signal less than the allowable value is formed on a substrate of a MIS type semiconductor IC via an insulation layer. CONSTITUTION:Input circuit elements are all arranged in insulation from the substrate 112 by a field oxide film 107 which is an insulation layer. The abnormal signal such as surge voltage included in the input signal inputted to a bonding pad 101 is attenuated by a resistor composed of a poly Si layer 120 and by a CR circuit of parasitic capacity formed between this resistor and the substrate, and the input signal exceeding the power source voltage has either one of diodes 122 and 125 reversely biased forward biased, resulting in the restriction of the voltage of the input signal less than the power source voltage, thereby the voltage of the gate 104 of the MIS transistor is kept always less than the power source voltage. Therefore, the strength to the abnormal high voltage such as surge is further improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal input circuit for an MIS type semiconductor integrated circuit, and particularly to a signal input circuit suitable for use when an input signal is at a high level.

MIS type semiconductor integrated circuit (MIS type semiconductor integrated circuit formed from type semiconductor elements)
(Hereinafter, simply referred to as MIS-IC), the a! In order to increase the voltage of the MIS type semiconductor element from the voltage to the voltage, for example, a signal input circuit having the configuration shown in FIG. 1 has been conventionally provided.

In Figure 1, 1 is a bonding pad, 2 is a diffused resistor, 3.4 is a diode connected to the power supply Vao and Vss in reverse bias, and 5.6 and 7 are MISs, respectively.
gate, north, and drain of a type transistor. As an example of what is formed in the Shingetsu input circuit eMIs-IC shown in FIG. 1, a vertically structured MIS-IC shown in the cross-sectional view of FIG. 2 is known.

In FIG. 2, 101 is a pounding pad, 102
is a diffused resistance made of a diffusion layer, and this diffusion layer is made of a second conductivity type (P type in the illustrated example) which is an opposite conductivity type to the substrate 112 of the first conductivity type (N type in the illustrated example). It is formed. 103 is a diffusion layer of the first conductivity type formed in the well 109 formed of a second conductivity type semiconductor, and 104, 105, and 106 are the gate, source, and drain of the MIS type transistor, respectively.

107 is a field oxide film, 108 is a PSG (ringer 2)
110 is a diffusion layer for applying a bias potential to the well 109, and 111 is a gate oxide film. The bonding pad 101 is connected to one end of the diffused resistor 102 by a line 113,
The other end of 02 is connected to the diffusion layer 103 and the gate 104 by a diagonal line 114.

The diffused resistor 102 corresponds to the diffused resistor 2 in FIG. 1, and the diode formed by the well 109 and the diffusion layer 103 corresponds to the diode 4 in FIG.

In the above configuration, by reverse biasing each diode, if a high voltage such as a surge voltage that exceeds the reverse bias voltage is superimposed on the input signal, one of the diodes will be reverse biased depending on the polarity. conducts and operates to limit its peak value, thereby causing MIS
This protects the gate oxide film 111 of the type transistor from dielectric breakdown caused by high voltage such as surge voltage.

However, since the insulation between the substrate 112 and the diffused resistor 102 or each of the reverse bias diodes is based on the reverse bias of the PN junction, if an abnormally high voltage that greatly exceeds this reverse bias voltage is input, If a forward bias current that exceeds the allowable current flows through the PN junction and the N junction is destroyed, or if the voltage is abnormally high and exceeds the reverse breakdown voltage, the PN junction will be in a destructive conduction state. It had the disadvantage of becoming

Also, 0MO8 (Complementary Met
In MIS-ICs with a Qxide Semiconductor) structure, a high-level DC input signal that exceeds the power supply voltage induces a launch amplifier, so the input signal voltage must be lower than the power supply voltage. had.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal input circuit for an MIS type semiconductor integrated circuit that has improved resistance to input signals containing abnormally high voltages such as surges, and is also capable of receiving input signals that are lower than the power supply voltage. It is in.

The present invention provides an input signal attenuation circuit that attenuates an input signal below a permissible value by forming an input signal attenuation circuit on the substrate of a MIS type semiconductor IC via an insulating layer, thereby achieving resistance to input signals including abnormally high voltages such as surges. In addition to improving the power supply voltage, it is also possible to capture a Δ force signal higher than the power supply voltage. Furthermore, by providing a voltage dividing circuit at the input stage of the input signal attenuation circuit, it is possible to receive an input signal that can be connected to an even larger power supply voltage.

Hereinafter, the present invention will be explained based on illustrated embodiments.

Embodiments 1 to 5 of the present invention are shown in FIGS. 3 to 11. In these drawings, the parts denoted by the same reference numerals mutually or with those of the conventional example shown in FIG. 2 have the same configuration and function.

In the first embodiment shown in FIG. 3, 12° is a polysilicon layer having a first conductivity type (e.g.
is a polysilicon layer having a second conductivity type (for example, P type), and 122 is a PN junction formed between the polysilicon layers 120 and 121.

123 is a polysilicon layer having a second conductivity type; 124
is a polysilicon layer having a first conductivity type, and 125 is a PN junction formed between the polysilicon layers 123 and 124. The polysilicon layer 120 acts as a resistor, and the input signal applied to the bonding pad 101 is applied to the MISI transistor 104 via the polysilicon layer 120. 1? N
Junctions 122 and 125 are entirely made of polysilicon as diodes, and have power supply voltages V on and V gs , respectively.
is reverse biased. This circuit consisting of reverse biased PN junctions (hereinafter referred to as diodes) 122 and 125 forms a so-called voltage clamp circuit. All of the input circuit elements formed as described above are insulated from the substrate 112 by the field oxide film 107, which is an insulating layer.

Because of this configuration, the bonding pad 1
Abnormal signals such as surge voltage included in the input signal input to 01 are attenuated by a resistor made of a polysilicon layer 120 and a CR circuit formed by a recessed capacitor formed between this resistor and the substrate. When an input signal exceeds the power supply voltage, either of the reverse biased diodes 122 and 125 is biased to limit the voltage of the human signal to below the power supply voltage, so the voltage at the gate 104 of the MIS transistor is It will always be kept below the power supply voltage.

Therefore, according to the first embodiment, since the circuit elements forming the signal input circuit are strongly insulated from the substrate by the insulating layer made of the field oxide film, the resistance to abnormal high voltages such as surges is significantly improved. It has the effect of improving Abnormal high voltages such as short circuits and surges are effectively attenuated by the CR circuit and the voltage clamp circuit, so that dielectric breakdown of the transistor gate can be sufficiently protected. effective. Furthermore, since no PN junction is formed between the signal input circuit and the substrate, there is an effect that even in the case of an 0MO8 structure, there is no possibility of latch-up or the like occurring.

Next, in the second embodiment shown in FIG. 4, 130 is a voltage dividing resistor formed from a polysilicon layer;
4 is a polysilicon layer having a first conductivity type; 132 and 1;
35 has the second conductivity type, l-' IJ silicon!
, 133 and 136 are PNs formed in the polysilicon layer.
It is a junction diode.

One end of the voltage dividing resistor 130 is connected to the bonding pad 101 by a line 113, the other end is connected to the ground (GNI) 1, and an intermediate terminal provided between these is connected to the gate 104 by a line 114. has been done. Also,
The line 114 is also connected to the polysilicon layers 132 and 134, and the polysilicon layers 131 and 135 are connected to the power supply voltage Vll!, respectively. l, VDD is applied.

The circuit of the second embodiment constructed in this manner is as shown in FIG.

Therefore, according to the second embodiment, as in the first embodiment, the circuit elements of the signal input circuit are strongly insulated from the substrate by the insulating layer, and the attenuation circuit consisting of the CRT circuit and the clamp circuit is installed. Because of this, it is possible to obtain the same effects as in the first embodiment.

Furthermore, according to the second embodiment, ~ll5) The gate voltage Va applied to the gate 104 of the transistor is the voltage V! of the input signal! Since the voltage is divided by the voltage dividing resistor 130, by setting an appropriate voltage dividing ratio, it is possible to take in input signals (for example, analog signals) of high voltage DC components that greatly exceed the power supply voltage. Furthermore, it is possible to prevent damage to the gate 104 or latch-up of the CMO8 element.

The third embodiment shown in FIG. 6 is similar to the equivalent circuit shown in FIG.
A voltage divider circuit consisting of 151 to 15
The present invention is characterized in that the voltage dividing circuit 150 is made up of 5 parts. Note that the MIS (MIS) transistor part in the figure is omitted, and a clamp circuit made of a diode may be provided as necessary.

In FIG. 6, 141 to 146 are conductor wiring portions of a low resistance polysilicon layer formed by diffusing high concentration impurities, and 151 to 155 are unit resistors made of a low concentration impurity polysilicon layer.

Therefore, according to the third embodiment, in addition to the effects of the second embodiment, by improving the consistency of the unit resistors 151 to 155, the input signal can be accurately divided into voltages (according to the present embodiment). 115), it has the advantage that it can also be applied as a high-precision analog symbol input circuit.

The fourth embodiment shown in FIG. 8 is similar to the equivalent circuit shown in FIG.
A voltage dividing circuit 150 consisting of diodes 181 to 18
This is replaced by a voltage dividing circuit 180 consisting of 5.

In FIG. 8, 161-165i#i are polysilicon layers having a first conductivity type, 171-175 are polysilicon layers having a second conductivity type, and 181-185 are polysilicon layers 161-165. , polynolycon layers 171 to 175 formed adjacent to these, and a diode (PN junction). These diodes 181 to 185 are connected in series, and diode 18
The anode of the diode 185 is connected to the bonding band 101, and the cand of the diode 185 is connected to the ground (GND). In addition, the diode 184 and the diode 185
The connection point of MIS, not shown by line 114, is
) connected to the gate of the transistor.

According to the fourth embodiment configured as above,
In addition to the effects of the third embodiment, each diode 181 to
If the voltage between the terminals of 185 is set to 4, which is sufficiently small, and the matching is made sufficiently high, each diode 181 to 185 will operate as a high resistance element, so an extremely high input impedance can be obtained. .

In the fifth embodiment shown in FIG. 10, 201 to 20
6 is a polysilicon layer having a first conductivity type, 211 to 2;
15 is a polysilicon layer having a second conductivity type. These polysilicon layers 201-206, 211-215
are formed alternately and adjacently on the field oxide film 107, and each junction includes diodes (PN junctions) 221 to 230. The equivalent circuit of the fifth embodiment configured as described above is composed of diodes 221 to 2 forming the voltage dividing circuit 200, as shown in FIG.
30 are alternately connected in reverse, and the anode of the diode 221 is connected to the bonding band 101, and the anode of the diode 230 is connected to the ground (GND). Further, the connection point between the diodes 228 and 229 is connected by a line 114 to the gate of an MIS transistor (not shown).

According to the fifth embodiment configured as above, the fourth
In addition to the effects of the embodiment, since a set of reversely connected diodes is used as one component of the voltage divider, the same voltage divider characteristics can be obtained regardless of the polarity of the input signal with respect to GND, and It is possible to apply it to the input signal.

Although polysilicon is used as an example of the constituent material of the resistor or diode in the first to fifth embodiments, it is clear that similar effects can be obtained with other semiconductor materials. be.

As described above, the present invention has the effect of improving resistance to input signals including abnormally high voltages such as surges, and being able to receive input signals higher than the power supply voltage.

[Brief explanation of drawings]

FIG. 1 is an equivalent circuit of a conventional signal input circuit, FIG. 2 is a vertical cross-sectional structural diagram of a main part of a MIS type semiconductor IC to which the conventional example shown in FIG. 1 is applied, and FIG. 3 is a first embodiment of the present invention. FIG. 4 is a vertical cross-sectional structural diagram of the main part of the second embodiment of the present invention, FIG. 5 is an equivalent circuit of the second embodiment shown in FIG. 4, and FIG.
The figure is a vertical cross-sectional structural diagram of a main part of a third embodiment of the present invention, FIG. 7 is an equivalent circuit of the third embodiment shown in FIG. 6, and FIG. 8 is a longitudinal cross-sectional structure of a main part of a fourth embodiment of the present invention. Figure 9 is the 4th diagram shown in Figure 8.
Equivalent circuit of the embodiment, FIG. 10 is a longitudinal sectional structural view of the main part of the fifth embodiment of the present invention, and FIG. 11 is an equivalent circuit of the second embodiment shown in FIG. 4. 120...Resistance, 122, 125, 133, 136.
・・PN junction, terminal auto 4, 130,150° / Figure 2 // 2 Figure 3 □ 22 Figure 1 1 gi 06 // 2 Figure 5 fND Wss Figure 7 Glθ Figure 3 Condolences (2)

Claims (1)

[Claims] 1. A signal of an MIS type semiconductor IC, characterized in that it is configured with an input signal attenuation circuit consisting of a semiconductor circuit element formed on a substrate of the MIS type semiconductor IC via an insulating layer. input circuit. 2. The MIS according to claim 1, wherein the input signal attenuation circuit is a circuit including a semiconductor resistor and a parasitic capacitor formed between the semiconductor resistor and the substrate. Signal input circuit for type semiconductor IC. 3. In the invention set forth in claim 1, the input signal attenuation circuit includes a circuit including a semiconductor resistor, a parasitic chamber formed between the semiconductor resistor and the substrate, and an output terminal of the circuit. A signal input circuit for an MIS type semiconductor IC, characterized in that it is formed by comprising a PN junction element connected in reverse bias to at least one pole of a bipolar power source. 4. The signal input circuit for an MIS type semiconductor IC according to the invention as set forth in claim 1, wherein the input signal attenuation circuit includes a voltage dividing circuit at an input stage. 5. In the invention as set forth in claim 4, the voltage dividing circuit is a circuit whose output terminal is an intermediate terminal of a semiconductor resistor whose one end is connected to a signal input terminal and the other end is connected to ground. The signal input circuit of the MIS type semiconductor IC shown in FIG. 6. The invention as set forth in claim 5, wherein the semiconductor resistor is formed by connecting a plurality of semiconductor resistors in series.
C signal input circuit. 7. In the invention set forth in claim 4, the voltage dividing circuit includes an intermediate connection point between a plurality of PN junction elements connected in series in the same direction, one end of which is connected to an input end and the other end of which is connected to ground. A signal input circuit for a MIS type semiconductor IC, characterized in that the circuit serves as an output terminal. 8. In the invention as set forth in claim 4, the voltage dividing circuit includes a plurality of pairs of PN junction elements connected in series, each of which is forward biased and reverse biased in series with respect to the input signal. A signal input circuit for an MIS type semiconductor IC, characterized in that the circuit has one end of a connected PN junction element connected to an input end, the other end connected to ground, and an intermediate connection point used as an output end.