WO2007129384A1 - Lc noise filter - Google Patents

Lc noise filter Download PDF

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Publication number
WO2007129384A1
WO2007129384A1 PCT/JP2006/309087 JP2006309087W WO2007129384A1 WO 2007129384 A1 WO2007129384 A1 WO 2007129384A1 JP 2006309087 W JP2006309087 W JP 2006309087W WO 2007129384 A1 WO2007129384 A1 WO 2007129384A1
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WO
WIPO (PCT)
Prior art keywords
noise filter
semiconductor substrate
inductor conductor
inductor
spiral electrode
Prior art date
Application number
PCT/JP2006/309087
Other languages
French (fr)
Japanese (ja)
Inventor
Takeshi Ikeda
Hiroshi Miyagi
Kouichi Ikeda
Original Assignee
Niigata Seimitsu Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Niigata Seimitsu Co., Ltd. filed Critical Niigata Seimitsu Co., Ltd.
Priority to PCT/JP2006/309087 priority Critical patent/WO2007129384A1/en
Publication of WO2007129384A1 publication Critical patent/WO2007129384A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227Inductive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/10Inductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F17/0006Printed inductances
    • H01F17/0013Printed inductances with stacked layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type 
    • H01F2017/0093Common mode choke coil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/40Structural association with built-in electric component, e.g. fuse
    • H01F27/402Association of measuring or protective means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021Constructional details
    • H03H2001/0064Constructional details comprising semiconductor material

Definitions

  • the present invention relates to an LC noise filter that removes noise in an electronic device.
  • Patent Document 1 Japanese Patent No. 3029929 (Page 2-3, Figure 1-6)
  • the noise filter disclosed in Patent Document 1 is formed on an insulating substrate (semiconductor substrate) using a semiconductor manufacturing technique, so an instantaneously excessive voltage such as static electricity with a low withstand voltage is applied.
  • an instantaneously excessive voltage such as static electricity with a low withstand voltage is applied.
  • the insulating layer between the double spiral electrode may be destroyed.
  • it is conceivable to insert an anti-static element between the external input terminal and the noise filter it is conceivable to insert an anti-static element between the external input terminal and the noise filter.
  • the increase in the number of parts and the associated assembly man-hours This will lead to an increase in the process complexity and cost.
  • the present invention was created in view of these points, and an object of the present invention is to provide an LC noise filter capable of preventing breakdown due to static electricity or the like by increasing the withstand voltage. Means to solve
  • an LC noise filter of the present invention includes a first inductor conductor formed on a semiconductor substrate, and at least a part of the first inductor conductor formed on the semiconductor substrate. And a second inductor conductor disposed at a position farther from the semiconductor substrate than the first inductor conductor. And an input protection circuit made of a semiconductor element connected to the ends of the first and second inductor conductors and formed on the semiconductor substrate.
  • the second inductor conductor described above is used for a signal line through which signals are input and output, and that one end of the first inductor conductor is grounded.
  • the thickness of the second inductor conductor which is the upper layer, is generally thicker depending on the manufacturing process.
  • the above-described second inductor conductor is provided with an input protection circuit at each of both ends, and the first inductor conductor is provided with an input protection circuit at an end that is grounded. .
  • a distributed constant type LC noise filter can be realized, and a noise component included in a signal input to the second inductor conductor can be removed.
  • the above-described first inductor conductor is provided with an input protection circuit at the other end as well as the end that is grounded. As a result, the breakdown voltage of the LC noise filter can be further increased.
  • the input protection circuit described above is preferably a diode configured by a PN junction formed on a semiconductor substrate.
  • the end portion of the first inductor conductor described above that is grounded is an inner peripheral end portion.
  • the first inductor conductor and the first inductor conductor are formed so as to overlap therewith.
  • the diameter of the outermost peripheral portion of the second inductor conductor can be increased, and a large inductance can be secured.
  • pads are connected to both ends of the second inductor conductor and one end of the first inductor conductor described above, and knocking is performed by wafer level CSP (Chip Scale Package). It is desirable. This makes it possible to reduce the size of the chip component when the LC noise filter is formed as a chip component.
  • the first and second inductor conductors and the input protection circuit are formed on a common semiconductor substrate. As a result, it is possible to realize a small chip component incorporating a large number of LC noise filters.
  • the second inductor conductor described above is used for a signal line through which signals are input and output, and the first inductor conductor is grounded at one end, and a plurality of first inductor conductors corresponding to a plurality of sets. It is desirable that one end of each is connected to each other. As a result, the number of terminals for external connection can be reduced in chip components incorporating a plurality of LC noise filters, and the distance between these terminals can be secured to the maximum. In addition, when it is necessary to ensure a certain distance between the terminals for external connection, it is possible to reduce the size of the chip component.
  • FIG. 1 is a plan view of an LC noise filter according to an embodiment.
  • FIG. 2 is a cross-sectional view of a circumferential portion of a spiral electrode.
  • FIG. 3 is a sectional view of the pad.
  • FIG. 4 is a cross-sectional view of the pad.
  • FIG. 5 is an equivalent circuit diagram of the LC noise filter.
  • FIG. 6 is an explanatory diagram of an outline of a method for manufacturing an LC noise filter.
  • FIG. 7 is an explanatory diagram outlining the manufacturing method of an LC noise filter.
  • FIG. 8 is a cross-sectional view of the LC noise filter shown in FIG.
  • FIG. 9 is a cross-sectional view of a wafer level CSP corresponding to an LC noise filter.
  • FIG. 10 is a diagram showing a wafer level CSP process.
  • FIG. 11 is a diagram showing a wafer level CSP process.
  • FIG. 12 is a diagram showing a wafer level CSP process.
  • FIG. 13 is a diagram showing a wafer level CSP process.
  • FIG. 14 is a diagram showing a specific example of dicing.
  • FIG. 1 is a plan view of an LC noise filter according to an embodiment.
  • the LC noise filter 100 of this embodiment includes spiral electrodes 120 and 130 as double inductor conductors formed on the surface of a semiconductor substrate 110 which is a P-type silicon substrate, and a semiconductor substrate 110.
  • Pads 122 and 124 as input / output terminals formed near both ends of one spiral electrode 120 on the far side (upper layer) and the inner peripheral end of the other spiral electrode 130 on the side closer to the semiconductor substrate 110 (lower layer)
  • a pad 132 as a grounding terminal formed in the vicinity and an N + region 112, 114, 116 formed at the position of the semiconductor substrate 110 facing these three pads 122, 124, 132 are provided. .
  • Each of the double spiral electrodes 120, 130 has a predetermined number of turns and has substantially the same shape.
  • these spiral electrodes 120 and 130 are formed using a two-layer metal wiring using gold or aluminum.
  • the force due to the manufacturing process The upper spiral electrode 120 is thicker than the lower spiral electrode 130.
  • the upper spiral electrode 120 with a large film thickness is used for a signal line
  • the lower spiral electrode 130 with a small film thickness is used for grounding (for the electrical connection state). Will be described later).
  • FIG. 2 is a cross-sectional view of the surrounding portions of the spiral electrodes 120 and 130.
  • a spiral electrode 130 is formed on the surface of the semiconductor substrate 110 with an insulating layer 200 interposed therebetween, and a spiral electrode 120 is formed thereon with an insulating layer 202 interposed therebetween.
  • insulating layers 200 and 202 for example, SiO 2 is used. In the example shown in FIGS. 1 and 2, spiral power is used.
  • a force that makes the shapes of the poles 120 and 130 substantially the same may be shifted from each other with at least a part of the force overlapping.
  • the lengths in the circumferential direction may be different (specifically, the length near the semiconductor substrate 110 and the length on the outer peripheral end side of the spiral electrode 130 may be shortened). That is, in the LC noise filter 100 described above, the spiral electrode 130 as the first inductor conductor formed on the semiconductor substrate 110 and the semiconductor substrate 110 are formed, and at least a part of the spiral electrode 130 and the insulating layer 20 are formed. 2 and a spiral electrode 120 as a second inductor conductor that is disposed at a position farther from the semiconductor substrate 110 than the overlapped partial force spiral electrode 130. I'll do it.
  • the number of turns of the spiral electrodes 120 and 130 may be 1 or less.
  • Pads 122 and 124 formed integrally with the spiral electrode 120 in the vicinity of both ends of one spiral electrode 120 are for inputting and outputting signals to be subjected to noise removal.
  • the pad 122 provided on the inner peripheral side is used as the input terminal 122A
  • the pad 124 provided on the outer peripheral side is used as the output terminal 124A.
  • diodes 112D and 114D formed by a PN junction between the semiconductor substrate 110 and N + regions 112 and 114 formed in a part of the semiconductor substrate 110 are arranged immediately below these pads 122 and 124.
  • FIG. 3 is a cross-sectional view of pad 122.
  • N + region 112 is formed in the vicinity of the surface of the P-type semiconductor substrate 110, and a diode 112D is configured by a PN junction between the semiconductor substrate 110 and the N + region 112.
  • the pad 122 is directly connected to the N + region 112 through a contact hole.
  • the pad 132 formed near the inner peripheral end of the other spiral electrode 130 is used as the ground terminal 132A.
  • an end of the spiral electrode 130 connected through the contact hole is arranged, and further below it is a space between the semiconductor substrate 110 and the N + region 116 formed in a part thereof.
  • a diode 116D formed by a PN junction is disposed.
  • FIG. 4 is a cross-sectional view of the pad 132.
  • An N + region 116 is formed in the vicinity of the surface of the P-type semiconductor substrate 110, and a diode 116D is constituted by these PN junctions.
  • An end portion of the spiral electrode 130 is directly formed on the surface of the N + region 116, and the node 132 is connected to the end portion of the spiral electrode 130 through a contact hole.
  • FIG. 5 is an equivalent circuit diagram of the LC noise filter 100. Since the upper spiral electrode 120 and the lower spiral electrode 130 are arranged so as to overlap each other, a capacitor 140 is formed between them. Accordingly, the spiral electrodes 120 and 130 and the Canon 140 constitute a distributed constant type LC noise filter 100. Also, diodes 112D, 114D, and 116D are connected to the input terminal 122A, the output terminal 124A, and the ground terminal 132A, respectively. These diodes 112D, 114D, and 116D are for input protection, and prevent the insulating layer 202 between the spiral electrodes 120 and 130 from being destroyed when an excessive voltage due to static electricity or the like is applied to the corresponding terminals. .
  • the withstand voltage can be increased by connecting the diode also to the vicinity of the outer peripheral end.
  • an N + region may be formed near the surface of the semiconductor substrate 110 corresponding to the outer peripheral edge of the spiral electrode 130.
  • FIG. 6 and FIG. 7 are explanatory views of the outline of the manufacturing method of the LC noise filter 100. Although one LC noise filter 100 is shown in FIG. 6 and the like, in practice, a large number of LC noise filters 100 are formed simultaneously using one silicon wafer, and one or more LC noise filters 100 are formed. Predetermined packaging is performed in units of pieces.
  • an insulating layer 200 is formed on the surface of a semiconductor substrate (silicon wafer) 110, and regions corresponding to the N + regions 112, 114, and 116 are removed using a photolithography method.
  • N + regions 112, 114, and 116 are formed by thermally diffusing arsenic or the like on the semiconductor substrate 100 through these regions (FIG. 6).
  • a predetermined pattern as a lower spiral electrode 130 is formed by photolithography using a photoresist (FIG. 7). Further, after removing the photoresist, an insulating layer 202 is formed on the surface, and a region corresponding to the N + regions 112 and 114 and a region corresponding to the inner peripheral edge of the spiral electrode 130 are removed by photolithography. Next, the upper layer spiral electrode 120 and the pad 132 having the pads 122 and 124 at both ends are formed. In this way, the LC noise filter 100 shown in FIG. 1 is completed.
  • the above-described LC noise filter 100 of the present embodiment can be manufactured as a chip component by performing a predetermined packaging that can be formed as one component included in an LSI. Next, a specific example will be described assuming that a wafer level CSP (Chip Scale Package) is performed on the LC noise filter 100 described above.
  • a wafer level CSP Chip Scale Package
  • FIG. 8 is a cross-sectional view of the LC noise filter 100 shown in FIG. 1, and shows a state before performing wafer level CSP.
  • FIG. 9 is a cross-sectional view of a wafer level CSP corresponding to the LC noise filter 100. 8 and 9 show structures that focus on the parts related to the solder balls that serve as the external connection terminals of the wafer level CSP, and other structures and positional relationships are simplified or It is omitted.
  • pads 132 are connected to solder balls 340 via UBM (underbump metal) 310, Cu rewiring 320, and Cu post 330. The same applies to the other pads.
  • FIGS. 10 to 13 are diagrams showing a wafer level CSP process.
  • a polyimide pattern 302 is formed on the surface of the passivation 300 (FIG. 10A) on the surface of the LC noise finer (FIG. 10B).
  • the passivation 300 is formed on the surface when the LC noise filter 100 is formed.
  • a UBM 310 is formed on the surface of the polyimide pattern 302 so as to be connected to the pad 132 or the like (FIG. 10C).
  • UBM310 consists of Ti layer and Cu layer, for example.
  • a resist pattern 312 is formed on the surface, and a Cu rewiring 320 is formed (FIG. 11A).
  • FIG. 14 is a diagram showing a specific example of dicing, and shows a case where a chip part including two LC noise filters 100 is manufactured.
  • the chip component shown in FIG. 14 has a size of lmm ⁇ 1.4 mm, and includes two LC noise filters 100 therein.
  • Each of the two LC noise filters 100 has an input terminal 122A force corresponding to solder balls 340 provided in the vicinity of different corners.
  • each of the two LC noise filters 100 corresponds to a solder ball 340 provided in the vicinity of different corners of the input terminal 124A force provided on each of the two LC noise filters 100.
  • solder balls 340 corresponding to the input terminal 122A and the output terminal 124A are arranged at the four corners of the chip component having a rectangular shape, and one solder ball 340 corresponding to the ground terminal 132A is arranged at the center.
  • the grounded central solder ball 340 and the other four solder balls 340 can be largely separated from each other, and the chip component can be miniaturized while ensuring a distance therebetween.
  • the horizontally long rectangular shape is divided into two in the horizontal direction, and the LC noise filter 100 is associated with each divided region.
  • the horizontally long rectangular shape is divided into two in the vertical direction, and The LC noise filter 100 may be associated with the divided areas.
  • the LC noise filter 100 is provided with the diodes 112D, 114D, and 116D as input protection circuits at the ends of the spiral electrodes 120 and 130, thereby providing an anti-resistance.
  • breakdown due to static electricity or the like insulation breakdown of the insulating layer 202 disposed between the spiral electrodes 120 and 130
  • the upper spiral electrode 120 is generally thicker depending on the manufacturing process. Therefore, the resistance of the signal line can be lowered by using the spiral electrode 120 as the signal line.
  • the upper spiral electrode 120 is provided with diodes 112D and 114D as input protection circuits at both ends, and the lower spiral electrode 130 is a diode 116D as an input protection circuit at the grounded end. Is provided. As a result, a distributed constant type LC noise filter 100 can be realized, and a noise component included in a signal input to the upper spiral electrode 120 can be removed.
  • the lower spiral electrode 130 may be provided with a diode as an input protection circuit at the other end as well as at the end to be grounded. As a result, the breakdown voltage of the LC noise filter 100 can be further increased.
  • diodes 112D, 114D, and 116D formed by PN junctions formed on the semiconductor substrate 110 are used as the input protection circuit.
  • a current can flow to the semiconductor substrate 110 side, and insulation breakdown between the spiral electrodes 120 and 130 due to the excessive voltage can be prevented. I can do it.
  • the grounded end of the lower layer spiral electrode 130 is disposed on the inner peripheral side end. This eliminates the need to form a connection pad on the outer peripheral side of the spiral electrode 130, so that when the size of the semiconductor substrate 110 is constant, the spiral electrode 130 and the spiral formed on the spiral electrode 130 are overlapped.
  • the diameter of the outermost periphery of the electrode 120 can be increased, and a large inductance can be secured.
  • the overlapping area of the spiral electrodes 120 and 130 may be varied according to the frequency characteristics. As a result, only the characteristics can be changed without changing the area or terminal arrangement of the LC noise filter 100.
  • Pads are connected to both ends of the upper spiral electrode 120 and one end of the lower spiral electrode 130, respectively, and are connected by a wafer level CSP (Chip Scale Package). Packaging. As a result, when the LC noise filter 100 is formed as a chip component, the chip component can be reduced in size.
  • CSP Chip Scale Package
  • a plurality of sets of spiral electrodes 120 and 130 and diodes 112D, 114D, and 116D as input protection circuits are formed on a common semiconductor substrate 110.
  • a small chip component with a large number of built-in LC noise filters 100 can be realized.
  • one end of the lower layer spiral electrode 130 included in the plurality of sets is connected to each other, thereby reducing the number of terminals for external connection in a chip component incorporating a plurality of LC noise filters 100. Therefore, the maximum distance between these terminals can be secured. In other words, it is possible to reduce the size of the chip component when it is necessary to ensure a certain distance between the terminals for external connection.
  • the spiral electrode 130 may be connected to an external terminal in which the pad 132 is connected to the inner terminal.
  • solder paste may be printed instead of the force used to use the solder balls 340 in the wafer level CSP.
  • the LC noise filter 100 having three or more forces in which two LC noise filters 100 are included in one chip component may be included.
  • the breakdown voltage can be increased and the breakdown due to static electricity or the like can be prevented.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
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Abstract

Provided is an LC noise filter by which breakage due to static electricity or the like is prevented by increasing the withstand voltage. The LC noise filter is provided with a spiral electrode (130) formed on a semiconductor substrate (110); a spiral electrode (120), which is formed on the semiconductor substrate (110), at least partly overlaps the spiral electrode (130) by maintaining a prescribed distance from the spiral electrode, and has the overlapped portion arranged further from the semiconductor substrate (110) than the spiral electrode (130); and diodes (112D, 114D, 116D) which are connected to the end sections of the spiral electrodes (130, 120) and are formed as an input protection circuit composed of a semiconductor element formed on the semiconductor substrate (110).

Description

[0001] 本発明は、電子機器においてノイズを除去する LCノイズフィルタに関する。  The present invention relates to an LC noise filter that removes noise in an electronic device.
背景技術  Background art
[0002] 従来から、半導体基板上形成された二重のスパイラル電極を有する分布定数型の ノイズフィルタが知られている(例えば、特許文献 1参照。)。分布定数型構成を採用 することにより、比較的広い周波数範囲に含まれるノイズを除去することが可能となる 特許文献 1 :特許第 3029929号公報 (第 2— 3頁、図 1— 6)  Conventionally, a distributed constant type noise filter having double spiral electrodes formed on a semiconductor substrate is known (for example, see Patent Document 1). By adopting a distributed constant configuration, it is possible to remove noise included in a relatively wide frequency range. Patent Document 1: Japanese Patent No. 3029929 (Page 2-3, Figure 1-6)
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0003] ところで、特許文献 1に開示されたノイズフィルタは絶縁基板(半導体基板)上に半 導体製造技術を用いて形成されるため耐圧が低ぐ静電気等の瞬間的に過大な電 圧が加わると二重のスパイラル電極間の絶縁層が破壊されるおそれがあるという問題 があった。また、このような不具合を回避するために、外部入力端子とノイズフィルタと の間に静電気対策用の素子を揷入することも考えられるが、部品点数の増加や、こ れに伴う組み付け工数の増加につながって、工程の複雑化、コスト上昇を招くため好 ましくない。 [0003] By the way, the noise filter disclosed in Patent Document 1 is formed on an insulating substrate (semiconductor substrate) using a semiconductor manufacturing technique, so an instantaneously excessive voltage such as static electricity with a low withstand voltage is applied. There is a problem that the insulating layer between the double spiral electrode may be destroyed. In order to avoid such problems, it is conceivable to insert an anti-static element between the external input terminal and the noise filter. However, the increase in the number of parts and the associated assembly man-hours. This will lead to an increase in the process complexity and cost.
[0004] 本発明は、このような点に鑑みて創作されたものであり、その目的は、耐圧を高くし て静電気等による破壊を防止することができる LCノイズフィルタを提供することにある 課題を解決するための手段  [0004] The present invention was created in view of these points, and an object of the present invention is to provide an LC noise filter capable of preventing breakdown due to static electricity or the like by increasing the withstand voltage. Means to solve
[0005] 上述した課題を解決するために、本発明の LCノイズフィルタは、半導体基板上に 形成された第 1のインダクタ導体と、半導体基板上に形成され、少なくとも一部が第 1 のインダクタ導体と所定の距離を維持した状態で重複し、この重複した部分が第 1の インダクタ導体よりも半導体基板から離れた位置に配置された第 2のインダクタ導体と 、第 1および第 2のインダクタ導体の端部に接続され、半導体基板に形成された半導 体素子からなる入力保護回路とを備えている。インダクタ導体の端部に入力保護回 路を設けることにより、耐圧を高くして静電気等による破壊を防止することができる。 In order to solve the above-described problem, an LC noise filter of the present invention includes a first inductor conductor formed on a semiconductor substrate, and at least a part of the first inductor conductor formed on the semiconductor substrate. And a second inductor conductor disposed at a position farther from the semiconductor substrate than the first inductor conductor. And an input protection circuit made of a semiconductor element connected to the ends of the first and second inductor conductors and formed on the semiconductor substrate. By providing an input protection circuit at the end of the inductor conductor, the breakdown voltage can be increased and breakdown due to static electricity or the like can be prevented.
[0006] また、上述した第 2のインダクタ導体は信号が入出力される信号線路に用いられ、 第 1のインダクタ導体は一方端が接地されることが望ましい。 2層メタル構造を採用し て第 1および第 2のインダクタ導体を形成した場合には、製造工程にもよるが、一般に は上層となる第 2のインダクタ導体の方が膜厚が厚くなるため、第 2のインダクタ導体 を信号線路として用いることにより、信号線路の抵抗を下げることができる。  [0006] Further, it is desirable that the second inductor conductor described above is used for a signal line through which signals are input and output, and that one end of the first inductor conductor is grounded. When the first and second inductor conductors are formed using a two-layer metal structure, the thickness of the second inductor conductor, which is the upper layer, is generally thicker depending on the manufacturing process. By using the second inductor conductor as the signal line, the resistance of the signal line can be lowered.
[0007] また、上述した第 2のインダクタ導体は、両端のそれぞれに入力保護回路が設けら れ、第 1のインダクタ導体は、接地される端部に入力保護回路が設けられていること が望ましい。これにより、分布定数型の LCノイズフィルタを実現することができ、第 2 のインダクタ導体に入力される信号に含まれるノイズ成分を除去することが可能となる  [0007] In addition, it is preferable that the above-described second inductor conductor is provided with an input protection circuit at each of both ends, and the first inductor conductor is provided with an input protection circuit at an end that is grounded. . As a result, a distributed constant type LC noise filter can be realized, and a noise component included in a signal input to the second inductor conductor can be removed.
[0008] また、上述した第 1のインダクタ導体は、接地される端部とともに他の端部にも入力 保護回路が設けられていることが望ましい。これにより、 LCノイズフィルタの耐圧をさ らに上げることが可能となる。 [0008] Further, it is desirable that the above-described first inductor conductor is provided with an input protection circuit at the other end as well as the end that is grounded. As a result, the breakdown voltage of the LC noise filter can be further increased.
[0009] また、上述した入力保護回路は、半導体基板に形成された PN接合によって構成さ れたダイオードであることが望ましい。これにより、第 1および第 2のインダクタ導体の 少なくとも一方に過大な電圧が印加されたときに半導体基板側に電流を流すことが でき、この過大な電圧による第 1および第 2のインダクタ導体間の絶縁破壊を防止す ること力 Sできる。  [0009] Further, the input protection circuit described above is preferably a diode configured by a PN junction formed on a semiconductor substrate. As a result, when an excessive voltage is applied to at least one of the first and second inductor conductors, a current can flow through the semiconductor substrate, and the first and second inductor conductors caused by the excessive voltage can flow. Power to prevent dielectric breakdown S
[0010] また、上述した第 1のインダクタ導体の接地される端部は内周側端部であることが望 ましい。これにより、第 1のインダクタ導体の外周側に接続用のパッド等を形成する必 要がなくなるため、半導体基板の大きさを一定としたときに、第 1のインダクタ導体お よびこれに重ねて形成される第 2のインダクタ導体の最外周部の径を大きくすることが でき、大きなインダクタンスを確保することが可能となる。  [0010] Further, it is desirable that the end portion of the first inductor conductor described above that is grounded is an inner peripheral end portion. As a result, there is no need to form connection pads on the outer periphery of the first inductor conductor. Therefore, when the size of the semiconductor substrate is constant, the first inductor conductor and the first inductor conductor are formed so as to overlap therewith. The diameter of the outermost peripheral portion of the second inductor conductor can be increased, and a large inductance can be secured.
[0011] また、上述した第 1および第 2のインダクタ導体の重複面積を可変することにより周 波数特性が調整されることが望ましい。これにより、 LCノイズフィルタの面積を変えず に特性を変化させることができる。 [0011] Further, it is desirable to adjust the frequency characteristics by varying the overlapping area of the first and second inductor conductors described above. This keeps the LC noise filter area unchanged The characteristics can be changed.
[0012] また、上述した第 2のインダクタ導体の両端と第 1のインダクタ導体の一方端のそれ ぞれにはパッドが接続されており、ウェハレベル CSP (Chip Scale Package)によって ノ ッケージングがなされることが望ましい。これにより、 LCノイズフィルタをチップ部品 として形成する場合にチップ部品の小型化が可能となる。  [0012] In addition, pads are connected to both ends of the second inductor conductor and one end of the first inductor conductor described above, and knocking is performed by wafer level CSP (Chip Scale Package). It is desirable. This makes it possible to reduce the size of the chip component when the LC noise filter is formed as a chip component.
[0013] また、上述した第 1および第 2のインダクタ導体と入力保護回路が複数組共通の半 導体基板に形成されることが望ましい。これにより、多数の LCノイズフィルタが内蔵さ れる小型のチップ部品を実現することができる。  [0013] In addition, it is desirable that the first and second inductor conductors and the input protection circuit are formed on a common semiconductor substrate. As a result, it is possible to realize a small chip component incorporating a large number of LC noise filters.
[0014] また、上述した第 2のインダクタ導体は信号が入出力される信号線路に用いられ、 第 1のインダクタ導体は一方端が接地され、複数組に対応する複数の第 1のインダク タ導体の一方端が相互に接続されることが望ましい。これにより、複数の LCノイズフィ ルタが内蔵されたチップ部品において外部接続用の端子の数を減らすことができ、こ れらの端子間の距離を最大限に確保することができる。また、外部接続用の端子間 の距離を一定以上確保する必要がある場合に、チップ部品の小型化が可能となる。 図面の簡単な説明  [0014] Further, the second inductor conductor described above is used for a signal line through which signals are input and output, and the first inductor conductor is grounded at one end, and a plurality of first inductor conductors corresponding to a plurality of sets. It is desirable that one end of each is connected to each other. As a result, the number of terminals for external connection can be reduced in chip components incorporating a plurality of LC noise filters, and the distance between these terminals can be secured to the maximum. In addition, when it is necessary to ensure a certain distance between the terminals for external connection, it is possible to reduce the size of the chip component. Brief Description of Drawings
[0015] [図 1]一実施形態の LCノイズフィルタの平面図である。  FIG. 1 is a plan view of an LC noise filter according to an embodiment.
[図 2]スパイラル電極の周回部分の断面図である。  FIG. 2 is a cross-sectional view of a circumferential portion of a spiral electrode.
[図 3]パッドの断面図である。  FIG. 3 is a sectional view of the pad.
[図 4]パッドの断面図である。  FIG. 4 is a cross-sectional view of the pad.
[図 5]LCノイズフィルタの等価回路図である。  FIG. 5 is an equivalent circuit diagram of the LC noise filter.
[図 6]LCノイズフィルタの製造方法の概要の説明図である。  FIG. 6 is an explanatory diagram of an outline of a method for manufacturing an LC noise filter.
[図 7]LCノイズフィルタの製造方法の概要の説明図である。  FIG. 7 is an explanatory diagram outlining the manufacturing method of an LC noise filter.
[図 8]図 1に示す LCノイズフィルタの断面図である。  FIG. 8 is a cross-sectional view of the LC noise filter shown in FIG.
[図 9]LCノイズフィルタに対応するウェハレベル CSPの断面図である。  FIG. 9 is a cross-sectional view of a wafer level CSP corresponding to an LC noise filter.
[図 10]ウェハレベル CSPの工程を示す図である。  FIG. 10 is a diagram showing a wafer level CSP process.
[図 11]ウェハレベル CSPの工程を示す図である。  FIG. 11 is a diagram showing a wafer level CSP process.
[図 12]ウェハレベル CSPの工程を示す図である。  FIG. 12 is a diagram showing a wafer level CSP process.
[図 13]ウェハレベル CSPの工程を示す図である。 [図 14]ダイシングの具体例を示す図である。 FIG. 13 is a diagram showing a wafer level CSP process. FIG. 14 is a diagram showing a specific example of dicing.
符号の説明  Explanation of symbols
[0016] 100 LCノイズフィルタ [0016] 100 LC noise filter
110 半導体基板  110 Semiconductor substrate
112、 114、 116 N+領域  112, 114, 116 N + region
112D、 114D、 116D ダイオード  112D, 114D, 116D diode
120、 130 スノイラノレ電極  120, 130 Snoylanore electrode
122、 124、 132 ノ ッド  122, 124, 132 nodes
122A 入力端子  122A input terminal
124A 出力端子  124A output terminal
132A 接地端子  132A Grounding terminal
140 キャパシタ  140 capacitors
200、 202 絶縁層  200, 202 Insulation layer
J 10 iJBM underbump metal)  J 10 iJBM underbump metal)
320 Cu再配線  320 Cu rewiring
330 Cuポスト  330 Cu post
340 半田ボーノレ  340 Handa Bonole
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0017] 以下、本発明を適用した一実施形態の LCノイズフィルタについて、図面を参照しな 力 詳細に説明する。 Hereinafter, an LC noise filter according to an embodiment to which the present invention is applied will be described in detail with reference to the drawings.
[0018] 図 1は、一実施形態の LCノイズフィルタの平面図である。図 1に示すように、本実施 形態の LCノイズフィルタ 100は、 P形シリコン基板である半導体基板 110の表面に形 成された二重のインダクタ導体としてのスパイラル電極 120、 130と、半導体基板 110 力も遠い側(上層)の一方のスパイラル電極 120の両端近傍に形成された入出力端 子としてのパッド 122、 124と、半導体基板 110に近い側(下層)の他方のスパイラル 電極 130の内周端近傍に形成された接地端子としてのパッド 132と、これら 3つのパ ッド 122、 124、 132に対向する半導体基板 110の位置に形成された N+領域 112、 114、 116とを備えてレヽる。 [0019] 二重のスパイラル電極 120、 130のそれぞれは、所定周回数であってほぼ同一形 状を有している。例えば、金やアルミニウムを用いた 2層メタル配線を利用してこれら のスパイラル電極 120、 130が形成されている。 2層メタル構造の場合、製造プロセス にもよる力 下層のスパイラル電極 130よりも上層のスパイラル電極 120の方が膜厚 が厚くなる。本実施形態では、膜厚が厚い上層のスパイラル電極 120を信号線路用 に用い、膜厚が薄い下層のスパイラル電極 130を接地用に用レ、てレ、る(電気的な接 続状態については後述する)。 FIG. 1 is a plan view of an LC noise filter according to an embodiment. As shown in FIG. 1, the LC noise filter 100 of this embodiment includes spiral electrodes 120 and 130 as double inductor conductors formed on the surface of a semiconductor substrate 110 which is a P-type silicon substrate, and a semiconductor substrate 110. Pads 122 and 124 as input / output terminals formed near both ends of one spiral electrode 120 on the far side (upper layer) and the inner peripheral end of the other spiral electrode 130 on the side closer to the semiconductor substrate 110 (lower layer) A pad 132 as a grounding terminal formed in the vicinity and an N + region 112, 114, 116 formed at the position of the semiconductor substrate 110 facing these three pads 122, 124, 132 are provided. . Each of the double spiral electrodes 120, 130 has a predetermined number of turns and has substantially the same shape. For example, these spiral electrodes 120 and 130 are formed using a two-layer metal wiring using gold or aluminum. In the case of a two-layer metal structure, the force due to the manufacturing process The upper spiral electrode 120 is thicker than the lower spiral electrode 130. In this embodiment, the upper spiral electrode 120 with a large film thickness is used for a signal line, and the lower spiral electrode 130 with a small film thickness is used for grounding (for the electrical connection state). Will be described later).
[0020] 図 2は、スパイラル電極 120、 130の周回部分の断面図である。半導体基板 110の 表面に、絶縁層 200を挟んでスパイラル電極 130が形成されており、さらにその上に 絶縁層 202を挟んでスパイラル電極 120が形成されている。絶縁層 200、 202として は、例えば SiO が用いられる。なお、図 1および図 2に示した例では、スパイラル電  FIG. 2 is a cross-sectional view of the surrounding portions of the spiral electrodes 120 and 130. A spiral electrode 130 is formed on the surface of the semiconductor substrate 110 with an insulating layer 200 interposed therebetween, and a spiral electrode 120 is formed thereon with an insulating layer 202 interposed therebetween. For the insulating layers 200 and 202, for example, SiO 2 is used. In the example shown in FIGS. 1 and 2, spiral power is used.
2  2
極 120、 130の形状をほぼ同一とした力 少なくとも一部を重複させた状態で互いの 周回位置をずらすようにしてもよい。あるいは、周回方向に沿った長さを異ならせるよ うにしてもよい(具体的には、半導体基板 110に近レ、スパイラル電極 130の外周端側 の長さを短くする場合が考えられる)。すなわち、上述した LCノイズフィルタ 100には 、半導体基板 110上に形成された第 1のインダクタ導体としてのスパイラル電極 130 と、半導体基板 110上に形成され、少なくとも一部がスパイラル電極 130と絶縁層 20 2を挟んで所定の距離を維持した状態で重複し、この重複した部分力スパイラル電極 130よりも半導体基板 110から離れた位置に配置された第 2のインダクタ導体として のスパイラル電極 120とが備わっていればよレ、。また、本実施形態の LCノイズフィノレ タ 100に入出力される信号の周波数が高い場合等においては、スパイラル電極 120 、 130の周回数を 1以下としてもよい。  A force that makes the shapes of the poles 120 and 130 substantially the same may be shifted from each other with at least a part of the force overlapping. Alternatively, the lengths in the circumferential direction may be different (specifically, the length near the semiconductor substrate 110 and the length on the outer peripheral end side of the spiral electrode 130 may be shortened). That is, in the LC noise filter 100 described above, the spiral electrode 130 as the first inductor conductor formed on the semiconductor substrate 110 and the semiconductor substrate 110 are formed, and at least a part of the spiral electrode 130 and the insulating layer 20 are formed. 2 and a spiral electrode 120 as a second inductor conductor that is disposed at a position farther from the semiconductor substrate 110 than the overlapped partial force spiral electrode 130. I'll do it. In addition, when the frequency of the signal input / output to / from the LC noise finisher 100 of this embodiment is high, the number of turns of the spiral electrodes 120 and 130 may be 1 or less.
[0021] 一方のスパイラル電極 120の両端近傍においてこのスパイラル電極 120と一体に 形成されたパッド 122、 124は、ノイズ除去の対象となる信号を入出力するためのも のである。例えば、内周側に設けられたパッド 122が入力端子 122Aとして、外周側 に設けられたパッド 124が出力端子 124Aとして用いられる。また、これらのパッド 12 2、 124の直下には、半導体基板 110とその一部に形成された N+領域 112、 114と の間の PN接合によって形成されるダイオード 112D、 114Dが配置されている。 [0022] 図 3は、パッド 122の断面図である。なお、パッド 124の断面構造も同じであり、詳細 な説明は省略する。 P形の半導体基板 110の表面近傍に N+領域 112が形成されて おり、半導体基板 110と N+領域 112の間の PN接合によってダイオード 112Dが構 成されている。パッド 122は、 N+領域 112にコンタクトホールを介して直接接続され ている。 [0021] Pads 122 and 124 formed integrally with the spiral electrode 120 in the vicinity of both ends of one spiral electrode 120 are for inputting and outputting signals to be subjected to noise removal. For example, the pad 122 provided on the inner peripheral side is used as the input terminal 122A, and the pad 124 provided on the outer peripheral side is used as the output terminal 124A. Further, diodes 112D and 114D formed by a PN junction between the semiconductor substrate 110 and N + regions 112 and 114 formed in a part of the semiconductor substrate 110 are arranged immediately below these pads 122 and 124. . FIG. 3 is a cross-sectional view of pad 122. Note that the cross-sectional structure of the pad 124 is the same, and a detailed description thereof is omitted. An N + region 112 is formed in the vicinity of the surface of the P-type semiconductor substrate 110, and a diode 112D is configured by a PN junction between the semiconductor substrate 110 and the N + region 112. The pad 122 is directly connected to the N + region 112 through a contact hole.
[0023] 他方のスパイラル電極 130の内周端近傍に形成されたパッド 132は、接地端子 13 2Aとして用いられる。このパッド 132の直下には、コンタクトホールを介して接続され たスパイラル電極 130の端部が配置され、さらにその下には、半導体基板 110とその 一部に形成された N+領域 116との間の PN接合によって形成されるダイオード 116 Dが配置されている。 The pad 132 formed near the inner peripheral end of the other spiral electrode 130 is used as the ground terminal 132A. Immediately below the pad 132, an end of the spiral electrode 130 connected through the contact hole is arranged, and further below it is a space between the semiconductor substrate 110 and the N + region 116 formed in a part thereof. A diode 116D formed by a PN junction is disposed.
[0024] 図 4は、パッド 132の断面図である。 P形の半導体基板 110の表面近傍に N+領域 1 16が形成されており、これらの PN接合によってダイオード 116Dが構成されている。 N+領域 116の表面にはスパイラル電極 130の端部が直接形成されており、ノ ッド 13 2は、このスパイラル電極 130の端部にコンタクトホールを介して接続されている。 FIG. 4 is a cross-sectional view of the pad 132. An N + region 116 is formed in the vicinity of the surface of the P-type semiconductor substrate 110, and a diode 116D is constituted by these PN junctions. An end portion of the spiral electrode 130 is directly formed on the surface of the N + region 116, and the node 132 is connected to the end portion of the spiral electrode 130 through a contact hole.
[0025] 図 5は、 LCノイズフィルタ 100の等価回路図である。上層のスパイラル電極 120と下 層のスパイラル電極 130は、互いに重ねられて配置されているため、これらの間には キャパシタ 140が形成される。これにより、スパイラル電極 120、 130とキヤノ シタ 140 とによって、分布定数型の LCノイズフィルタ 100が構成される。また、入力端子 122 A、出力端子 124A、接地端子 132Aのそれぞれにはダイオード 112D、 114D、 11 6Dが接続されている。これらのダイオード 112D、 114D、 116Dは、入力保護用で あり、対応する端子に静電気等による過大な電圧が印加されたときにスパイラル電極 120、 130間の絶縁層 202が破壊されることを防止する。なお、スパイラル電極 130 側は、内周端近傍にのみダイオード 116Dを接続したが、外周端近傍にもダイオード を接続することにより、耐圧を上げることができる。この場合には、スパイラル電極 130 の外周端に対応する半導体基板 110の表面近傍に N+領域を形成すればよい。 FIG. 5 is an equivalent circuit diagram of the LC noise filter 100. Since the upper spiral electrode 120 and the lower spiral electrode 130 are arranged so as to overlap each other, a capacitor 140 is formed between them. Accordingly, the spiral electrodes 120 and 130 and the Canon 140 constitute a distributed constant type LC noise filter 100. Also, diodes 112D, 114D, and 116D are connected to the input terminal 122A, the output terminal 124A, and the ground terminal 132A, respectively. These diodes 112D, 114D, and 116D are for input protection, and prevent the insulating layer 202 between the spiral electrodes 120 and 130 from being destroyed when an excessive voltage due to static electricity or the like is applied to the corresponding terminals. . Although the diode 116D is connected only to the vicinity of the inner peripheral end on the spiral electrode 130 side, the withstand voltage can be increased by connecting the diode also to the vicinity of the outer peripheral end. In this case, an N + region may be formed near the surface of the semiconductor substrate 110 corresponding to the outer peripheral edge of the spiral electrode 130.
[0026] 図 6および図 7は、 LCノイズフィルタ 100の製造方法の概要の説明図である。なお 、図 6等には 1個の LCノイズフィルタ 100が示されているが、実際には、 1枚のシリコ ンウェハを用レ、て多数の LCノイズフィルタ 100が同時に形成され、 1個あるいは複数 個を単位として所定のパッケージングが行われる。 FIG. 6 and FIG. 7 are explanatory views of the outline of the manufacturing method of the LC noise filter 100. Although one LC noise filter 100 is shown in FIG. 6 and the like, in practice, a large number of LC noise filters 100 are formed simultaneously using one silicon wafer, and one or more LC noise filters 100 are formed. Predetermined packaging is performed in units of pieces.
[0027] まず、半導体基板(シリコンウェハ) 110の表面に絶縁層 200を形成し、写真蝕刻法 を用いて N+領域 112、 114、 116に対応する領域を除去する。次に、これらの領域 を通して半導体基板 100上にヒ素等を熱拡散させることにより、 N+領域 112、 114、 116を形成する(図 6)。 First, an insulating layer 200 is formed on the surface of a semiconductor substrate (silicon wafer) 110, and regions corresponding to the N + regions 112, 114, and 116 are removed using a photolithography method. Next, N + regions 112, 114, and 116 are formed by thermally diffusing arsenic or the like on the semiconductor substrate 100 through these regions (FIG. 6).
[0028] 次に、アルミニウムや金等の金属材料を表面に蒸着させた後、フォトレジストを用い た写真蝕刻法によって下層のスパイラル電極 130としての所定のパターンを形成す る(図 7)。さらに、フォトレジストを除去した後、表面に絶縁層 202形成し、写真蝕刻 法を用いて N+領域 112、 114に対応する領域とスパイラル電極 130の内周端に対 応する領域を除去する。次に、両端のパッド 122、 124がー体となった上層のスパイ ラル電極 120とパッド 132を形成する。このようにして、図 1に示す LCノイズフィルタ 1 00が完成する。 [0028] Next, after depositing a metal material such as aluminum or gold on the surface, a predetermined pattern as a lower spiral electrode 130 is formed by photolithography using a photoresist (FIG. 7). Further, after removing the photoresist, an insulating layer 202 is formed on the surface, and a region corresponding to the N + regions 112 and 114 and a region corresponding to the inner peripheral edge of the spiral electrode 130 are removed by photolithography. Next, the upper layer spiral electrode 120 and the pad 132 having the pads 122 and 124 at both ends are formed. In this way, the LC noise filter 100 shown in FIG. 1 is completed.
[0029] 上述した本実施形態の LCノイズフィルタ 100は、 LSIに含まれる一部品として形成 することが可能である力 所定のパッケージングを行ってチップ部品として製造するこ ともできる。次に、上述した LCノイズフィルタ 100に対してウェハレベル CSP (Chip Sc ale Package)を行うものとして、その具体例について説明する。  The above-described LC noise filter 100 of the present embodiment can be manufactured as a chip component by performing a predetermined packaging that can be formed as one component included in an LSI. Next, a specific example will be described assuming that a wafer level CSP (Chip Scale Package) is performed on the LC noise filter 100 described above.
[0030] 図 8は、図 1に示す LCノイズフィルタ 100の断面図であり、ウェハレベル CSPを行う 前の状態が示されている。また、図 9は LCノイズフィルタ 100に対応するウェハレべ ル CSPの断面図である。なお、図 8および図 9には、ウェハレベル CSPの外部接続 用の端子となる半田ボールに関連する部分に着目した構造が示されており、それ以 外の構造や位置関係については簡略化あるいは省略されている。  FIG. 8 is a cross-sectional view of the LC noise filter 100 shown in FIG. 1, and shows a state before performing wafer level CSP. FIG. 9 is a cross-sectional view of a wafer level CSP corresponding to the LC noise filter 100. 8 and 9 show structures that focus on the parts related to the solder balls that serve as the external connection terminals of the wafer level CSP, and other structures and positional relationships are simplified or It is omitted.
[0031] 図 9に示すように、ウェハレベル CSPでは、パッド 132が UBM (underbump metal) 310、 Cu再配線 320、 Cuポスト 330を介して半田ボール 340と接続される。他のパッ ドについても同様である。  As shown in FIG. 9, in wafer level CSP, pads 132 are connected to solder balls 340 via UBM (underbump metal) 310, Cu rewiring 320, and Cu post 330. The same applies to the other pads.
[0032] 図 10〜図 13は、ウェハレベル CSPの工程を示す図である。まず、 LCノイズフィノレ タの表面のパッシベーシヨン 300 (図 10 (A) )のさらに表面にポリイミドパターン 302を 形成する(図 10 (B) )。なお、パッシベーシヨン 300は、 LCノイズフィルタ 100を形成 する際にその表面に形成される。 [0033] 次に、ポリイミドパターン 302の表面に、パッド 132等に接続されるように UBM310 を形成する(図 10 (C) )。 UBM310は、例えば Ti層と Cu層からなる。次に、その表面 にレジストパターン 312を形成し、 Cu再配線 320を形成する(図 11 (A) )。 FIGS. 10 to 13 are diagrams showing a wafer level CSP process. First, a polyimide pattern 302 is formed on the surface of the passivation 300 (FIG. 10A) on the surface of the LC noise finer (FIG. 10B). The passivation 300 is formed on the surface when the LC noise filter 100 is formed. Next, a UBM 310 is formed on the surface of the polyimide pattern 302 so as to be connected to the pad 132 or the like (FIG. 10C). UBM310 consists of Ti layer and Cu layer, for example. Next, a resist pattern 312 is formed on the surface, and a Cu rewiring 320 is formed (FIG. 11A).
[0034] 次に、レジスト除去後(図 11 (B) )、ドライフィルムラミネータ 322を形成してスカム除 去を行った後(図11 ( )、 01ポスト330を形成する(図12 (八))。その後、レジスト剥 離、アツシングを行った後(図 12 (B) )、封止樹脂 332を形成してその表面を研磨す る(図 13 (A) )。  [0034] Next, after removing the resist (FIG. 11 (B)), after forming the dry film laminator 322 and removing the scum (FIG. 11 ()), the 01 post 330 is formed (FIG. 12 (8)). Then, after resist stripping and ashing (FIG. 12B), a sealing resin 332 is formed and its surface is polished (FIG. 13A).
[0035] 次に、 Cuポスト 330の表面に半田ボール 340を搭載した後(図 13 (B) )、リフローを 行う(図 13 (C) )。以上の各工程はウェハの状態で行われ、その後、チップ部品とし ての LCノイズフィルタ 100に切り分けるダイシングが実施される。  Next, after mounting the solder balls 340 on the surface of the Cu post 330 (FIG. 13B), reflow is performed (FIG. 13C). Each of the above steps is performed in the state of a wafer, and then dicing is performed for separating into LC noise filters 100 as chip parts.
[0036] 図 14は、ダイシングの具体例を示す図であり、 2個の LCノイズフィルタ 100が含ま れるチップ部品を製造する場合が示されている。図 14に示すチップ部品は、 lmm X 1. 4mmの大きさを有し、その中に 2個の LCノイズフィルタ 100が含まれている。 2個 の LCノイズフィルタ 100のそれぞれに備わった入力端子 122A力 別々の角部近傍 に設けられた半田ボール 340にそれぞれ対応している。同様に、 2個の LCノイズフィ ルタ 100のそれぞれに備わった入力端子 124A力 別々の角部近傍に設けられた半 田ボール 340にそれぞれ対応している。また、 2個の LCノイズフィルタのそれぞれに 備わった接地端子 132A力 中央近傍に設けられた 1つの半田ボール 340に対応し ている。このように、長方形形状を有するチップ部品の四隅に入力端子 122Aおよび 出力端子 124Aに対応する 4個の半田ボール 340を配置するとともに、中央に接地 端子 132Aに対応する 1つの半田ボール 340を配置することにより、接地された中央 の半田ボール 340とそれ以外の 4つの半田ボール 340とを大きく離間することができ 、これらの間の距離を確保しつつチップ部品の小型化が可能となる。なお、図 14に 示す例では、横長の長方形形状を横方向に 2分割してそれぞれの分割領域に LCノ ィズフィルタ 100を対応させたが、横長の長方形形状を縦方向に 2分割してそれぞれ の分割領域に LCノイズフィルタ 100を対応させてもよい。  FIG. 14 is a diagram showing a specific example of dicing, and shows a case where a chip part including two LC noise filters 100 is manufactured. The chip component shown in FIG. 14 has a size of lmm × 1.4 mm, and includes two LC noise filters 100 therein. Each of the two LC noise filters 100 has an input terminal 122A force corresponding to solder balls 340 provided in the vicinity of different corners. Similarly, each of the two LC noise filters 100 corresponds to a solder ball 340 provided in the vicinity of different corners of the input terminal 124A force provided on each of the two LC noise filters 100. Also, it corresponds to one solder ball 340 provided near the center of the ground terminal 132A force provided in each of the two LC noise filters. In this way, four solder balls 340 corresponding to the input terminal 122A and the output terminal 124A are arranged at the four corners of the chip component having a rectangular shape, and one solder ball 340 corresponding to the ground terminal 132A is arranged at the center. As a result, the grounded central solder ball 340 and the other four solder balls 340 can be largely separated from each other, and the chip component can be miniaturized while ensuring a distance therebetween. In the example shown in FIG. 14, the horizontally long rectangular shape is divided into two in the horizontal direction, and the LC noise filter 100 is associated with each divided region. However, the horizontally long rectangular shape is divided into two in the vertical direction, and The LC noise filter 100 may be associated with the divided areas.
[0037] このように、本実施形態の LCノイズフィルタ 100は、スパイラル電極 120、 130の端 部に入力保護回路としてのダイオード 112D、 114D、 116Dを設けることにより、耐 圧を高くして静電気等による破壊 (スパイラル電極 120、 130間に配置された絶縁層 202の絶縁破壊)を防止することができる。また、 2層メタル構造を採用して二重のス ノ ィラル電極 120、 130を形成した場合には、製造工程にもよるが、一般には上層と なるスパイラル電極 120の方が膜厚が厚くなるため、このスパイラル電極 120を信号 線路として用いることにより、信号線路の抵抗を下げることができる。 As described above, the LC noise filter 100 according to the present embodiment is provided with the diodes 112D, 114D, and 116D as input protection circuits at the ends of the spiral electrodes 120 and 130, thereby providing an anti-resistance. By increasing the pressure, breakdown due to static electricity or the like (insulation breakdown of the insulating layer 202 disposed between the spiral electrodes 120 and 130) can be prevented. In addition, when the double spiral electrodes 120 and 130 are formed using a two-layer metal structure, the upper spiral electrode 120 is generally thicker depending on the manufacturing process. Therefore, the resistance of the signal line can be lowered by using the spiral electrode 120 as the signal line.
[0038] また、上層のスパイラル電極 120は、両端のそれぞれに入力保護回路としてのダイ オード 112D、 114Dが設けられ、下層のスパイラル電極 130は、接地される端部に 入力保護回路としてのダイオード 116Dが設けられている。これにより、分布定数型 の LCノイズフィルタ 100を実現することができ、上層のスパイラル電極 120に入力さ れる信号に含まれるノイズ成分を除去することが可能となる。  [0038] The upper spiral electrode 120 is provided with diodes 112D and 114D as input protection circuits at both ends, and the lower spiral electrode 130 is a diode 116D as an input protection circuit at the grounded end. Is provided. As a result, a distributed constant type LC noise filter 100 can be realized, and a noise component included in a signal input to the upper spiral electrode 120 can be removed.
[0039] また、下層のスパイラル電極 130は、接地される端部とともに他の端部にも入力保 護回路としてのダイオードを設けるようにしてもよい。これにより、 LCノイズフィルタ 10 0の耐圧をさらに上げることが可能となる。  [0039] In addition, the lower spiral electrode 130 may be provided with a diode as an input protection circuit at the other end as well as at the end to be grounded. As a result, the breakdown voltage of the LC noise filter 100 can be further increased.
[0040] また、入力保護回路として、半導体基板 110に形成された PN接合によって構成さ れたダイオード 112D、 114D、 116Dを用いている。これにより、スパイラル電極 120 、 130の少なくとも一方に過大な電圧が印加されたときに半導体基板 110側に電流 を流すことができ、この過大な電圧によるスパイラル電極 120、 130間の絶縁破壊を 防止すること力できる。  [0040] Further, as the input protection circuit, diodes 112D, 114D, and 116D formed by PN junctions formed on the semiconductor substrate 110 are used. As a result, when an excessive voltage is applied to at least one of the spiral electrodes 120 and 130, a current can flow to the semiconductor substrate 110 side, and insulation breakdown between the spiral electrodes 120 and 130 due to the excessive voltage can be prevented. I can do it.
[0041] また、下層のスパイラル電極 130の接地される端部を内周側端部側に配置している 。これにより、スパイラル電極 130の外周側に接続用のパッド等を形成する必要がな くなるため、半導体基板 110の大きさを一定としたときに、スパイラル電極 130および これに重ねて形成されるスパイラル電極 120の最外周部の径を大きくすることができ 、大きなインダクタンスを確保することが可能となる。  In addition, the grounded end of the lower layer spiral electrode 130 is disposed on the inner peripheral side end. This eliminates the need to form a connection pad on the outer peripheral side of the spiral electrode 130, so that when the size of the semiconductor substrate 110 is constant, the spiral electrode 130 and the spiral formed on the spiral electrode 130 are overlapped. The diameter of the outermost periphery of the electrode 120 can be increased, and a large inductance can be secured.
[0042] また、スパイラル電極 120、 130の重複面積を周波数特性に合わせて可変するよう にしてもよレ、。これにより、 LCノイズフィルタ 100の面積や端子配置を変えずに特性 のみを変化させることができる。  [0042] Further, the overlapping area of the spiral electrodes 120 and 130 may be varied according to the frequency characteristics. As a result, only the characteristics can be changed without changing the area or terminal arrangement of the LC noise filter 100.
[0043] また、上層のスパイラル電極 120の両端と下層のスパイラル電極 130の一方端のそ れぞれにはパッドが接続されており、ウェハレベル CSP (Chip Scale Package)によつ てパッケージングがなされている。これにより、 LCノイズフィルタ 100をチップ部品とし て形成する場合にチップ部品の小型化が可能となる。 [0043] Pads are connected to both ends of the upper spiral electrode 120 and one end of the lower spiral electrode 130, respectively, and are connected by a wafer level CSP (Chip Scale Package). Packaging. As a result, when the LC noise filter 100 is formed as a chip component, the chip component can be reduced in size.
[0044] また、スパイラル電極 120、 130と入力保護回路としてのダイオード 112D、 114D、 116Dの複数組(図 14に示した例では 2組)が共通の半導体基板 110に形成されて いる。これにより、多数の LCノイズフィルタ 100が内蔵される小型のチップ部品を実 現することができる。特に、この複数組に含まれる下層のスパイラル電極 130の一方 端は相互に接続されており、これにより、複数の LCノイズフィルタ 100が内蔵された チップ部品において外部接続用の端子の数を少なくすることができるため、これらの 端子間の距離を最大限に確保することができる。換言すれば、外部接続用の端子間 の距離を一定以上確保する必要がある場合に、チップ部品の小型化が可能となる。  In addition, a plurality of sets of spiral electrodes 120 and 130 and diodes 112D, 114D, and 116D as input protection circuits (two sets in the example shown in FIG. 14) are formed on a common semiconductor substrate 110. As a result, a small chip component with a large number of built-in LC noise filters 100 can be realized. In particular, one end of the lower layer spiral electrode 130 included in the plurality of sets is connected to each other, thereby reducing the number of terminals for external connection in a chip component incorporating a plurality of LC noise filters 100. Therefore, the maximum distance between these terminals can be secured. In other words, it is possible to reduce the size of the chip component when it is necessary to ensure a certain distance between the terminals for external connection.
[0045] なお、本発明は上記実施形態に限定されるものではなぐ本発明の要旨の範囲内 において種々の変形実施が可能である。例えば、上述した実施形態ではスパイラル 電極 130の内終端にパッド 132を接続するようにした力 外終端に接続するようにし てもよい。また、ウェハレベル CSPにおいて半田ボール 340を用いるようにした力 代 わりに半田ペーストを印刷するようにしてもよい。また、図 14に示した例では、 2個の L Cノイズフィルタ 100を 1個のチップ部品に含ませるようにした力 3個以上の LCノイズ フィルタ 100を含ませるようにしてもよい。  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. For example, in the above-described embodiment, the spiral electrode 130 may be connected to an external terminal in which the pad 132 is connected to the inner terminal. Alternatively, solder paste may be printed instead of the force used to use the solder balls 340 in the wafer level CSP. Further, in the example shown in FIG. 14, the LC noise filter 100 having three or more forces in which two LC noise filters 100 are included in one chip component may be included.
産業上の利用可能性  Industrial applicability
[0046] 本発明によれば、インダクタ導体の端部に入力保護回路を設けることにより、耐圧を 高くして静電気等による破壊を防止することができる。 [0046] According to the present invention, by providing the input protection circuit at the end of the inductor conductor, the breakdown voltage can be increased and the breakdown due to static electricity or the like can be prevented.

Claims

請求の範囲 The scope of the claims
[1] 半導体基板上に形成された第 1のインダクタ導体と、  [1] a first inductor conductor formed on a semiconductor substrate;
前記半導体基板上に形成され、少なくとも一部が前記第 1のインダクタ導体と所定 の距離を維持した状態で重複し、この重複した部分が前記第 1のインダクタ導体より も前記半導体基板から離れた位置に配置された第 2のインダクタ導体と、  The semiconductor substrate is formed on the semiconductor substrate, and at least a part of the first inductor conductor overlaps with a predetermined distance maintained, and the overlapped part is located farther from the semiconductor substrate than the first inductor conductor. A second inductor conductor disposed in the
前記第 1および第 2のインダクタ導体の端部に接続され、前記半導体基板に形成さ れた半導体素子からなる入力保護回路と、  An input protection circuit comprising a semiconductor element connected to ends of the first and second inductor conductors and formed on the semiconductor substrate;
を備える LCノイズフィルタ。  LC noise filter with
[2] 請求項 1において、 [2] In claim 1,
前記第 2のインダクタ導体は信号が入出力される信号線路に用いられ、前記第 1の インダクタ導体は一方端が接地される LCノイズフィルタ。  The second inductor conductor is an LC noise filter used for a signal line through which signals are input and output, and the first inductor conductor is grounded at one end.
[3] 請求項 2において、 [3] In claim 2,
前記第 2のインダクタ導体は、両端のそれぞれに前記入力保護回路が設けられ、 前記第 1のインダクタ導体は、接地される端部に前記入力保護回路が設けられてい る LCノイズフィルタ。  The LC noise filter, wherein the second inductor conductor is provided with the input protection circuit at both ends, and the first inductor conductor is provided with the input protection circuit at a grounded end.
[4] 請求項 3において、 [4] In claim 3,
前記第 1のインダクタ導体は、接地される端部とともに他の端部にも前記入力保護 回路が設けられている LCノイズフィルタ。  The LC noise filter, wherein the first inductor conductor is provided with the input protection circuit at the other end as well as the end that is grounded.
[5] 請求項 1において、 [5] In claim 1,
前記入力保護回路は、前記半導体基板に形成された PN接合によって構成された ダイオードである LCノイズフィルタ。  The LC noise filter, wherein the input protection circuit is a diode formed by a PN junction formed on the semiconductor substrate.
[6] 請求項 2において、 [6] In claim 2,
前記第 1のインダクタ導体の接地される端部は内周側端部である LCノイズフィルタ  The end of the first inductor conductor that is grounded is an inner peripheral end. LC noise filter
[7] 請求項 1において、 [7] In claim 1,
第 1および第 2のインダクタ導体の重複面積を可変することにより周波数特性が調 整される LCノイズフィルタ。  LC noise filter whose frequency characteristics are adjusted by changing the overlapping area of the first and second inductor conductors.
[8] 請求項 1において、 前記第 2のインダクタ導体の両端と前記第 1のインダクタ導体の一方端のそれぞれ にはパッドが接続されており、ウェハレベル CSP (Chip Scale Package)によってパッ ケージングがなされる LCノイズフィルタ。 [8] In claim 1, An LC noise filter in which pads are connected to both ends of the second inductor conductor and one end of the first inductor conductor, and packaging is performed by wafer level CSP (Chip Scale Package).
[9] 請求項 8において、 [9] In claim 8,
前記第 1および第 2のインダクタ導体と前記入力保護回路が複数組共通の前記半 導体基板に形成される LCノイズフィルタ。  An LC noise filter, wherein the first and second inductor conductors and the input protection circuit are formed on the semiconductor substrate common to a plurality of sets.
[10] 請求項 9において、 [10] In claim 9,
前記第 2のインダクタ導体は信号が入出力される信号線路に用いられ、前記第 1の インダクタ導体は一方端が接地され、  The second inductor conductor is used for a signal line through which signals are input and output, and the first inductor conductor is grounded at one end,
前記複数組に対応する複数の第 1のインダクタ導体の一方端が相互に接続される LCノイズフィルタ。  An LC noise filter in which one ends of a plurality of first inductor conductors corresponding to the plurality of sets are connected to each other.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019160880A1 (en) * 2018-02-13 2019-08-22 Cirrus Logic International Semiconductor Ltd. Fabrication of integrated circuit including passive electrical component
GB2585536A (en) * 2018-02-13 2021-01-13 Cirrus Logic Int Semiconductor Ltd Fabrication of integrated circuit including passive electrical component

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