JPS63148671A - Device preventive of electrostatic breakdown in semiconductor integrated circuit device - Google Patents
Device preventive of electrostatic breakdown in semiconductor integrated circuit deviceInfo
- Publication number
- JPS63148671A JPS63148671A JP29711686A JP29711686A JPS63148671A JP S63148671 A JPS63148671 A JP S63148671A JP 29711686 A JP29711686 A JP 29711686A JP 29711686 A JP29711686 A JP 29711686A JP S63148671 A JPS63148671 A JP S63148671A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- region
- semiconductor substrate
- diode
- electrostatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 85
- 230000015556 catabolic process Effects 0.000 title claims description 24
- 230000003449 preventive effect Effects 0.000 title abstract 6
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 230000002265 prevention Effects 0.000 claims description 38
- 239000012535 impurity Substances 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 13
- 238000002955 isolation Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001502 supplementing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体集積回路装置の静電破壊防止装置に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrostatic breakdown prevention device for semiconductor integrated circuit devices.
第３図は従来の半導体集積回路装置の静電破壊防止装置
の構成を示す回路図で、図において、３１は入力端子、
３２は入力ＮＰＮ）ランジスタ、３３は前記入力ＮＰＮ
）ランジスタ３２の静電破壊を防止するために設けられ
た電流制限用抵抗体、３４は静電破壊防止用ダイオード
である。FIG. 3 is a circuit diagram showing the configuration of a conventional electrostatic breakdown prevention device for a semiconductor integrated circuit device. In the figure, 31 is an input terminal;
32 is an input NPN) transistor, 33 is the input NPN
) A current limiting resistor 34 is provided to prevent electrostatic damage of the transistor 32, and 34 is a diode for preventing electrostatic damage.
第４図は第３図に示した静電破壊防止装置の構造を示す
断面図で、第３図と同一符号は同一部分を示し、図中、
４１はＰ−型半導体基板、４２゜４３はｎ９型埋込領域
、４４ａ、４４ｂはＰ０型分離領域、４５．４６はｎ−
型半導体層、４７゜４８はＰ型拡散領域、４９．５０は
ｎ＋型拡散領域、５１ａ、５１ｂは誘電体領域である分
離用酸化物領域、Ｖｔｔは電源端子で、通常最低電位が
与えられる。FIG. 4 is a cross-sectional view showing the structure of the electrostatic damage prevention device shown in FIG. 3. The same reference numerals as in FIG.
41 is a P- type semiconductor substrate, 42°43 is an n9 type buried region, 44a and 44b are P0 type isolation regions, and 45.46 is an n- type semiconductor substrate.
type semiconductor layer, 47.degree. 48 is a P type diffusion region, 49.50 is an n+ type diffusion region, 51a and 51b are isolation oxide regions which are dielectric regions, and Vtt is a power supply terminal to which the lowest potential is usually applied.
以下、従来の静電破壊防止装置の動作について説明する
。正のサージ電圧が入力端子３１に加わった場合、この
サージ電流は電流制限用抵抗体３３によって制限された
のち、入力ＮＰＮ）ランジスタ３２に流れ込む。このと
き入力トランジスタ３２は、ベース・エミッタ接合、ベ
ース・コレクタ接続が順方向にバイアスされるので比較
的サージ耐圧が高い。The operation of the conventional electrostatic damage prevention device will be described below. When a positive surge voltage is applied to the input terminal 31, this surge current flows into the input NPN transistor 32 after being limited by the current limiting resistor 33. At this time, the input transistor 32 has a relatively high surge resistance because its base-emitter junction and base-collector connection are biased in the forward direction.
一方、負のサージ電圧が入力端子３１に印加された場合
、Ｐ型拡散領域４７、ｎｏ型拡散領域４９とから形成さ
れろ静電破壊防止用ダイオード３４により、電源端子Ｖ
ｔｔから入力端子３１へ放電される。On the other hand, when a negative surge voltage is applied to the input terminal 31, the electrostatic damage prevention diode 34 formed from the P-type diffusion region 47 and the NO-type diffusion region 49 closes the power supply terminal V.
tt is discharged to the input terminal 31.
上記のような従来の静電破壊防止装置は、静電保護ダイ
オードとして半導体集積回路装置に形成されるトランジ
スタの接合を用いているが、半導体集積回路装置の高速
化とともにその接合の深さが浅くなる傾向にあるため、
静電破壊防止用ダイオードが破壊されやすくなるという
問題点があった。Conventional electrostatic damage prevention devices such as those mentioned above use transistor junctions formed in semiconductor integrated circuit devices as electrostatic protection diodes, but as semiconductor integrated circuit devices become faster, the depth of the junction becomes shallower. Because there is a tendency to
There was a problem in that the diode for preventing electrostatic damage was easily destroyed.
この発明は、かかる問題点を解決するためになされたも
ので、正負のサージ電圧に対する静電破耐量の高い半導
体集積回路装置の静電破壊防止装置を得ることを目的と
する。The present invention has been made to solve these problems, and an object of the present invention is to provide an electrostatic breakdown prevention device for a semiconductor integrated circuit device that has high electrostatic breakdown resistance against positive and negative surge voltages.
この発明に係る半導体集積回路装置の静電破壊防止装置
は、半導体集積回路装置が構成される半導体基板上に、
電流制限用の抵抗体と、上記半導体基板の一部をアノー
ドとする、負のサージに対する第１の静電破壊防止用ダ
イオードとを設けたものにおいて、上記半導体基板の一
部をエミッタ、第１の静電破壊防止用ダイオードのカソ
ードの一部をベース、電流制限用抵抗体の一部をコレク
タとする縦型構造を負のサージに対する静電破壊防止用
トランジスタとし、更に正のサージに対する第２の静電
破壊防止用ダイオードを形成するようにしたものである
。The electrostatic discharge damage prevention device for a semiconductor integrated circuit device according to the present invention includes:
A resistor for current limiting, and a first electrostatic breakdown prevention diode for negative surge, which uses a part of the semiconductor substrate as an anode, wherein the part of the semiconductor substrate is used as an emitter, and the first diode is used as an anode. A vertical structure with a part of the cathode of the electrostatic damage prevention diode as a base and a part of the current limiting resistor as the collector is used as a transistor for preventing electrostatic damage against negative surges, and a second transistor against positive surges is used. This is to form a diode for preventing electrostatic damage.
この発明においては、正のサージ電圧が加わった場合に
は第２の静電破壊防止用ダイオードを介して放電が行わ
れ、負のサージ電圧が加わった場合には第１の静電破壊
防止用ダイオード及び静電破壊防止用トランジスタを介
して放電が行われるから、半導体集積回路装置の接合が
浅くなっても入力トランジスタが破壊されにくくなる。In this invention, when a positive surge voltage is applied, discharge is performed through the second electrostatic damage prevention diode, and when a negative surge voltage is applied, the discharge is performed through the first electrostatic damage prevention diode. Since discharge occurs through the diode and the transistor for preventing electrostatic damage, the input transistor is less likely to be destroyed even if the junction of the semiconductor integrated circuit device becomes shallow.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例による半導体集積回路装置の静
電破壊防止装置の構成を示す断面図で、図において、１
１はＰ−型半導体基板、１２．１３は半導体埋込領域で
ある高不純物濃度のｎ゛型埋込碩域（第２導電型の第１
．第２の埋込領域）、１４ａ、１４ｂはＰ０型分離領域
、１５゜１６は低不純物濃度のｎ−型半導体層（第２導
電型の第１．第２の半導体層）（１７，１８は高不純物
濃度のｎ°型拡散領域（第２導電型の第３゜第４の半導
体領域）、１９．２０はＰ型拡散領域（第１導電型の第
１．第２の半導体領域）、２１ａ、２１ｂ、２１ｃは誘
電体領域である分離用酸化物領域、１は入力端子、ＶＣ
Ｃは第１の電源端子、Ｖａｔは最低電位が与えられる第
２の電源端子である。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view showing the structure of an electrostatic breakdown prevention device for a semiconductor integrated circuit device according to an embodiment of the present invention.
1 is a P-type semiconductor substrate, 12.13 is a semiconductor buried region, which is a high impurity concentration n-type buried region (second conductivity type first
．． 15° and 16 are n-type semiconductor layers with low impurity concentration (first and second semiconductor layers of the second conductivity type) (17 and 18 are High impurity concentration n° type diffusion region (second conductivity type third and fourth semiconductor regions), 19.20 P type diffusion region (first conductivity type first and second semiconductor regions), 21a , 21b, 21c are isolation oxide regions which are dielectric regions, 1 is an input terminal, VC
C is a first power supply terminal, and Vat is a second power supply terminal to which the lowest potential is applied.
ここで、電源端子ＶＣＣ及びｖｏに印加される電圧は同
一基板上に形成される論理回路の構成に依存するが、電
流切替え型回路の場合には通常ＶＣＣを接地電位とし■
。に負電位が与えられる。Here, the voltages applied to the power supply terminals VCC and vo depend on the configuration of the logic circuit formed on the same substrate, but in the case of a current switching type circuit, VCC is usually set to the ground potential.
. A negative potential is applied to.
また、第２図は第１図に示した静電破壊防止装置の等価
回路で、第１図と同一符号は同一部分を示し、２は第１
の静電破壊防止用ダイオード、３は第２の静電破壊防止
用ダイオード、４は静電破壊防止用ＰＮＰ ）ランジス
タ（静電破壊防止用バイポーラトランジスタ）、５は電
流制限用抵抗体、６は入力ＮＰＮ）ランジスタである。In addition, Fig. 2 is an equivalent circuit of the electrostatic damage prevention device shown in Fig. 1, where the same symbols as in Fig. 1 indicate the same parts, and 2 indicates the first
A diode for preventing electrostatic damage, 3 a second diode for preventing electrostatic damage, 4 a PNP transistor for preventing electrostatic damage (bipolar transistor for preventing electrostatic damage), 5 a resistor for current limiting, 6 a resistor for current limiting. Input NPN) transistor.
第１図および第２図から明らかなように、Ｐ型拡散領域
１９は電流制限用抵抗体５となり、ｎ゛゛拡散領域１７
とｎ゛型型埋領領域１２Ｐ−型半導体基板１１とから第
１の静電破壊防止用ダイオード２が形成され、Ｐ型拡散
領域２０とｎ−型半導体Ｎ１６とｎ゛型型埋領領域１３
ｎ１型拡散領域１８とから第２の静電破壊防止用ダイオ
ード３が形成され、Ｐ−型半導体基板１１をエミッタ、
ｎ−型半導体層１５をベース、Ｐ型拡散領域１９をコレ
クタとする静電破壊防止用ＰＮＰ ）ランジスタ４が形
成されている。As is clear from FIGS. 1 and 2, the P type diffusion region 19 becomes the current limiting resistor 5, and the n゛゛ diffusion region 17
A first electrostatic breakdown prevention diode 2 is formed from the P-type semiconductor substrate 11 and the n-type buried region 12, and the P-type diffusion region 20, the n-type semiconductor N16, and the n-type buried region 13.
A second electrostatic breakdown prevention diode 3 is formed from the n1 type diffusion region 18, and the P- type semiconductor substrate 11 is used as an emitter.
A PNP transistor 4 for preventing electrostatic damage is formed having the n-type semiconductor layer 15 as a base and the P-type diffusion region 19 as a collector.
以下、第２図を参照して動作について説明する。The operation will be explained below with reference to FIG.
正のサージ電圧が入力端子１に加わった場合、第２の静
電破壊防止用ダイオード３によって入力端子ｌから第１
の電源端子ＶＣｃへ放電する。この放電によって、電流
制限用抵抗体５を介して入力ＮＰＮ）ランジスタロに流
れ込む電流が大幅に減少するため、入力ＮＰＮ）ランジ
スタロは静電破壊から免れる。When a positive surge voltage is applied to the input terminal 1, the second electrostatic damage prevention diode 3 connects the input terminal l to the first
is discharged to the power supply terminal VCc. Due to this discharge, the current flowing into the input NPN transistor through the current limiting resistor 5 is significantly reduced, so that the input NPN transistor is spared from electrostatic damage.
一方、負のサージ電圧が入力端子１に加わった場合、第
１の静電破壊防止用ダイオード２によって電源端子ｖ０
から入力端子１への放電が起こるとともに、静電破壊防
止用ＰＮＰ ）ランジスタ４によっても電源端子ｖ０か
ら入力端子への放電が起こる。この放電によって、入力
ＮＰＮ）ランジスタロ及び電流制限用抵抗体５に流れる
電流が大幅に減少するため、入力ＮＰＮ）ランジスタロ
は静電破壊から免れる。On the other hand, when a negative surge voltage is applied to the input terminal 1, the first electrostatic breakdown prevention diode 2 causes the power supply terminal v0 to
Discharge occurs from the power supply terminal v0 to the input terminal 1, and discharge also occurs from the power supply terminal v0 to the input terminal due to the PNP transistor 4 for preventing electrostatic damage. Due to this discharge, the current flowing through the input NPN transistor and the current limiting resistor 5 is significantly reduced, so that the input NPN transistor is spared from electrostatic damage.
このように、本実施例によれば正のサージに対する保護
素子として第２の静電破壊防止用ダイオードを設け、か
つ負のサージに対する第１の静電破壊防止用トランジス
タによるサージ保護能力の不足分を縦型ＰＮＰ ）ラン
ジスタを設けて補うようにしたので、半導体集積回路の
入力トランジスタを正、負両方のサージから充分保護す
ることができ、しかもその保護手段を構成する層を、可
能な限り複数の素子で共用するように構成したので、占
有面積を殆ど増大させることなく保護手段の機能向上を
達成できた。In this way, according to this embodiment, the second electrostatic breakdown prevention diode is provided as a protection element against positive surges, and the lack of surge protection ability of the first electrostatic breakdown prevention transistor against negative surges is compensated for. By supplementing this with a vertical PNP (PNP) transistor, the input transistor of the semiconductor integrated circuit can be sufficiently protected from both positive and negative surges.Moreover, the number of layers constituting the protection means can be as many as possible. Since it is configured so that it is shared by two elements, it is possible to improve the functionality of the protection means without increasing the occupied area.
以上のように、この発明によれば、半導体集積回路装置
が構成される半導体基板上に、電流制限用抵抗体と負の
サージに対する保護素子としての第１のダイオードと縦
型ＰＮＰ トランジスタ及び正のサージに対する保護素
子としての第２のダイオードを形成するようにしたので
、半導体集積回路装置の高速化に伴って接合が浅くなっ
ても入力トランジスタが過電流によって破壊されにくく
なるうえ、特別な製造工程を用いることなく半導体集積
回路装置の静電破壊防止装置の静電破壊耐量を高く出来
るという効果がある。As described above, according to the present invention, a current limiting resistor, a first diode as a negative surge protection element, a vertical PNP transistor, and a positive surge are arranged on a semiconductor substrate constituting a semiconductor integrated circuit device. By forming a second diode as a protection element against surges, the input transistor is less likely to be destroyed by overcurrent even if the junction becomes shallower as the speed of semiconductor integrated circuit devices increases. This has the effect of increasing the electrostatic breakdown resistance of the electrostatic breakdown prevention device for semiconductor integrated circuit devices without using.
第１図はこの発明の一実施例による半導体集積回路装置
の静電破壊防止装置の構成を示す断面図、第２図は第１
図に示した静電破壊防止装置の等価回路図、第３図は従
来の半導体集積回路装置の静電破壊防止装置の構成を示
す回路図、第４図は第３図に示した従来の静電破壊防止
装置の構成を示す断面図である。
図において、１．３１は入力端子、２．３４は第１の静
電破壊防止用ダイオード、３は第２の静電破壊防止用ダ
イオード、４は静電破壊防止用ＰＮＰＩ−ランジスタ（
静電破壊防止用バイポーラトランジスタ）、５．３３は
電流制限用抵抗体、６゜３２は入力ＮＰＮ）ランジスタ
、１１．４１はＰ−型半導体基板、１２．１３，４２．
４３はｎ＋型型埋領領域１４ａ、１４ｂ、１４ｃ、、４
４ａ、４４ｂはＰ゛型分離領域、１５．１６．４５．４
６はｎ−型半導体層、１７．１８は深いｎ゛型拡散領域
、１９．２０．４７．４８はＰ型拡散領域、２１ ａ、
２１ ｂ、 ２１ ｃ、 ５１ ａ、 ５
ｌ ｂは分離用酸化物領域である。
なお図中同一符号は同−又は相当部分を示す。
第１図
第２図
２： ゛第１の１争ｉる支！ｐカ上用グイオード゛３：
＃ｚの静を石良環助上用夕′イオード゛４： Ｉ！を毛
皮Ｖ方寸二用ＰＮＰＩ−ランジスク５：を九制限用低抗
体
６； 入力ＮＰＮ）ランジスタFIG. 1 is a sectional view showing the structure of an electrostatic breakdown prevention device for a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
3 is an equivalent circuit diagram of the electrostatic discharge prevention device shown in the figure, FIG. 3 is a circuit diagram showing the configuration of a conventional electrostatic discharge prevention device for a semiconductor integrated circuit device, and FIG. It is a sectional view showing the composition of an electric breakdown prevention device. In the figure, 1.31 is the input terminal, 2.34 is the first electrostatic damage prevention diode, 3 is the second electrostatic damage prevention diode, and 4 is the electrostatic damage prevention PNPI-transistor (
5.33 is a current limiting resistor, 6°32 is an input NPN) transistor, 11.41 is a P-type semiconductor substrate, 12.13, 42.
43 are n+ type buried regions 14a, 14b, 14c, 4
4a and 44b are P' type isolation regions, 15.16.45.4
6 is an n-type semiconductor layer, 17.18 is a deep n-type diffusion region, 19.20.47.48 is a P-type diffusion region, 21a,
21 b, 21 c, 51 a, 5
lb is the isolation oxide region. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 Figure 2 Figure 2: ゛The first battle! Guiode 3 for PC top:
#z's Shizuka Ishiyoshi Tamaki Sukejo Yu'iod 4: I! The fur V direction 2 for PNPI-ranjisku 5: the 9 limit for low antibody 6; input NPN)
Claims (4)
板の一部をアノード領域とする第１の静電破壊防止用ダ
イオードと、 該半導体基板の一部をエミッタ領域とする第１導電型の
静電破壊防止用バイポーラトランジスタと、 電流制限用抵抗体及び第２の静電破壊防止用ダイオード
とを備え、 上記第１の静電破壊防止用ダイオードのカソード、バイ
ポーラトランジスタのベース及びコレクタ、抵抗体の一
端並びに第２の静電破壊防止用ダイオードのアノードが
入力端子に共通接続され、上記第２の静電破壊防止用ダ
イオードのカソードが第１の電源端子に接続され、 上記半導体基板が第２の電源端子に接続されるとともに
上記抵抗体の他端が上記半導体基板上に同時に形成され
た、所望の回路を構成するバイポーラトランジスタのベ
ースに接続されて成ることを特徴とする半導体集積回路
装置の静電破壊防止装置。(1) A first electrostatic breakdown prevention diode formed on a first conductive type semiconductor substrate and having a part of the semiconductor substrate as an anode region; and a first conductive diode having a part of the semiconductor substrate as an emitter region. A bipolar transistor for preventing electrostatic damage of the type, a current limiting resistor and a second diode for preventing electrostatic damage, the cathode of the first diode for preventing electrostatic damage, the base and collector of the bipolar transistor, One end of the resistor and the anode of the second electrostatic breakdown prevention diode are commonly connected to the input terminal, the cathode of the second electrostatic breakdown prevention diode is connected to the first power supply terminal, and the semiconductor substrate is connected to the input terminal. A semiconductor integrated circuit characterized in that it is connected to a second power supply terminal, and the other end of the resistor is connected to the base of a bipolar transistor constituting a desired circuit, which is simultaneously formed on the semiconductor substrate. Electrostatic damage prevention device for equipment.
に分離された低不純物濃度の第２導電型の第１及び第２
の半導体層が形成され、 上記第１の半導体層と上記半導体基板との境界部の一部
領域には高不純物濃度の第２導電型の第１の半導体埋込
領域が形成され、 上記第２の半導体層と上記半導体基板との境界部全面に
は第２導電型の第２の半導体埋込領域が形成され、 上記第１及び第２の半導体層の表面部にはそれぞれ第１
導電型の第１及び第２の半導体領域が形成され、 上記第１及び第２の半導体層の表面部からそれぞれ上記
第１及び第２の半導体埋込領域までを接続すべく高不純
物濃度の第２導電型の第３及び第４の半導体領域が形成
されてなり、 上記第１の半導体領域を上記電流制限用抵抗体とすると
ともに、 上記半導体基板及び上記第１の半導体埋込領域により該
半導体基板の一部をアノード、該第１の半導体埋込領域
をカソードとする上記第１の静電破壊防止用ダイオード
を構成し、上記半導体基板、上記第１の半導体層、上記
第１の半導体領域により該半導体基板をエミッタ、該第
１の半導体層をベース、該第１の半導体領域をコレクタ
とする縦型構造の上記静電破壊防止用バイポーラトラン
ジスタを構成し、 上記第２の半導体領域及び上記第２の半導体層により該
第２の半導体領域をアノード、該第２の半導体層をカソ
ードとする上記第２の静電破壊防止用ダイオードを構成
したことを特徴とする特許請求の範囲第１項記載の半導
体集積回路装置の静電破壊防止装置。(2) On the semiconductor substrate, first and second semiconductor substrates of a second conductivity type with a low impurity concentration are electrically separated from each other by a dielectric region.
a first semiconductor layer of a second conductivity type with a high impurity concentration is formed in a part of the boundary between the first semiconductor layer and the semiconductor substrate; A second semiconductor buried region of a second conductivity type is formed on the entire boundary between the semiconductor layer and the semiconductor substrate, and a first semiconductor buried region is formed on the surface portions of the first and second semiconductor layers, respectively.
First and second conductivity type semiconductor regions are formed, and a high impurity concentration semiconductor region is formed to connect the surface portions of the first and second semiconductor layers to the first and second semiconductor buried regions, respectively. Third and fourth semiconductor regions of two conductivity types are formed, the first semiconductor region serves as the current limiting resistor, and the semiconductor substrate and the first semiconductor buried region The first electrostatic breakdown prevention diode has a part of the substrate as an anode and the first semiconductor buried region as a cathode, and comprises the semiconductor substrate, the first semiconductor layer, and the first semiconductor region. constitutes the electrostatic breakdown prevention bipolar transistor having a vertical structure in which the semiconductor substrate is an emitter, the first semiconductor layer is a base, and the first semiconductor region is a collector, and the second semiconductor region and the Claim 1, characterized in that the second semiconductor layer constitutes the second electrostatic breakdown prevention diode in which the second semiconductor region is an anode and the second semiconductor layer is a cathode. An electrostatic breakdown prevention device for a semiconductor integrated circuit device as described above.
一端と上記第２の半導体領域とが共通接続されるととも
に上記入力端子に接続され、 上記第１の半導体領域の他端が上記半導体基板上に同時
に形成された所望の回路を構成するバイポーラトランジ
スタのベースに接続され、 上記第４の半導体領域が上記第１の電源端子に接続され
、 上記半導体基板が上記第２の電源端子に接続されて成る
ことを特徴とする特許請求の範囲第１項または第２項記
載の半導体集積回路装置の静電破壊防止装置。(3) The third semiconductor region, one end of the first semiconductor region, and the second semiconductor region are commonly connected and connected to the input terminal, and the other end of the first semiconductor region is connected to the second semiconductor region. connected to the base of a bipolar transistor constituting a desired circuit simultaneously formed on the semiconductor substrate, the fourth semiconductor region connected to the first power terminal, and the semiconductor substrate connected to the second power terminal. An electrostatic damage prevention device for a semiconductor integrated circuit device according to claim 1 or 2, characterized in that the device is connected to one another.
もに上記第２の電源端子が負電位に設定されて成ること
を特徴とする特許請求の範囲第１項ないし第３項のいず
れかに記載の半導体集積回路装置の静電破壊防止装置。(4) Any one of claims 1 to 3, wherein the first power supply terminal is set to a ground potential and the second power supply terminal is set to a negative potential. An electrostatic breakdown prevention device for a semiconductor integrated circuit device according to .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61297116A JPH0766957B2 (en) | 1986-12-12 | 1986-12-12 | Device for preventing electrostatic breakdown of semiconductor integrated circuit devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61297116A JPH0766957B2 (en) | 1986-12-12 | 1986-12-12 | Device for preventing electrostatic breakdown of semiconductor integrated circuit devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63148671A true JPS63148671A (en) | 1988-06-21 |
| JPH0766957B2 JPH0766957B2 (en) | 1995-07-19 |
Family
ID=17842416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61297116A Expired - Fee Related JPH0766957B2 (en) | 1986-12-12 | 1986-12-12 | Device for preventing electrostatic breakdown of semiconductor integrated circuit devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0766957B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984031A (en) * | 1987-05-02 | 1991-01-08 | Telefunken Electronic Gmbh | Integrated circuit arrangement |
| EP0702410A3 (en) * | 1994-09-14 | 1996-11-06 | Oki Electric Ind Co Ltd | A transistor protection circuit |
| KR20020082400A (en) * | 2001-04-19 | 2002-10-31 | 닛본 덴기 가부시끼가이샤 | ESD protection apparatus and method for fabricating the same |
| JP2004512685A (en) * | 2000-10-16 | 2004-04-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Integrated circuit with overvoltage protection and method of manufacturing the same |
| JP2013073991A (en) * | 2011-09-27 | 2013-04-22 | Semiconductor Components Industries Llc | Semiconductor device |
| WO2024121936A1 (en) * | 2022-12-06 | 2024-06-13 | 日清紡マイクロデバイス株式会社 | Esd protection diode and structure thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6123353A (en) * | 1984-07-11 | 1986-01-31 | Hitachi Ltd | Over voltage protection element |
| JPS61171159A (en) * | 1985-01-25 | 1986-08-01 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
-
1986
- 1986-12-12 JP JP61297116A patent/JPH0766957B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6123353A (en) * | 1984-07-11 | 1986-01-31 | Hitachi Ltd | Over voltage protection element |
| JPS61171159A (en) * | 1985-01-25 | 1986-08-01 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984031A (en) * | 1987-05-02 | 1991-01-08 | Telefunken Electronic Gmbh | Integrated circuit arrangement |
| EP0702410A3 (en) * | 1994-09-14 | 1996-11-06 | Oki Electric Ind Co Ltd | A transistor protection circuit |
| US5781389A (en) * | 1994-09-14 | 1998-07-14 | Oki Electric Industry Co., Ltd. | Transistor protection circuit |
| JP2004512685A (en) * | 2000-10-16 | 2004-04-22 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Integrated circuit with overvoltage protection and method of manufacturing the same |
| KR20020082400A (en) * | 2001-04-19 | 2002-10-31 | 닛본 덴기 가부시끼가이샤 | ESD protection apparatus and method for fabricating the same |
| JP2013073991A (en) * | 2011-09-27 | 2013-04-22 | Semiconductor Components Industries Llc | Semiconductor device |
| WO2024121936A1 (en) * | 2022-12-06 | 2024-06-13 | 日清紡マイクロデバイス株式会社 | Esd protection diode and structure thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0766957B2 (en) | 1995-07-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6236087B1 (en) | SCR cell for electrical overstress protection of electronic circuits | |
| US5646433A (en) | Pad protection diode structure | |
| KR0159451B1 (en) | Protection circuit for a semiconductor device | |
| KR100200352B1 (en) | Protection device of semiconductor device | |
| EP0103306B1 (en) | Semiconductor protective device | |
| EP1046193B1 (en) | An integrated circuit provided with esd protection means | |
| US6847059B2 (en) | Semiconductor input protection circuit | |
| US5148250A (en) | Bipolar transistor as protective element for integrated circuits | |
| JPS63148671A (en) | Device preventive of electrostatic breakdown in semiconductor integrated circuit device | |
| JPH1084098A (en) | Esd protection of high-density dram using triple well tehchnology | |
| JPS5967670A (en) | Semiconductor device | |
| JP2003060059A (en) | Protective circuit and protective element | |
| JP4457620B2 (en) | ESD protection circuit | |
| JPH0478162A (en) | Protecting device for integrated circuit | |
| KR0169360B1 (en) | Protection device of semiconductor device | |
| KR0169359B1 (en) | Protection device of semiconductor device | |
| JP2656045B2 (en) | Electrostatic discharge protection circuit | |
| JPH0523065B2 (en) | ||
| JPS63301555A (en) | Semiconductor device | |
| JPH06120412A (en) | Protecting device of semiconductor | |
| JPS6352469A (en) | Electrostatic breakdown preventing device for semiconductor integrated circuit device | |
| KR100230404B1 (en) | Electrostatic discharge protection | |
| JPS58186959A (en) | Semiconductor device | |
| JPH06140576A (en) | Ic protective device against electrostatic breakdown | |
| KR100198658B1 (en) | Esd protection circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |