JPH0766957B2 - Device for preventing electrostatic breakdown of semiconductor integrated circuit devices - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic breakdown prevention device for a semiconductor integrated circuit device.

[Conventional technology]

FIG. 3 is a circuit diagram showing the structure of a conventional electrostatic breakdown prevention device for a semiconductor integrated circuit device, in which 31 is an input terminal and 32 is an input terminal.
Is an input NPN transistor, 33 is the input NPN transistor
A current limiting resistor provided to prevent electrostatic breakdown of 32, and an electrostatic breakdown prevention diode 34.

FIG. 4 is a cross-sectional view showing the structure of the electrostatic breakdown prevention device shown in FIG. 3, and the same reference numerals as those in FIG. 3 denote the same parts.
41 is a P ^- type semiconductor substrate, 42 and 43 are n ⁺ type buried regions, and 44a and 44b are
P ⁺ type isolation regions, 45 and 46 n ⁻ type semiconductor layers, 47 and 48 P type diffusion regions, 49 and 50 n ⁺ type diffusion regions, 51a and 51b are isolation oxide regions that are dielectric regions, V _EE is a power supply pin and is usually given the lowest potential.

The operation of the conventional electrostatic breakdown prevention device will be described below. When a positive surge voltage is applied to the input terminal 31, this surge current is limited by the current limiting resistor 33 and then flows into the input NPN transistor 32. At this time, the input transistor 32 has a relatively high surge withstand voltage because the base-emitter junction and the base-collector connection are forward biased.

On the other hand, when a negative surge voltage is applied to the input terminal 31,
The electrostatic breakdown preventing diode 34 formed of the P type diffusion region 47 and the n ⁺ type diffusion region 49 discharges the power supply terminal V _EE to the input terminal 31.

[Problems to be solved by the invention]

The conventional electrostatic breakdown prevention device as described above uses the junction of the transistors formed in the semiconductor integrated circuit device as the electrostatic protection diode, but the junction depth becomes shallow as the speed of the semiconductor integrated circuit device increases. Tend to be
There is a problem that the electrostatic breakdown prevention diode is easily destroyed.

The present invention has been made in order to solve such a problem, and an object thereof is to obtain an electrostatic breakdown prevention device for a semiconductor integrated circuit device having a high electrostatic breakdown resistance against positive and negative surge voltages.

[Means for solving problems]

An electrostatic breakdown prevention device for a semiconductor integrated circuit device according to the present invention is an electrostatic breakdown prevention device formed on a P-type semiconductor substrate together with a bipolar semiconductor integrated circuit device and performing surge protection on the bipolar semiconductor integrated circuit device. The first and second n-type regions formed in a predetermined portion of the upper region of the P-type semiconductor substrate so as to be electrically isolated from other portions of the upper region, and the first and second n-type regions. The first and second P-type regions each formed in an island shape in the n-type region, and a part other than a part of the boundary between the first n-type region and the lower region of the semiconductor substrate A third n-type region having a high impurity concentration that is buried and formed, and a fourth n-type that has a high impurity concentration and is buried at the boundary between the second n-type region and the lower region of the semiconductor substrate. Region and within the first n-type region In a region different from the first P-type region forming region, a fifth its bottom is made of high impurity concentration is formed to reach the part of the third n-type region
Of the second n-type region and a region of the second n-type region different from the formation region of the second p-type region, so that the lowermost part thereof reaches a part of the fourth n-type region. And a sixth n-type region having a high impurity concentration, wherein one end of the first P-type region is connected to a base of an input transistor which constitutes an input portion of the bipolar semiconductor integrated circuit device. The other end of the first P-type region, the second P-type region,
And the fifth n-type region is commonly connected to the input terminal, the lower region of the P-type semiconductor substrate is connected to the negative side of the power source,
The sixth n-type region is connected to the positive side of the power supply.

[Action]

In the present invention, because of the above-mentioned configuration, the diode composed of the second P-type region and the second, fourth and sixth n-type regions serves as a protection element against positive surge. A positive surge voltage is discharged to the positive side of the power source by the first diode, and the input constituting the input section of the bipolar semiconductor integrated circuit device is caused by the discharge through the resistor formed of the first P-type region. The positive surge current that flows into the base of the transistor is greatly reduced, and with a higher breakdown voltage, electrostatic breakdown can be prevented,
For negative surge, a second diode composed of the third and fifth n-type regions and a lower region of the P-type semiconductor substrate, and the first P-type region and the first diode. A vertical structure having an n-type region and a lower region of the P-type semiconductor substrate
The PNP transistor serves as a protection element, and the negative surge current is shunted not only to the n-type region that is the cathode of the second diode but also to the collector region (P-type region) of the PNP transistor. As the size of the PNP transistor of the vertical structure is reduced, the junction of the PNP transistor of the vertical structure and the transistor of the bipolar semiconductor integrated circuit device, that is, the first n-type region formed in the upper region of the P-type semiconductor substrate. Is longer than that of a transistor formed in a different n-type region, and its junction breakdown voltage is high, so that electrostatic breakdown can be prevented with a higher breakdown voltage.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. First
FIG. 1 is a sectional view showing the structure of an electrostatic breakdown prevention device for a semiconductor integrated circuit device according to an embodiment of the present invention.
Is a P ⁻ -type semiconductor substrate, 12 and 13 are high-impurity-concentration n ⁺ -type buried regions (second conductivity type first and second buried regions) that are semiconductor buried regions, and 14a and 14b are P ⁺ -type semiconductor substrates. N ^- type semiconductor layers (second conductivity type first and second semiconductor layers) having a low impurity concentration,
17, 18 are n ⁺ type diffusion regions of high impurity concentration (second conductivity type first
3, 4th semiconductor region), 19 and 20 are P type diffusion regions (first conductivity type 1st and 2nd semiconductor regions), 21a, 21b and 21c are isolation oxide regions which are dielectric regions, _{Reference numeral} 1 is an input terminal, V _CC is a first power supply terminal, and V _EE is a second power supply terminal to which the lowest potential is applied.

Here, the voltage applied to the power supply terminals V _CC and V _EE depends on the configuration of the logic circuit formed on the same substrate, but in the case of a current switching type circuit, normally V _{CC is set} to the ground potential and V _EE A negative potential is applied.

2 is an equivalent circuit diagram of the electrostatic breakdown prevention device shown in FIG. 1. The same reference numerals as those in FIG. 1 denote the same parts, 2 is a first electrostatic breakdown prevention diode, and 3 is a first electrostatic breakdown prevention diode. 2 is a diode for preventing electrostatic breakdown, 4 is a PNP transistor for preventing electrostatic breakdown (bipolar transistor for preventing electrostatic breakdown), 5 is a resistor for limiting current, and 6 is an input NPN transistor.

As is clear from FIGS. 1 and 2, the P-type diffusion region
19 serves as a current limiting resistor 5, and the first electrostatic breakdown preventing diode 2 is formed from the n ⁺ type diffusion region 17, the n ⁺ type buried region 12, and the P ⁻ type semiconductor substrate 11, and the P type diffusion region is formed. From the region 20, the n ⁻ type semiconductor layer 16, the n ⁺ type buried region 13 and the n ⁺ type diffusion region 18, the second
The electrostatic breakdown preventing diode 3 is formed, and the electrostatic breakdown preventing PNP transistor 4 having the P ⁻ type semiconductor substrate 11 as the emitter, the n ⁻ type semiconductor layer 15 as the base, and the P type diffusion region 19 as the collector is formed. ing.

The operation will be described below with reference to FIG.

When a positive surge voltage is applied to the input terminal 1, the second electrostatic breakdown preventing diode 3 causes
Discharge to the power supply terminal V _{CC of} . Due to this discharge, the current flowing into the input NPN transistor 6 via the current limiting resistor 5 is significantly reduced, so that the input NPN transistor 6
Is free from electrostatic damage.

On the other hand, when a negative surge voltage is applied to the input terminal 1, the first electrostatic breakdown prevention diode 2 causes the power supply terminal V _EE
Is discharged from the power supply terminal V _EE to the input terminal by the electrostatic breakdown prevention PNP transistor 4. Due to this discharge, the current flowing through the input NPN transistor 6 and the current limiting resistor 5 is significantly reduced, so that the input NPN transistor 6 is protected from electrostatic breakdown.

Since the second electrostatic breakdown preventing diode 3 is provided as a protection element against a positive surge in such a device of this embodiment, when a positive surge voltage is applied to the input terminal 1, the diode 3 prevents the surge. Power supply terminal with positive surge voltage
By discharging through V _{CC, the} positive surge current flowing into the base of the input NPN transistor 6 which constitutes the input portion of the bipolar type semiconductor integrated circuit device through the current limiting resistor 5 is significantly reduced by the discharge. Higher withstand voltage can prevent electrostatic breakdown, and
Since the first electrostatic breakdown prevention diode 2 and the vertical structure PNP transistor 4 are used as the protection element against the negative surge, the negative surge current is generated by the cathode of the first electrostatic breakdown prevention diode 2. In addition to the n ⁺ type diffusion regions 12 and 17, which are the above, the current density is reduced by shunting the current to the collector region (P type diffusion region 19) of the vertical type PNP transistor 4 and the vertical type PNP transistor 4 is also formed. The junction of the transistors 4 is formed in a transistor that constitutes the bipolar semiconductor integrated circuit device, that is, in an n-type region different from the n-type diffusion regions 15 and 16 formed in the upper region of the P ⁻ -type conductivity type semiconductor substrate 11. Since the length of the transistor thus formed is longer than that of the transistor and the junction breakdown voltage thereof is high, electrostatic breakdown can be prevented with a higher breakdown voltage.

〔The invention's effect〕

As described above, the electrostatic breakdown preventing device for a semiconductor integrated circuit device according to the present invention is formed on a P-type semiconductor substrate together with the bipolar semiconductor integrated circuit device, and performs electrostatic protection for surge protection of the bipolar semiconductor integrated circuit device. A destruction prevention device, comprising: first and second n-type regions formed in a predetermined portion of the upper region of the P-type semiconductor substrate so as to be electrically isolated from other portions of the upper region; 1
And the first and second islands formed in the second n-type region, respectively.
A third n-type region having a high impurity concentration, which is embedded in a second P-type region and a portion other than a part of a boundary between the first n-type region and the lower region of the semiconductor substrate. When,
A fourth n-type region having a high impurity concentration, which is embedded and formed in a boundary portion between the second n-type region and the lower region of the semiconductor substrate, and the first P-type region in the first n-type region. In the area different from the area where the mold area is formed, the lowermost part is the third area.
Region different from the formation region of the second P-type region in the second n-type region and the fifth n-type region formed to reach a part of the n-type region of high impurity concentration And a sixth n-type region having a high impurity concentration formed so that the lowermost part thereof reaches a part of the fourth n-type region,
One end of the first P-type region is connected to the base of an input transistor that constitutes an input section of the bipolar semiconductor integrated circuit device, the other end of the first P-type region, the second
The P-type region and the fifth n-type region are commonly connected to the input terminal, the lower region of the P-type semiconductor substrate is connected to the negative side of the power source, and the sixth n-type region is the positive side of the power source. Since it is assumed that the positive surge is connected to the second
The first diode composed of the P-type region and the second, fourth, and sixth n-type regions serves as a protective element, and a positive surge voltage is discharged to the positive side of the power source by the first diode, Due to such discharge, the positive surge current flowing into the base of the input transistor constituting the input section of the bipolar semiconductor integrated circuit device through the resistor formed of the first P-type region is significantly reduced. With a higher breakdown voltage, electrostatic breakdown can be prevented, and with respect to a negative surge, a second region composed of the third and fifth n-type regions and the lower region of the P-type semiconductor substrate can be used. And a PNP transistor having a vertical structure composed of the first P-type region, the first n-type region and the lower region of the P-type semiconductor substrate serves as a protection element, and a negative surge current is generated by the At the cathode of diode 2 That not only n-type region only, the PN
By shunting the current to the collector region (P-type region) of the P-transistor, the current density is reduced, and the junction of the PNP transistor having the vertical structure is a transistor forming the bipolar semiconductor integrated circuit device, that is, Since the transistor formed in the n-type region different from the first n-type region formed in the upper region of the P-type conductivity type semiconductor substrate is longer than that of the transistor and the junction breakdown voltage thereof is high. ， With a higher breakdown voltage, there is an effect that electrostatic breakdown can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view showing the structure of an electrostatic breakdown preventing device for a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
FIG. 3 is an equivalent circuit diagram of the electrostatic breakdown prevention device shown in FIG. 3, FIG. 3 is a circuit diagram showing a structure of the conventional electrostatic breakdown prevention device of a semiconductor integrated circuit device, and FIG. 4 is a conventional static electricity prevention device shown in FIG. It is sectional drawing which shows the structure of an electric breakdown prevention apparatus. In the figure, 1 and 31 are input terminals, 2 and 34 are first electrostatic breakdown prevention diodes, 3 is a second electrostatic breakdown prevention diode, and 4 is an electrostatic breakdown prevention PNP transistor (electrostatic breakdown prevention Bipolar transistor), 5,33 are current limiting resistors, 6,32 are input NPN transistors, 11,41 are P ^- type semiconductor substrates, 12,13,42,43 are n ⁺ type buried regions, 14a, 14b, 14c, 44a, 44b
Is a P ⁺ type isolation region, 15,16,45,46 are n ⁻ type semiconductor layers, 17,18 are deep n ⁺ type diffusion regions, 19,20,47,48 are P type diffusion regions, 21a, 2
1b, 21c, 51a and 51b are isolation oxide regions. The same reference numerals in the drawings indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 23/522 23/556 23/60 23/62 27/04 29/73 29/866 H01L 29 / 90 D 29/72

Claims (1)

[Claims] 1. An electrostatic breakdown prevention device formed on a P-type semiconductor substrate together with a bipolar semiconductor integrated circuit device for surge protection of the bipolar semiconductor integrated circuit device, the device being provided in an upper region of the P-type semiconductor substrate. First and second n-type regions formed in a predetermined portion so as to be electrically isolated from other portions in the upper region, and island-shaped in the first and second n-type regions, respectively. A first and second P-type region, and a third high-impurity concentration embedded in a portion other than a part of a boundary between the first n-type region and the lower region of the semiconductor substrate. In the first n-type region, a fourth n-type region having a high impurity concentration and buried in a boundary portion between the second n-type region and the lower region of the semiconductor substrate. Different from the formation region of the first P-type region A fifth n-type region having a high impurity concentration, which is formed so that the lowermost part thereof reaches a part of the third n-type region, and the second n-type region in the second n-type region. A sixth n-type region having a high impurity concentration, which is formed such that the lowermost part thereof reaches a part of the fourth n-type region in a region different from the formation region of the P-type region, One end of the P-type region 1 is connected to the base of an input transistor forming the input section of the bipolar semiconductor integrated circuit device, the other end of the first P-type region, the second p-type region, and The fifth n-type region is commonly connected to an input terminal, the lower region of the P-type semiconductor substrate is connected to the negative side of the power supply, and the sixth n-type region is connected to the positive side of the power supply. A device for preventing electrostatic breakdown of a semiconductor integrated circuit device, comprising: