JPS6348192B2 - - Google Patents
Info
- Publication number
- JPS6348192B2 JPS6348192B2 JP55110019A JP11001980A JPS6348192B2 JP S6348192 B2 JPS6348192 B2 JP S6348192B2 JP 55110019 A JP55110019 A JP 55110019A JP 11001980 A JP11001980 A JP 11001980A JP S6348192 B2 JPS6348192 B2 JP S6348192B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- collector
- impurity
- base
- base region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000012535 impurity Substances 0.000 claims description 43
- 230000015556 catabolic process Effects 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 description 6
- 230000001681 protective effect Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 238000011109 contamination Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、接合型トランジスタからなる半導体
装置に係り、特に保護用ツエナーダイオードを内
装した半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device comprising a junction transistor, and more particularly to a semiconductor device incorporating a protective Zener diode.
従来、電力用トランジスタは、如何なる場合に
おいても電力用トランジスタが安全動作領域
（ASO：Area of Safe Operation）内で作動さ
せるために二次降状破壊制限領域（Ｓ／Ｂ制限領
域）に追い込まれないように保護回路を設けてい
る。 Conventionally, power transistors are not forced into the secondary breakdown limited area (S/B limited area) in order to operate within the safe operation area (ASO) under any circumstances. A protection circuit is provided.
保護回路としては一般に電力用トランジスタの
コレクタとベース間に保護用のツエナーダイオー
ドを挿入したものが用いられている。ツエナーダ
イオードの耐圧は電力用トランジスタの保障耐圧
よりも低く、しかも出力用トランジスタの動作点
電圧よりも高い点に設定されている。 As a protection circuit, a protection circuit in which a Zener diode for protection is inserted between the collector and base of a power transistor is generally used. The breakdown voltage of the Zener diode is set to be lower than the guaranteed breakdown voltage of the power transistor, and higher than the operating point voltage of the output transistor.
而して、もし負荷シヨート等の不測の事態を生
じたとき、VCC（出力電圧）はいきなり出力用ト
ランジスタのコレクタに印加されることになる
が、コレクタ、ベース間に挿入された保護用のツ
エナーダイオードが先にブレークダウンを起す。
このときのブレークダウン電流は電力用トランジ
スタのベース電流として加わり、トランジスタの
基本原理からしてコレクタ電流として電流増幅器
（hFE）倍になつて現われる。この電流によつてエ
ミツタまたはコレクタのいずれかに直結されたフ
ユーズ（エミツタの回路に挿入されたフユーズ）
を断つことによつて電力用トランジスタをＳ／Ｂ
領域に到らしめることなく保護できるようになつ
ている。 Therefore, if an unexpected situation such as a load short occurs, V CC (output voltage) will suddenly be applied to the collector of the output transistor, but the protective The Zener diode breaks down first.
The breakdown current at this time is added as a base current of the power transistor, and based on the basic principle of transistors, it appears as a collector current times the current amplifier (h FE ). A fuse that is directly connected to either the emitter or collector by this current (a fuse inserted in the emitter circuit)
S/B of power transistors by cutting off
It is now possible to protect the area without allowing it to reach the area.
しかしながらこのように電力用トランジスタの
コレクタとベース間にツエナーダイオードを設け
た半導体装置は、次のような欠点を有している。 However, such a semiconductor device in which a Zener diode is provided between the collector and base of a power transistor has the following drawbacks.
(1) 回路構成のための必要部品数が多く、回路が
高価になる。(1) A large number of parts are required for the circuit configuration, making the circuit expensive.
(2) 電力用トランジスタと保護用ダイオードと組
み合わせを誤ることがある。(2) Power transistors and protection diodes may be incorrectly combined.
(3) 電気回路の接続の労力とスペースが大きく、
機器を小型化することができない。(3) It takes a lot of effort and space to connect the electric circuit;
It is not possible to downsize the equipment.
(4) 回路装置、機器の信頼性が低い。(4) Low reliability of circuit devices and equipment.
(5) 電気回路の耐湿、汚染に対し弱い。(5) Moisture resistance of electrical circuits and susceptibility to contamination.
本発明は、かかる点に鑑みてなされたものであ
り、所望の接合型トランジスタが形成された半導
体基板内に、保護用のツエナーダイオードを形成
して集積度、信頼性を向上させるとともに価格の
低減を図つた半導体装置を提供するものである。 The present invention has been made in view of the above points, and improves the degree of integration and reliability by forming a protective Zener diode in a semiconductor substrate on which a desired junction transistor is formed, and reduces the cost. The present invention provides a semiconductor device that achieves the following.
以下、本発明の実施例を図面を参照して説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明の一実施例の断面図である。
図中１は、N+導電型の半導体基板であり、半導
体基板１上にはN-導電型のコレクタ領域２が設
けられている。コレクタ領域２の所定部位にはＰ
導電型のベース領域３が形成されている。 FIG. 1 is a sectional view of one embodiment of the present invention.
In the figure, reference numeral 1 denotes an N + conductivity type semiconductor substrate, and an N - conductivity type collector region 2 is provided on the semiconductor substrate 1 . A predetermined portion of the collector area 2 has P
A conductive type base region 3 is formed.
ベース領域３内にはベースコンタクトのオーミ
ツク性を良好にするためにP+導電型の低抵抗領
域3aが形成されている。この低抵抗領域３ａで
囲まれたベース領域３内には、N+導電型のエミ
ツタ領域４が形成されている。 A low resistance region 3a of P + conductivity type is formed in the base region 3 in order to improve the ohmic properties of the base contact. An N + conductivity type emitter region 4 is formed in the base region 3 surrounded by the low resistance region 3a.
また、コレクタ領域２にはベース領域３からの
空乏層が延在する範囲内にＰ導電型の不純物領域
５が選択的に形成されている。不純物領域５とベ
ース領域３間のコレクタ領域２の表面部分には、
ベース領域３と所定間隔を設けてコレクタ領域２
よりも高い不純物濃度を有するN+導電型の高不
純物領域６が形成されている。 Further, in the collector region 2, a P conductivity type impurity region 5 is selectively formed within the range in which the depletion layer extends from the base region 3. In the surface portion of the collector region 2 between the impurity region 5 and the base region 3,
A collector region 2 is provided with a predetermined interval from the base region 3.
A highly impurity region 6 of N + conductivity type having an impurity concentration higher than that is formed.
また、不純物領域５、高不純物領域６、コレク
タ領域２、ベース領域３、低抵抗領域3a、及び
エミツタ領域４の表面には、酸化膜７が形成され
ており、酸化膜７に穿設されたコンタクトホール
を介してエミツタ領域４、及び低抵抗領域３ａ
（ベース領域３）に接合する電極８が夫々形成さ
れている。不純物領域５及びコレクタ領域２の露
出表面には、これらの領域を同電位するための電
極９が設けられている。 Further, an oxide film 7 is formed on the surfaces of the impurity region 5, the high impurity region 6, the collector region 2, the base region 3, the low resistance region 3a, and the emitter region 4. Emitter region 4 and low resistance region 3a through contact hole
Electrodes 8 are respectively formed to be bonded to (base region 3). An electrode 9 is provided on the exposed surfaces of impurity region 5 and collector region 2 to bring these regions to the same potential.
ここで、ベース領域３と不純物領域５間の間隔
（WX）は、第２図に示す如く、ベース領域３と高
不純物領域６間の間隔（WY）より大きく設定さ
れている。 Here, the distance ( W.sub.X ) between the base region 3 and the impurity region 5 is set larger than the distance ( W.sub.Y ) between the base region 3 and the highly impurity region 6, as shown in FIG.
また、コレクタ領域２の不純物濃度（CN -）に
対する高不純領域６の不純物濃度（CN）の比
（CN／CN -）は、ベース領域３と不純物領域５との間
隔（WX）及び前記ベース領域３と高不純物領域
６との間隔（WY）に応じてベース領域３と不純
物領域５間の耐圧が、ベース領域３と高不純物領
域６間の耐圧及びベース領域３とコレクタ領域２
間の耐圧よりも小さくなるように設定されてい
る。 Further, the ratio (C N /C N - ) of the impurity concentration (C N ) of the high impurity region 6 to the impurity concentration (C N - ) of the collector region 2 is determined by the distance between the base region 3 and the impurity region 5 ( W ) and the distance (W Y ) between the base region 3 and the high impurity region 6, the breakdown voltage between the base region 3 and the impurity region 5 is determined by the breakdown voltage between the base region 3 and the high impurity region 6 and the breakdown voltage between the base region 3 and the collector. Area 2
It is set to be lower than the withstand voltage between the two.
このように構成された半導体装置１０によれ
ば、ベース領域３と不純物領域５間の耐圧が、ベ
ース領域３と高不純物領域６間の耐圧及び、ベー
ス領域３とコレクタ領域２間の耐圧より小さく設
定されているので、電力用トランジスタを用いる
電気回路において電力用トランジスタに並列に接
続して保護するための保護ダイオードを特に外部
回路に設けることを要せず、電力用トランジスタ
素子内に内装（すなわち、同一半導体基板に設け
ること）しているので次のような利点を有する。 According to the semiconductor device 10 configured in this manner, the breakdown voltage between the base region 3 and the impurity region 5 is smaller than the breakdown voltage between the base region 3 and the high impurity region 6 and the breakdown voltage between the base region 3 and the collector region 2. Therefore, in an electric circuit using a power transistor, there is no need to provide a protection diode in the external circuit to protect the power transistor by connecting it in parallel with the power transistor. , provided on the same semiconductor substrate), it has the following advantages.
(A) 回路構成のための必要部品が低減できるので
廉価は回路を提供できる。(A) Since the number of parts required for the circuit configuration can be reduced, the circuit can be provided at a low price.
(B) 電力用トランジスタとして一体になるため、
電力用トランジスタと保護用ダイオードとの組
み合わせを誤ることがない。(B) Since it is integrated as a power transistor,
There is no possibility of making a mistake in the combination of a power transistor and a protection diode.
(C) 電気回路の接続の労力とスペースが節減で
き、集積度の向上とともに機器を小型化でき
る。(C) Labor and space for connecting electrical circuits can be saved, and devices can be made smaller as the degree of integration is improved.
(D) 回路装置、機器の信頼性が向上する。(D) The reliability of circuit devices and equipment will improve.
(E) 電気回路の耐湿、汚染防止に有効である。(E) Effective in preventing moisture and contamination of electrical circuits.
因に、コレクタ領域２の不純物濃度（CN -）を
２×1014（１／cm3）、ベース領域３と不純物領域５
の間隔（WX）を25μ、ベース領域３と高不純物領
域６の間隔（WY）を15μとすると、領ベース領域
３とコレクタ領域２間の耐圧（BV1）は、下記式
（）に示す如く算出され、ベース領域３と高不
純物領域６間の耐圧（BV2）は、下記式（）に
示す如く算出され、ベース領域３と不純物領域５
間の耐圧（BV3）は、下記式（）に示す如く算
出される。 Incidentally, the impurity concentration (C N - ) of the collector region 2 is 2×10 14 (1/cm 3 ), and the impurity concentration of the base region 3 and the impurity region 5 is 2×10 14 (1/cm 3 ).
Assuming that the distance between the base region 3 and the highly impurity region 6 ( W The breakdown voltage (BV 2 ) between the base region 3 and the highly impurity region 6 is calculated as shown in the following formula ().
The breakdown voltage (BV 3 ) between is calculated as shown in the following formula ().
（）BV1＝Ks・εo・εcrit 2／2q・CN -＝11.7×8.86
×10-14×（2.3×105）2／２×1.6×10-19×２×1014＝
857（Ｖ）
（）BV2＝εcrit・WY−ｑ・CN−・WY2／2KS・εO
＝2.3×105×15×10-4−1.5×10-19×２×1014×（15
×10-4）2／２×11.7×8.86×10-14＝210（Ｖ）
（）BV3＝ｑ・CN−WX 2／2KS・εO＝1.6×10-19×２
×1014×（25×10-14）2／２×11.7×8.86×10-14＝97
（Ｖ）
また、ベース領域３と不純物領域５がない場合
のエミツタ領域４とコレクタ領域２間の耐圧
（VCEO）を電流増幅率（hFE）を100と仮定して下
記（）式から求めると
となる。 ()BV 1 = Ks・εo・ε crit 2 /2q・C N - = 11.7×8.86
×10 -14 × (2.3 × 10 5 ) 2 / 2 × 1.6 × 10 -19 × 2 × 10 14 =
857 (V) ()BV 2 = ε crit・W Y −q・C N −・W Y2 ／2K S・ε O ＝2.3×10 5 ×15×10 -4 −1.5×10 -19 ×2×10 14 × (15
×10 -4 ) 2 /2 × 11.7 × 8.86 × 10 -14 = 210 (V) () BV 3 = q・C N −W X 2 /2K S・ε O = 1.6×10 -19 ×2
×10 14 × (25 × 10 -14 ) 2 / 2 × 11.7 × 8.86 × 10 -14 = 97
(V) Also, the withstand voltage (V CEO ) between the emitter region 4 and the collector region 2 when there is no base region 3 and impurity region 5 is calculated from the following formula () assuming that the current amplification factor (h FE ) is 100. and becomes.
つまり、この半導体装置では、コレクタ・エミ
ツタ間逆耐圧（VCEO）が271Vのトランジスタに
コレクタ・ベース逆耐圧（VZ）が97Vのツエナ
ーダイオードを装着したことになる。 In other words, in this semiconductor device, a Zener diode with a collector-base reverse breakdown voltage (V Z ) of 97V is attached to a transistor with a collector-emitter reverse breakdown voltage (V CEO ) of 271V.
尚、上記式（〜）中の各記号の意味は次の
通りである。 In addition, the meaning of each symbol in the above formula (-) is as follows.
KS：半導体基板の静電定数
εO：真空中の誘電率
εcrit：臨界電解
ｑ：移動電荷
CN -：コレクタ領域の不純物濃度
CN：高不純物領域の不純物濃度
WX：ベース領域と不純物領域間の距離
VCEO：コレクタ・エミツタ間逆耐圧
VZ：コレクタ・ベース逆耐圧
また、実施例ではNPNトランジスタに本発明
を適用したものについて説明したが、この他にも
PNPトランジスタにも適用できることは勿論で
ある。K S : Electrostatic constant of semiconductor substrate ε O : Dielectric constant in vacuum ε crit : Critical electrolyte q : Mobile charge C N - : Impurity concentration in collector region C N : Impurity concentration in high impurity region W X : Base region and Distance between impurity regions V CEO : Collector-emitter reverse breakdown voltage V Z : Collector-base reverse breakdown voltage Additionally, in the embodiment, the present invention was applied to an NPN transistor, but there are other applications as well.
Of course, it can also be applied to PNP transistors.
以上説明した如く、本発明に係る半導体装置に
よれば、接合型トランジスタが形成された半導体
基板内に保護用のダイオードを設けたので、集積
度及び信頼性を向上させることができるととも
に、価格を低減させることができる等顕著な効果
を有するものである。 As explained above, according to the semiconductor device according to the present invention, since the protective diode is provided in the semiconductor substrate on which the junction transistor is formed, the degree of integration and reliability can be improved, and the price can be reduced. It has remarkable effects such as being able to reduce the amount of water used.
第１図は、本発明の一実施例の断面図、第２図
は、同実施例の構造を示す拡大図である。
２……コレクタ領域、３……ベース領域、４…
…エミツタ領域、５……不純物領域、６……高不
純物領域、１０……半導体装置。
FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is an enlarged view showing the structure of the same embodiment. 2... Collector area, 3... Base area, 4...
...Emitter region, 5...Impurity region, 6...High impurity region, 10 ...Semiconductor device.
Claims (1)
域、ベース領域、及びコレクタ領域と、前記ベー
ス領域からの空乏層が延在する範囲内の前記コレ
クタ領域の所定部位に選択的に形成された前記コ
レクタ領域と逆導電型の不純物領域と、該不純物
領域と前記コレクタ領域を同電位にならしめる電
気的接続手段と、該不純物領域と前記ベース領域
間の前記コレクタ領域の表面部分に前記ベース領
域と所定間隔で離間して形成された前記コレクタ
領域と同導電型で且つ前記コレクタ領域よりも高
い不純物濃度の高不純物領域とを具備し、前記ベ
ース領域と前記逆導電型の不純物領域間の耐圧
が、前記ベース領域と前記コレクタ領域間の耐圧
及び前記ベース領域と前記高不純物領域間の耐圧
よりも小さくなるように、前記コレクタ領域の不
純物濃度、前記高不純物領域の不純物濃度、前記
ベース領域と前記高不純物濃度領域間の間隔及び
前記ベース領域と前記不純物濃度領域間の間隔を
設定したことを特徴とする半導体装置。1. An emitter region, a base region, and a collector region constituting a junction transistor, and a region opposite to the collector region selectively formed at a predetermined portion of the collector region within a range where a depletion layer extends from the base region. a conductive type impurity region, an electrical connection means for bringing the impurity region and the collector region to the same potential, and a surface portion of the collector region between the impurity region and the base region and spaced apart from the base region at a predetermined distance. a highly impurity region having the same conductivity type as the collector region and having a higher impurity concentration than the collector region, the withstand voltage between the base region and the impurity region of the opposite conductivity type being higher than the base region; and the impurity concentration of the collector region, the impurity concentration of the high impurity region, and the base region and the high impurity concentration region so that the breakdown voltage between the base region and the high impurity region is lower than the breakdown voltage between the base region and the high impurity region. A semiconductor device characterized in that a distance between the base region and the impurity concentration region is set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001980A JPS5734363A (en) | 1980-08-11 | 1980-08-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001980A JPS5734363A (en) | 1980-08-11 | 1980-08-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5734363A JPS5734363A (en) | 1982-02-24 |
| JPS6348192B2 true JPS6348192B2 (en) | 1988-09-28 |
Family
ID=14525055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11001980A Granted JPS5734363A (en) | 1980-08-11 | 1980-08-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5734363A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60226176A (en) * | 1984-04-25 | 1985-11-11 | Matsushita Electronics Corp | Semiconductor device |
| JPS62106663A (en) * | 1985-11-02 | 1987-05-18 | Matsushita Electronics Corp | Semiconductor device |
| JPH07109041B2 (en) * | 1986-09-04 | 1995-11-22 | 東レ株式会社 | Acrylic composite fiber assembly having excellent crimping properties and level dyeing property, and method for producing the same |
| JPH01104826A (en) * | 1987-10-13 | 1989-04-21 | Toray Ind Inc | Novel acrylic conjugated fiber of specific crimp properties |
| JPH01104825A (en) * | 1987-10-13 | 1989-04-21 | Toray Ind Inc | Production of acrylic conjugated fiber of excellent crimp properties |
| JPH01104828A (en) * | 1987-10-13 | 1989-04-21 | Toray Ind Inc | Acrylic modified cross-section fiber |
| JPH0672326B2 (en) * | 1988-03-04 | 1994-09-14 | 東レ株式会社 | Method for producing acrylic conjugate fiber having excellent crimp developability |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159883A (en) * | 1978-06-08 | 1979-12-18 | Toshiba Corp | Semiconductor device |
-
1980
- 1980-08-11 JP JP11001980A patent/JPS5734363A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54159883A (en) * | 1978-06-08 | 1979-12-18 | Toshiba Corp | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5734363A (en) | 1982-02-24 |
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