JPH06204372A - Power transistor - Google Patents

Abstract

PURPOSE:To lessen a power transistor in collector resistance, base resistance, and saturation voltage by a method wherein an emitter region is separated into emitter subregions which are electrically independent of each other. CONSTITUTION:Collector regions 24 and 25 and base regions 26 and 27 are formed on a semiconductor substrate 21, and emitter regions 28 and 29 are formed in the base regions 26 and 27. The emitter regions 28 and 29 are formed through such a manner that a conventional emitter region is separated into the emitter regions 28 and 29 electrically isolated from each other, and the base regions 26 and 27 are provided through the same manner with the emitter regions. That is, a first transistor composed of the emitter region 28, the base region 26, and the collector region 24 and a second transistor composed of the emitter region 29, the base region 27, and the collector region 25 are formed.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to the structure of power transistors.

[0002]

2. Description of the Related Art Generally, a power transistor formed in a semiconductor integrated circuit (IC) has a large emitter area in order to reduce a saturation voltage V _CE (sat) when a large current flows.

A conventional example will be described with reference to FIGS. 4 is a cross-sectional view of the power transistor, FIG. 5 is a plan view of the power transistor, and FIG. 6 is an output static characteristic diagram of the power transistor.

4 and 5, 1 is a P-type semiconductor substrate
Board, 2 is N⁺Type buried layer, 3 is a P type isolation region, 4 is
N^- Type collector region, 5 is a P type base region, 6 is N⁺
Type emitter region, 7 is N⁺Mold collector extraction area,
8 is an insulating layer, 9 is a collector electrode, 10 is a base electrode, 1
1 is an emitter electrode.

Although reference numeral 12 is a part of the N ⁻ type epitaxial layer formed on the semiconductor substrate 1, the semiconductor substrate 1 will be described here as including the epitaxial layer 12.

FIG. 5 is a plan view of FIG. 4, but the insulating film 8 is removed and the reference numeral is given for convenience of description.

[0007]

However, according to the above conventional example, as shown in FIG. 4, the resistance from the emitter electrode 11 to the collector electrode 9 is R ₅ + R ₂ + R ₁ , and R ₅
+ R ₃ + R ₄ next, especially in the buried layer 2 collector resistor R
₂ and R ₃ are large, and the base resistance R _B from the base electrode 10 to the emitter region 6 is large, so that the saturation voltage V _CE (sat) becomes large as shown in FIG. .

[0008]

In a power transistor in which a collector region and a base region are formed in a semiconductor substrate and an emitter region is formed in the base region, the emitter regions are electrically isolated from each other. It is divided into a plurality of emitter regions.

[0009]

This power transistor has a saturation voltage V _CE (s
at) is reduced.

[0010]

EXAMPLES Next, examples of the power transistor according to the present invention will be described. 1, 2, and 3 are a cross-sectional view, a plan view, and an output static characteristic diagram of a power transistor, respectively.

1 and 2, 21 is a P-type semiconductor substrate, 22 is an N ⁺ -type buried layer, 23 is a P-type isolation region, and 24 and 25 are N ⁻ -type collector regions, respectively.
6 and 27 are P-type base regions, and 28 and 29 are
Each of the emitter regions, 30, 31, 32 is an N ⁺ -type collector extraction region, 33 is an insulating layer such as an oxide film, 34, 35, 36 are collector electrodes, 37, respectively.
Reference numeral 38 is a base electrode, and 39 and 40 are emitter electrodes.

Although 41 is a part of the N type epitaxial layer formed on the semiconductor substrate 21, the semiconductor substrate 21 will be described here as including the epitaxial layer 41.

FIG. 2 is a plan view of FIG. 1, but the insulating film 33 is removed for convenience of explanation and reference numerals are given.

Here, the emitter regions 28 and 29 divide the above-mentioned conventional emitter region 6 electrically independently of each other, and the base regions 26 and 27 are also divided from the conventional base region 5 accordingly. The collector extraction region 31 is divided into the emitter regions 28 and 29 (base region 2).
6 and 27) are additionally formed.

That is, the conventional emitter region 6 is divided into a first transistor including an emitter region 28, a base region 26 and a collector region 24, and an emitter region 2.
A plurality of second transistors including the base region 27, the base region 27, and the collector region 25 are formed. Although not shown, the emitter electrodes 39 and 40 and the base electrode 3 are formed.
7, 38 and the collector electrodes 35, 36 are electrically connected to each other to form one power transistor as a whole.

According to the above construction, in the first transistor as shown in FIG. 1, the resistances from the emitter electrode 39 to the collector electrodes 34, 35 are R ₅₁ + R ₂₁ + R ₁₁ and R ₅₁ + R ₃₁ + R ₄₁ , respectively. In particular, the collector resistances R ₂₁ and R ₃₁ of the buried layer 22 are halved in comparison with the conventional resistances R ₂ and R ₃ described above, and the resistance value becomes small.
Further, the base resistance R _B1 from the base electrode 37 to the emitter region 28 is also dimensionally compared, and the resistance value is reduced to half that of the above-described conventional base resistance R _B.

The second transistor similarly has a collector resistance R.
₂₂ and R ₃₂ become smaller, and the base resistance R _B2 also becomes smaller.

FIG. 3 is an output static characteristic diagram of the power transistor obtained in FIGS. Compared with FIG. 6, the value of the saturation voltage V _CE (sat) is smaller.

In the above description, the emitter region is not limited to two divisions, the conductivity type in the emitter, base region, etc. is not limited to that shown in the embodiment, and it is not a power transistor in the IC but a single unit. Good.

[0020]

As described above, the power transistor according to the present invention is a power transistor in which a collector region and a base region are formed in a semiconductor substrate, and an emitter region is formed in the base region. Since the regions are electrically isolated from each other and divided into a plurality of emitter regions, the collector resistance and the base resistance are reduced, and the saturation voltage of the transistor can be reduced.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a power transistor.

FIG. 2 is a plan view of a power transistor.

FIG. 3 is an output static characteristic diagram of a power transistor.

FIG. 4 is a cross-sectional view of a power transistor showing a conventional example.

FIG. 5 is a plan view of a power transistor showing a conventional example.

FIG. 6 shows an output static characteristic diagram of a power transistor, showing a conventional example.

[Explanation of symbols]

21 substrate 22 buried layer 24, 25 collector region 26, 27 base region 28, 29 emitter region 30, 31, 32 collector extraction region R _B1 , R _B2 base resistance R ₂₁ , R ₃₁ , R ₂₂ , R ₃₂ collector resistance

Claims (1)

[Claims] 1. A power transistor comprising a semiconductor substrate having a collector region and a base region formed therein, and an emitter region formed in the base region, wherein the emitter regions are electrically isolated from each other. A power transistor characterized by being divided into