JPH0337738B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a semiconductor integrated circuit that eliminates thyristor parasitic effects.

(b) Prior Art Conventionally, as shown in FIG. 1, a P-type semiconductor substrate 1, an N-type epitaxial layer 2 laminated thereon, and the epitaxial layer 2 are separated into island regions 3 and 4. A semiconductor integrated structure comprising a P ⁺ type isolation region 5 , a P ⁺ type diffusion region 6 diffused on the surface of the first island region 3 , and an N ⁺ type diffusion region 7 diffused on the surface of the second island region 4 In the circuit, there is a possibility that a thyristor parasitic effect may occur between both diffusion regions 6 and 7.
In other words, the P ⁺ type diffusion region 6 is the emitter or collector region of a lateral transistor biased to a high potential, or the P type diffused resistor, and the N ⁺ type diffusion region 7 is a tunnel region or epitaxial region biased to a low potential. This is the case with a resistor terminal. In these cases, a PNPN self-bias parasitic thyristor is formed by the P ⁺ type diffusion region 6, the N type first island region 3, the P ⁺ type isolation region 5, and the N type second island region 4. However, the parasitic thyristor turns on and a parasitic current shown by the arrow flows. FIG. 2 is an equivalent circuit diagram of a parasitic thyristor, where Tr ₁ is a PNP transistor formed by a P ⁺ type diffusion region 6, an N type first island region 3, and a P ⁺ type isolation region 5; ₂ is an NPN transistor formed of an N-type first island region 3, a P ⁺ -type isolation region 5, and an N-type second island region 4.

Such a parasitic thyristor effect occurs when the power supply terminal is inserted into the socket before the ground terminal that is in contact with the semiconductor substrate 1, and the substrate potential rises and a current of several 100 mA is generated even if the ground terminal is inserted into the socket. Keep flowing.

(c) Object of the Invention The present invention has been made in view of the above, and provides a semiconductor integrated circuit that completely prevents the conventional thyristor parasitic effect.

(D) Structure of the Invention As shown in FIG. 3, the semiconductor integrated circuit according to the present invention includes a P-type semiconductor substrate 11, an N-type epitaxial layer 12 laminated thereon, and an epitaxial layer 12, respectively. A P ⁺ type isolation region 16 that provides PN separation into island regions 13, 14, and 15, a P ⁺ type diffusion region 17 provided on the surface of the first island region 13, and an N ⁺ type provided on the surface of the second island region 14. It consists of a diffusion region 18 and a resistance region 19 provided in the third island region 15, which is a feature of the present invention, and the resistance region 19 is formed between the P ⁺ type diffusion region 17 and the first island region 13 or ^the It is connected between the mold separation region 16 and the second island region 14 .

(E) Example In this example, as shown in FIG. 14 and 15, a P-type isolation region 16 for PN isolation by isolation diffusion, and an emitter or collector region of a lateral transistor provided on the surface of the first island region 13 or a diffused resistor.
The resistance region 19, which is a feature of the present invention, includes a P ⁺ type diffusion region 17 and an N ⁺ type diffusion region 18 such as a tunnel region provided on the surface of the second island region 14.
It is formed in the island region 15 of . Note that each of the above-mentioned regions is sequentially formed by selective diffusion of desired impurities.

The resistance region 19 is formed in an independent third island region 15, and specifically, the epitaxial layer 12 is used as it is, the resistor region 19 is formed in the third island region 15 by base diffusion, or the third island region 15 is formed by ion implantation. Some are formed on the surface of the island region 15,
The present invention can achieve any of the objectives. The resistance value is
Depending on the magnitude of the base current of Tr ₁ or Tr ₂ , it is selected between approximately 10KΩ and 100KΩ, and is designed to have a voltage drop of approximately 0.3V. The A and B terminals of the resistance region 19 are the A 1 and B 1 terminals between the P ⁺ type diffusion region 17 and the first island region 13 or the A ₁ and B ₁ terminals between the P ⁺ type isolation region 16 and the second island region 14 . A ₂ , B ₂ between
Either one of the terminals or both terminals may be connected to each other. Note that when connecting the A and B terminals of the resistance region 19 to the A ₁ and B ₁ terminals, the first island region 13 is used in a floating state. This is to prevent the resistance region 19 from becoming a resistance in the equivalent circuit.

According to the above configuration, within the first island area 13
P ⁺ type diffusion region 17, N in first island region 13
type epitaxial layer 12 and P ⁺ type isolation region 16 correspond to the emitter-base and collector regions of a PNP type lateral transistor Tr ₁ ;
Further, the N-type epitaxial layer 12 in the first island region 13, the P ⁺ type isolation region 16, and the N-type epitaxial layer 12 in the second island region 14,
Collector of NPN type lateral transistor Tr ₂ ,
Corresponds to the base and emitter areas. Also the terminal
As can be seen from FIG. 3, A ₁ and B ₁ correspond to the emitter and base regions of Tr ₁ , and terminals A ₂ and
B ₂ corresponds to the base and emitter region of Tr ₂ . Here, terminals A and B are connected to either one or both of terminals A ₁ and B ₁ and terminals A ₂ and B ₂ , so the resistance R between terminals A and B is the emitter base of Tr _1. (corresponds to Figure 4), between the base and emitter of Tr ₂ (corresponds to Figure 5), or
Between the emitter and base of Tr ₁ and between the base and base of Tr ₂ .
The configuration is such that it is connected between the emitters (corresponding to FIG. 6).

_The equivalent circuit diagrams of such a structure are shown in FIGS. 4, 5, and 6. Tr ₁ and _{Tr 2 have} the same configuration as in FIG.
A resistor R is connected between the base and emitter of. As a result, the voltage between the base and emitter of either or both of Tr ₁ and Tr ₂ is maintained at approximately 0.3V, thereby preventing the parasitic thyristor from turning on.

(F) Effects According to the present invention, the parasitic thyristor effect can be easily prevented using only the resistance region 19, contributing to an improvement in the degree of integration of semiconductor integrated circuits. Furthermore, since this can be done using only the resistance region 19, its pattern arrangement is also easy.
Furthermore, it has many advantages such as being able to be realized without adding a new manufacturing process.

[Brief explanation of drawings]

FIG. 1 is a sectional view explaining the conventional example, FIG. 2 is an equivalent circuit diagram of the conventional example, FIG. 3 is a sectional view explaining the present invention, and FIGS. 4 to 6 are equivalent circuit diagrams of the present invention. be. 11 is a P-type semiconductor substrate, 12 is an N-type epitaxial layer, 13, 14, and 15 are island regions, and 16 is a P ⁺
type separation region, 17 is P ⁺ type diffusion region, 18 is
The N ⁺ type diffusion region 19 is a resistance region.

Claims (1)

[Claims] 1. A semiconductor substrate of one conductivity type, an epitaxial layer of an opposite conductivity type provided on the substrate, and a separation region of one conductivity type that separates the epitaxial layer into a plurality of island regions. , between a diffusion region of one conductivity type on the surface of the first island region biased at a high potential and an adjacent diffusion region of the opposite conductivity type on the surface of the second island region biased at a low potential; A first parasitic transistor is formed in which the epitaxial layer in the first island region, the epitaxial layer in the first island region, and the isolation region serve as an emitter, a base, and a collector, and the epitaxial layer in the first island region, the isolation region , in a semiconductor integrated circuit in which a second parasitic transistor is configured in which the diffusion region of the opposite conductivity type serves as a collector, a base, and an emitter, and a thyristor parasitic effect is produced, a resistance region is provided in the third island region; A semiconductor integrated circuit characterized in that a potential is connected between the base of the first parasitic transistor or between the low potential and the base of the second parasitic transistor.