JPH0453104B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a semiconductor capacitive coupling element used for coupling between amplifiers in an integrated circuit, and particularly to a semiconductor capacitive coupling element whose parasitic capacitance is reduced.

(b) Conventional technology When coupling two circuits, such as between stages of a conventional amplifier, if it is difficult to directly connect the two circuits due to problems such as bias differences, coupling is done using capacitance. There are many. When this is done in an integrated circuit, the MOS capacitor described in, for example, Japanese Unexamined Patent Publication No. 59-28368 is often used.

Figure 4 shows such MOS capacitance, where 1 is P
type semiconductor substrate, 2 is an N ^- type epitaxial layer, 3
4 is an N ⁺ type buried layer buried on the substrate 1, 4 is a P ⁺ type isolation region that penetrates the epitaxial layer 2, 5 is an island region separated into islands by the isolation region 4, and 6 is an island region. 5 is an N ⁺ type first region formed on the surface of island region 5; 7 is an insulating film covering the surface of island region 5; 8 is a first electrode in ohmic contact with first region 6; This is a second electrode provided on region 6. Then, the first electrode 8 is connected to the input terminal A, the second electrode 9 is connected to the output terminal B, and the MOS capacitor formed with the first region 6 as one electrode and the second electrode 9 as the other electrode is used as a coupling capacitance. It is what you use.

FIG. 5 shows an equivalent circuit of such a device, consisting of an input terminal A, an output terminal B, and the coupling capacitor C _C connected between the input terminal A and the output terminal B. However, when formed in an integrated circuit in this way, the first
A parasitic capacitance C _S0 is formed between the region 6 and the substrate 1,
This parasitic capacitance C _S0 is equivalently interposed between the input terminal A and the ground terminal GND.

(c) Problems to be solved by the invention However, in conventional devices, this parasitic capacitance
Since C _S0 is large, the signal current (AC component) applied to input terminal A flows to board 1, which has the disadvantage that the level of the signal to output terminal B is attenuated more than the input level. Ta.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned drawbacks, and includes a P-type first region 16 formed on the surface of the island region 15 and a first
A second region 17 of N ⁺ type, which serves as one electrode of the MOS capacitor formed on the surface of the region 16, is provided, a ground potential is applied to the first region 16 via a resistor R, and a shot is applied to the island region 15. A feature is that a power supply potential is applied via a key diode Di.

(E) Effect According to the present invention, the input terminal A and the ground terminal GND
, a junction capacitance C _S1 between the second region 17 and the first region 16 , a junction capacitance C _S2 between the first region 16 and the island region 15 , and a junction capacitance C _S3 between the island region 15 and the substrate 11 .
, and both connection points C and D are not grounded in an AC manner, so that the overall parasitic capacitance C _S0 with respect to the input signal (AC component) becomes extremely small.

(f) Examples The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a first embodiment according to the present invention, 1
1 is a P-type semiconductor substrate, 12 is an N ^- type epitaxial layer, 13 is an N ⁺ type buried layer formed on the surface of the substrate 11, and 14 is a P ⁺ layer that penetrates the epitaxial layer 12.
A type isolation region, 15 is an island region electrically isolated by the isolation region 14, 16 is a P-type first region formed on the surface of the island region 15, 17 is a second region formed on the surface of the first region 16, 18 19 and 20 are first and second electrodes in ohmic contact with the first region 16 and second region 17, respectively; 21 is an insulating film 18 covering the second region 17; The third electrode 22 provided in the sandwich is a fourth electrode that makes a shot key contact with the island region 15. The first electrode 19 is connected to the ground terminal GND via the resistor R, the second electrode 20 is connected to the input terminal A, the third electrode 21 is connected to the output terminal B, and the fourth electrode 22 is connected to the power supply terminal V _CC , respectively. A MOS capacitor formed with the second region 17 as one electrode and the third electrode 21 as the other electrode is used as a coupling capacitor. A ground potential is applied to the first region 16 via a resistor R, and a power supply potential is applied to the island region 15 via a Schottky diode Di which uses itself as an anode and the fourth electrode 22 as a cathode. .

FIG. 2 is an equivalent circuit diagram of such a device, showing input terminal A, output terminal B, and input terminal A and output terminal B.
It consists of the coupling capacitance C _C connected between. Between the second region 17 and the substrate 11, there are a junction capacitance C _S1 between the second region 17 and the first region 16, a junction capacitance C S2 between the first region 16 and the island region 15, and a junction capacitance C _S2 between the first region 16 and the island region 15.
A junction capacitance C _S3 is formed between the input terminal A and the substrate 11, and these are connected in series between the input terminal A and the ground terminal GND. Since the junction point C between the junction capacitances C _S1 and C _S2 is connected to the ground terminal GND via the resistor R ₁ , it is equal to the ground potential in terms of direct current, but is not grounded in terms of alternating current. Furthermore, at the connection point D between the junction capacitances C _S2 and C _C3 , if the circuit network is considered as an equivalently large capacitance, the power supply terminal V _CC itself is grounded in terms of AC, but the Schottky diode Di becomes reverse biased. Since it is connected like this, it is not grounded in terms of AC.

FIG. 3 shows a plan view of a second embodiment according to the present invention, which has a structure in which the first region 16 is extended to form a resistor portion 16a, and one end of the resistor portion 16a is connected to the isolation region 14. Since a ground potential is normally applied to the isolation region 14, the equivalent circuit shown in FIG. 2 is constructed by setting the resistance R _A of the resistance section 16a to a resistance R.

The most characteristic feature of the present invention is that a second region 17 is formed on the surface of the first region 16 and serves as one electrode of the MOS capacitor.
, and junction capacitances C _S1 , C _S2 , and C _S3 are connected in series between the second region 17 and the substrate 11 . and the first area 16 and the second area 1
PN junction with 7, first region 16 and island region 15
A ground potential is applied to the first region 16 as a means for the PN junction between the island region 15 and the substrate 11 to form junction capacitances C _S1 , C _S2 , and C _S3 , respectively.
A power supply potential is applied to each of the connection points C,
Resistors R and D are used as a means to prevent both D from being grounded in an AC manner, that is, to prevent the input signal (AC component) from flowing to the ground terminal GND or power supply terminal V _CC via the junction capacitance C _S1 or C _S2 . A Schottky diode Di is provided. According to this structure, the total parasitic capacitance C _S0 for the input signal (AC component) is the junction capacitance
This is the total capacitance of C _S1 , C _S2 , and C _S3 connected in series, and the junction capacitance C _S2 and C _S3 have the largest potential difference in the integrated circuit, that is, the power supply potential and the ground potential, applied across them. Since the capacitance value is
becomes a very small value. Therefore, circuit coupling can be performed without deteriorating the input signal (AC component).

It is also possible to use a resistor instead of the Schottky diode Di, but if this resistor is formed separately, the chip area increases and the island area 15
Even if such a parasitic resistance is used, in order to increase its value, the first region 16 and the fourth electrode 22 must be separated by a considerable distance, which also results in an increase in the chip area. In contrast, in the present invention, since it is sufficient to provide only the fourth electrode 22 for Schottky junction, the pattern area can be approximately equal to that of a conventional MOS capacitor.

(g) Effects of the invention As explained above, according to the present invention, parasitic capacitance
Since C _S0 can be made to a very small value,
This has the advantage that good circuit coupling can be achieved without deteriorating the input signal (AC component). Further, according to the second embodiment, there is no need to separately form the resistor R, so there is an advantage that high integration can be achieved. Furthermore, compared to the method of using a resistor instead of the Schottky diode Di, this method has the advantage that the pattern area can be reduced. Furthermore, it has the advantage that elements such as resistors for other purposes can be formed within the same island region.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of the present invention, FIG. 3 is a plan view showing a second embodiment of the present invention, and FIGS. 4 and 5 are a sectional view and an equivalent circuit diagram for explaining the conventional example, respectively. It is. Explanation of main figure numbers, 1 and 11 are P-type semiconductor substrates,
5 and 15 are island areas, 16 is the first area, and 17 is the second area.
Areas 19, 20, 21, and 22 are the first,
These are the second, third, and fourth electrodes.

Claims (1)

[Claims] 1. One island region electrically isolated by a separation region of one conductivity type, a first region of one conductivity type formed on the surface of the island region, and an opposite region formed on the surface of the first region. a conductive type second region, an insulating film covering the surface of the island region, an electrode provided on the second region with the insulating film sandwiched therebetween, an electrode in contact with the second region, and a resistor in the first region. A semiconductor capacitive coupling element comprising means for applying a ground potential through the island region and means for applying a power supply potential to the island region through a Schottky diode, and generating parasitic capacitance in each PN junction. . 2. The semiconductor capacitive coupling element according to claim 1, wherein the resistor is constructed using the first region.