JP2752832B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a switched capacitor filter (hereinafter referred to as SC).
F), C / R type A / D converter, C / R type D
The present invention relates to a semiconductor integrated circuit device including a capacitance element such as an / A converter.

[0002]

2. Description of the Related Art A semiconductor integrated circuit device is an aggregate of transistor elements and capacitance elements. It is also an aggregate of functional blocks including them. Here, an SCF as an example of a semiconductor integrated circuit device will be described.

FIG. 3 is a plan view and a sectional view of a conventional semiconductor integrated circuit device in which a feedback capacitance element C2 and an input capacitance element C1 used in the SCF shown in the circuit diagram of FIG. (A) and (B).

An N-type well region 8 is formed on a P-type semiconductor substrate 9, and a P-type polysilicon layer 2 is formed on an upper surface of the N-type well region 8 via an insulating film 17 made of a silicon oxide film.
Numeral 12 is formed as a lower electrode of the capacitive element, and a plurality of unit upper electrodes 1 are formed thereon via an insulating film 7 as a dielectric. In the input capacitance element C1, the overlapping portion of the four unit upper electrodes 1 and the lower electrode 2 connected by the upper electrode wiring 3 in the extraction section 6 becomes a capacitance. That is, the unit capacitance elements C ₀ consists of overlapping portions of the unit upper electrode 1 and the lower electrode 2 is a capacitive element connected to the four parallel. Similarly, the feedback capacitor C2 is connected two unit upper electrode 1 from being connected by the upper electrode wiring 13, the unit capacitance element C ₀ is the two parallel composed of overlap between the lower electrode 12 This is a capacitive element.

The N-type well region 8 has a ground potential (0 V) due to the well electrode wiring 11 connected at the extraction portion 10. On the other hand, the polysilicon layer 2 as the lower electrode of the input capacitance element C1 is connected to the input signal terminal by the lower electrode wiring 4 connected at the extraction portion 5 (FIG. 4), and the polysilicon as the lower electrode of the feedback capacitance element C2 is formed. The layer 12 is connected to the output signal terminal by the lower electrode wiring 14 connected at the extraction part 5 (FIG. 4). As shown in FIG. 4, the upper electrodes of the input capacitance element C1 and the feedback capacitance element C2 are switched by wirings 3 and 13, respectively.
That is, it is connected to one input terminal of the AMP through a semiconductor switch formed by a transistor formed in the semiconductor integrated circuit device. In FIG. 4, a white triangle (▽) indicates a reference voltage terminal.

[0006]

In the above-mentioned conventional semiconductor integrated circuit device, as shown in FIG. 3B, an insulating film 17 between the lower electrodes 2 and 12 and the N-type well region 8 is formed as a dielectric film. MOS capacitors C5 and C6 are formed as parasitic capacitances, respectively. Therefore, conventionally, the N-type well region 8 is connected to a low-voltage power supply (for example, a ground potential) in order to prevent noise from flowing from the N-type well region 8 due to the parasitic capacitance. However, the parasitic capacitance C5 and the parasitic capacitance C6 (for example, about 0.02 pF when the area of the lower electrode is 500 μm ² ) are formed on the same N well region, and the resistor R1 exists in the well region. Resistance R
1 (for example, when the distance between the lower electrodes is 10 μm, 5 k
Ω), there is a drawback that noise from the output side goes around to the input side and the noise characteristics are deteriorated.

[0007]

A feature of the present invention is that in a semiconductor integrated circuit device having a functional block including a plurality of capacitive elements, first and second capacitive elements having a common connection point in the functional block. Is a semiconductor integrated circuit device formed on the first and second well regions of opposite conductivity type separated from each other by a semiconductor substrate of one conductivity type. The first and second capacitors can be configured by connecting unit capacitors in parallel.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIGS. 1A and 1B as an embodiment of the present invention relating to the circuit diagram of FIG. 4 which is an example of a semiconductor integrated circuit device,
It is the top view and sectional drawing of the semiconductor integrated circuit device in which the input capacitance element C1 and the feedback capacitance element C2 of SCF are comprised. Note that in FIGS. 1A and 1B, FIGS.
Parts that are the same as or similar to (B) are denoted by the same reference numerals.

First and second N-well regions 18 and 28 are formed on a P-type semiconductor substrate 9, respectively, and the upper surfaces of these N-type well regions 18 and 28 are formed with an insulating film 17 made of a silicon oxide film interposed therebetween. Formed polysilicon layers 2 and 12 are formed as lower electrodes of the capacitive element, and a plurality of unit upper electrodes 1 made of polysilicon are formed thereon via an insulating film 7 as a dielectric. Input capacitance element C
Reference numeral 1 denotes a take-out portion 6 in which an overlapping portion of the four unit upper electrodes 1 and the lower electrode 2 connected by the upper electrode wiring 3 serves as a capacitor. That is, the unit capacitance elements C ₀ consists of overlapping portions of the unit upper electrode 1 and the lower electrode 2 is a capacitive element connected to the four parallel. Similarly, the feedback capacitance element C2
Since the two unit upper electrodes 1 are connected by the upper electrode wiring 13, this is a capacitance element in which two unit capacitance elements C _{0, which} are configured to overlap the lower electrode 12, are connected in parallel.

Each of the N-type well regions 18 and 28 has
The ground potential (0 V) is attained by the well electrode wiring 11 connected by the extraction unit 10. On the other hand, the input capacitance element C
The polysilicon layer 2 serving as a lower electrode of
The lower electrode wiring 4 connected to the input signal terminal (FIG. 4) and the polysilicon layer 12 as the lower electrode of the feedback capacitor C2 is connected to the output signal terminal by the lower electrode wiring 14 connected at the extraction portion 5. Connected (FIG. 4). As shown in FIG. 4, the upper electrodes of the input capacitance element C1 and the feedback capacitance element C2 are switched by their wirings 3 and 13, respectively, that is, one of the AMPs through a semiconductor switch formed by a transistor formed in the semiconductor integrated circuit device. Connected to input terminal. Similarly to FIG. 3, the lower electrode 2 of the input capacitor C1 and the N-type well region 1
8, a parasitic capacitance C5 (for example, about 0.02 pF when the area of the lower electrode is 500 μm ² ) is formed between the lower electrode 12 and the N-type well region 28 of the feedback capacitance element C2. The parasitic capacitance C6 (for example, when the area of the lower electrode is 50
In the case of 0 μm ² , about 0.02 pF) is formed.

However, in the present invention, the input capacitance element C
N-type well region 18 for shielding lower electrode 2 from P-type semiconductor substrate (sub-substrate) 9 and feedback capacitor C
The second lower electrode 12 is separated from the N-type well region 28 for shielding the lower electrode 12 from the P-type semiconductor substrate (sub-substrate) 9. By separating the N-type well region for shielding in this manner, the parasitic capacitance C5 and the parasitic capacitance C6 do not exist on the same well region, so that they are not directly connected by the parasitic resistance. The noise on the output side does not enter the input side, and the noise characteristics are improved.

Although the SCF has been described above as an example, the present invention is not limited to this, and similar effects can be obtained with a C / R A / D converter, a C / R D / A converter, and the like. Can be

FIGS. 2A and 2B are a plan view and a sectional view showing another embodiment of the present invention of a semiconductor integrated circuit device in which an input capacitance element C1 and a feedback capacitance element C2 of an SCF are formed. It is. 2A and 2B, FIG.
Parts that are the same as or similar to (A) and (B) are denoted by the same reference numerals. A substrate (sub-substrate) electrode lead-out portion 15 is provided in a portion of the P-type semiconductor substrate (sub-substrate) 9 between the N-well region 18 below the input capacitance element C1 and the N-well region 28 below the feedback capacitance element C2. Board electrode wiring 1 connected to
6 to the ground terminal. In this case, as shown in FIG. 2B, even if the parasitic capacitances C7 and C8 occur, the substrate portion between the well regions is connected to a low-impedance power supply by the electrode extraction portion 15, so that the parasitic capacitances C7 and C8 The output noise does not sneak to the input through this, and the noise characteristics can be further improved as compared with the embodiment of FIG.

[0014]

As described above, according to the present invention, the N-type well region 18 for shielding the lower electrode 2 of the input capacitance element C1 from the P-type semiconductor substrate 9 and the P-type lower electrode 12 of the feedback capacitance element C2 are formed. By separating the semiconductor substrate 9 from the N-type well region 28 for shielding, the system that passes through the parasitic capacitances C5 and C6 and the parasitic resistance R1 shown in the circuit diagram of FIG. 4 can be eliminated. Therefore, the output noise does not reach the input, and the noise characteristics are improved.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing one embodiment of the present invention, wherein FIG. 1A is a plan view, and FIG.

FIGS. 2A and 2B are diagrams showing another embodiment of the present invention, in which FIG. 2A is a plan view, and FIG.

FIG. 3 is a diagram showing a conventional technique, wherein (A) is a plan view,
(B) is a sectional view of the AA part of (A).

FIG. 4 is a circuit diagram of an SCF.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Upper electrode 2, 12 Lower electrode 3, 13 Wiring of upper electrode 4, 14 Wiring of lower electrode 5 Lower electrode take-out part 6 Upper electrode take-out part 7 Insulating film as dielectric film of capacitive element 8, 18, 28 N type Well region 9 P-type semiconductor substrate (sub-substrate) 10 Well electrode lead-out part 11 Well electrode wiring 15 Substrate electrode lead-out part 16 Substrate electrode wiring 17 Insulating film

Claims (2)

(57) [Claims] In a semiconductor integrated circuit device having a functional block including a plurality of capacitive elements, first and second capacitive elements having a common connection point in the functional block are disposed on a semiconductor substrate of one conductivity type. The first of the separated reverse conductivity type
And a semiconductor integrated circuit device formed on the second well region. 2. The semiconductor integrated circuit device according to claim 1, wherein each of said first and second capacitance elements is configured by connecting unit capacitance elements in parallel.