JPH06103735B2 - Semiconductor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a MOS type capacitance element.

[Conventional technology]

It has been conventionally known that the capacitance value of a MOS type capacitive element changes depending on the potential difference between the two poles. Therefore, the MOS type capacitance element could not be used as a capacitance element such as a switched capacitor filter in which it is difficult to change the capacitance. Therefore,
As shown in FIG. 4, the conventional capacitive element has a semiconductor substrate 14
An insulating film 15 is provided on the insulating film 15, and a polycrystalline silicon layer or an aluminum layer is deposited on the insulating film 15 and selectively etched to provide a lower electrode 16. Next, an interlayer insulating film 17 is deposited on the surface including the electrode 16, a polycrystalline silicon layer or an aluminum layer is deposited on the interlayer insulating film 17, and the layer is selectively etched to form an electrode through the interlayer insulating film 17. Upper electrode facing 16
It was constructed by providing 18.

[Problems to be Solved by the Invention]

In the above-described conventional semiconductor integrated circuit, since the capacitive element is formed by using the interlayer insulating film interposed between the opposing lower layer electrode and upper layer electrode as a dielectric, the interlayer insulating film can be formed thin. This is difficult, and as a result, there is a problem that the capacitance is reduced, or the area for forming electrodes for increasing the capacitance is increased and the integration degree is reduced.

[Means for Solving the Problems]

In the semiconductor integrated circuit of the present invention, the first and second wells of opposite conductivity type provided on the one conductivity type semiconductor substrate and the regions of the first and second wells are provided via a gate insulating film, respectively. First and second gate electrodes, and the first and second gate electrodes
First conductivity type first and second diffusion regions provided in each of the first and second wells in alignment with the gate electrode of
A wiring that connects the first gate electrode to the second diffusion region and the second well; and a wiring that connects the second gate electrode to the first diffusion region and the first well. It has a capacitive element in which MOS capacitive elements having substantially the same shape are connected in parallel in opposite directions.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of the embodiment shown in FIG.

As shown in FIGS. 1 and 2, the first N-type well 2a and the second N-type well 2b are selectively provided on the main surface of the P-type silicon substrate 1, and the N-type well 2a, The gate insulating film 3 is provided on the surface including 2b. Next, the first gate electrode 4a is selectively provided on the gate insulating film 3 on the region of the N-type well 2a, and the second gate electrode 4a is formed on the gate insulating film 3 on the region of the N-type well 2b.
The respective gate electrodes 4b are provided. Next, the gate electrode 4a
The first P-type diffusion region 5a is provided in the N-type well 2a in alignment with the above, and the second P-type diffusion region 5b is provided in the N-type well 2b in alignment with the gate electrode 4b. Then, the N ⁺ -type diffusion region 6a and the N-type well 2b for contact N-type well 2a for contact N ⁺
A mold diffusion region 6b is provided. Next, the interlayer insulating film 7 is deposited on the surface including the gate electrodes 4a and 4b, and the contact openings of the gate electrodes 4a and 4b and the P type diffusion regions 5a and 5b and the N ⁺ type diffusion regions 6a and 6b are formed. And a wiring 8 connected to each electrode and region of the opening is provided to connect the first gate electrode 4a and the second P electrode.
The type diffusion region 5b and the second N ⁺ type diffusion region 6b are electrically connected to the terminal 9, and the second gate electrode 4b and the first P type diffusion region are formed.
5a and the first N ⁺ type diffusion region 6a are electrically connected to the terminal 10 to obtain a capacitive element in which MOS type capacitive elements having substantially the same configuration are connected in parallel in opposite directions.

The P-type diffusion regions 5a and 5b may be integrally provided in each N-type well 2a or 2b.

FIG. 3 shows C of the MOS type capacitance element of the semiconductor integrated circuit of the present invention.
It is a -V characteristic view.

As shown in FIG. 3, the CV characteristic 11 of the first MOS-type capacitance element is such that when a positive voltage is applied to the gate electrode 4a, electrons are transferred to the surface of the N-type well 2 through the gate insulating film 3. And the capacitance is only the gate insulating film capacitance C _ox ,
When the applied voltage is lowered and a voltage near the gate threshold voltage is applied to the gate electrode 4a, a depletion region is formed on the surface of the N-type well 2, so that the MOS capacitance is depleted with the gate insulating film capacitance C _ox. The layer capacitance C _D is connected in series and decreases. When the voltage applied to the gate electrode 4a is further lowered, N
An opposite layer is formed on the surface of the mold well 4, and the MOS capacitance is again dominated by the gate insulating film capacitance C _ox .
Further, the CV characteristic 12 of the second MOS type capacitance element having the opposite polarity is a curve obtained by inverting the CV curve of the first MOS type capacitance element centering on the OV point, that is, a curve represented by a broken line. . Therefore, the C-V characteristic 13 of the combined capacitive element is symmetrical with respect to the OV point. Therefore, the combined capacitance value of the MOS type capacitance element is twice, and the fluctuation value due to the bias voltage near the OV point is MO.
This is the same as in the case of one S-type capacitance element, the ratio of the variation value to the capacitance value is reduced, and a MOS-type capacitance element having a small voltage dependence can be obtained.

〔The invention's effect〕

As described above, according to the present invention, the voltage dependency of the capacitance value can be reduced as compared with the related art by forming the capacitance element by connecting the first and second MOS type capacitance elements in parallel in opposite directions. It can be used for high-precision circuits, and has an effect of reducing the cost or improving the degree of integration of a semiconductor integrated circuit having a capacitive element.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of the embodiment shown in FIG. 1, and FIG. 3 is a MOS type semiconductor integrated circuit of the present invention. FIG. 4 is a CV characteristic diagram of the capacitive element, and FIG. 4 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit. 1 ... P-type silicon substrate, 2a, 2b ... N-type well, 3 ... Gate insulating film, 4a, 4b ... Gate electrode, 5a, 5b ... P-type diffusion region,
6a, 6b ... N ⁺ type diffusion region, 7 ... Interlayer insulating film, 8 ... Wiring, 9,1
0 ... Terminal, 11 ... CV characteristic of the first MOS type capacitive element, 12 ...
CV characteristics of second MOS type capacitance element, 13 ... CV characteristics of synthesized capacitance element, 14 ... Semiconductor substrate, 15 ... Insulating film, 16 ...
Electrodes, 17 ... Interlayer insulating film, 18 ... Electrodes.

Claims (1)

[Claims] 1. A first and second wells of opposite conductivity type provided on a semiconductor substrate of one conductivity type, and first and second wells respectively provided on the regions of the first and second wells via a gate insulating film. A second gate electrode; first and second diffusion regions of one conductivity type which are provided in the first and second wells in alignment with the first and second gate electrodes; A wiring connecting the gate electrode to the second diffusion region and the second well, and a wiring connecting the second gate electrode to the first diffusion region and the first well. A semiconductor integrated circuit having a capacitive element in which MOS capacitive elements having the same shape are connected in parallel in mutually opposite directions.