JPH0525743U - Semiconductor device - Google Patents

Abstract

(57) [Summary] [Object] The present invention relates to a semiconductor device, and an object thereof is to provide a semiconductor device in which the parasitic junction capacitance has a small voltage dependence. [Composition] A CM formed on a semiconductor substrate in which a P well and an N well are formed symmetrically and a dielectric layer is formed on the surface.
By utilizing the symmetry of the OS structure and holding the N well at a high potential and the P well at a low potential, the voltage dependence of the parasitic junction capacitance is canceled.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a semiconductor device, and more particularly to improvement of voltage dependence of parasitic capacitance in a MOS capacitor mounted on a semiconductor integrated circuit.

[0002]

[Prior Art]

FIG. 4 is a structural example diagram of a conventional MOS capacitor mounted on a semiconductor integrated circuit, showing a structure by a bipolar process. In the figure, reference numeral 1 denotes a p-type semiconductor substrate, an n-type diffusion layer 2 is formed in the vicinity of the upper part thereof, and an n ⁺ diffusion layer 3 is formed in a part of the vicinity of the upper part of the diffusion layer 2. There is. Reference numeral 4 is a dielectric layer such as SiO ₂ formed on the surfaces of the semiconductor substrate 1, the diffusion layers 3 and 4. Reference numerals 5 and 6 are electrodes made of, for example, Al, the electrode 5 is connected to the dielectric layer 4, and the electrode 6 is connected to the n ⁺ diffusion layer 3 through a hole provided in the dielectric layer 4. There is.

FIG. 3 is an equivalent circuit diagram of FIG. That is, between the electrodes 5, 6 MOS capacitance _{C a b} are formed. Then, the parasitic junction capacitance C _j also exists between the semiconductor substrate 1 and the electrode 6 connected to the diffusion layer 3.

[0004]

[Problems to be solved by the device]

However, the value of the parasitic junction capacitance C _j in such a structure depends on the width of the depletion layer having voltage dependence, and the capacitance value changes relatively greatly in response to changes in the signal level. There are drawbacks.

The present invention has been made in view of such problems, and an object thereof is to provide a semiconductor device in which the parasitic junction capacitance has a small voltage dependency.

[0006]

[Means for Solving the Problems]

According to the present invention, a P-well and an N-well are formed symmetrically and a dielectric layer is formed on the surface of the semiconductor substrate, and an N ⁺ region and a P ⁺ region are diffused in the P-well to form the dielectric layer. through the N ⁺ first electrode to regions facing is formed, the through holes formed in the dielectric layer and the second electrode to the N ⁺ region is connected, it is provided on the dielectric layer was first and MOS which the third electrode is connected to the P ⁺ region through the hole, the P ⁺ region and the N ⁺ region in the N well is formed diffused, P ⁺ region through said dielectric layer A first electrode is formed so as to face with the second electrode, a second electrode is connected to the P ⁺ region through a hole provided in the dielectric layer, and a N electrode is formed through a hole provided in the dielectric layer. ⁺ region third electrode is composed of a second MOS connected to the first electrode and the second of each MOS The electrodes are connected in common, the third electrode of the first MOS is held at a low voltage, and the third electrode of the second MOS is held at a high voltage. is there.

[0007]

[Action]

 The parasitic junction capacitance of each MOS changes in a canceling direction according to the change of the voltage applied to the second electrode of each MOS, and the change of the combined capacitance seen from the second electrode is smaller than in the conventional case. ..

[0008]

【Example】

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, 11 is an N-type semiconductor substrate, in which a P well 12 forming a first MOS and an N well 13 forming a second MOS are symmetrically formed, and a dielectric layer 14 is formed on the surface. Has been formed.

Then, an N ⁺ region 15 and a P ⁺ region 16 are formed in the vicinity of the upper portion of the P well 12 by diffusion, and the first N ⁺ region 15 and the P ⁺ region 16 are formed so as to face the N ⁺ region 15 via the dielectric layer 14. An electrode 17 is formed, a second electrode 18 is connected to the N ⁺ region 15 through a hole provided in the dielectric layer 14, and a second electrode 18 is connected to the P ⁺ region 16 through a hole provided in the dielectric layer 14. The third electrode 19 is connected. These form the first MOS.

On the other hand, a P ⁺ region 20 and an N ⁺ region 21 are diffused and formed near the upper part of the N well 13, and the first electrode is formed so as to face the P ⁺ region 20 via the dielectric layer 14. 22 is formed, the second electrode 23 is connected to the P ⁺ region 20 through the hole provided in the dielectric layer 14, and the second electrode 23 is connected to the N ⁺ region 21 through the hole provided in the dielectric layer 14. Three electrodes 24 are connected. These form the second MOS.

The first electrodes 17 and 22 of each MOS are commonly connected to the A terminal, and the second electrodes 18 and 23 of each MOS are commonly connected to the B terminal. The third electrode 19 of the first MOS has a low potential V_SSAnd the third electrode 24 of the second MOS is held at _DD Held in.

FIG. 2 is an equivalent circuit diagram of FIG. That is, between the A terminal and the B terminal, the capacitance C _mn between the first electrode 17 and the second electrode 18 forming the first MOS and the first electrode 22 forming the second MO S. The capacitance C _mp between the second electrodes 23 is connected in parallel. Then, the parasitic junction capacitance C _jn between the P well 12 and the third electrode 19 is connected between the second electrode 18 and the third electrode 19 which form the first MOS, and the second MOS is connected to the parasitic junction capacitance C _jn. A parasitic junction capacitance C _jp between the N well 13 and the third electrode 24 is connected between the constituent second electrode 23 and the third electrode 24.

In such a configuration, when the potential of the terminal B rises, the potential difference between the N well 13 and the third electrode 24 becomes smaller and the width of the depletion layer at the junction portion becomes narrower. Therefore, the parasitic junction capacitance C_jpBecomes larger, the potential difference between the P well 12 and the third electrode 19 becomes larger, and the width of the depletion layer at the junction becomes wider. Therefore, the parasitic junction capacitance C _jn Becomes bigger. Further, when the potential of the terminal B decreases, the potential difference between the N well 13 and the third electrode 24 increases, and the width of the depletion layer in the junction portion widens._jpBecomes smaller, the potential difference between the P well 12 and the third electrode 19 becomes smaller, and the width of the depletion layer at the junction becomes narrower. Therefore, the parasitic junction capacitance C_{j n} Becomes bigger.

As described above, the changes in the parasitic junction capacitances C _jn and C _jp connected to the terminal B _tend to be offset, and the change in the combined capacitance seen from the terminal B is smaller than that in the conventional connection structure. Become.

By adjusting the concentration of each well 12 and the electrode area, it is possible to design the voltage dependence of the parasitic junction capacitances C _jn and C _jp to the optimum values. It is also possible to intentionally make the voltage dependence of the parasitic junction capacitances C _jn and C _jp positive or negative.

[0016]

[Effect of the device]

 According to the present invention described in detail above, the following effects can be obtained. Since the voltage dependence of the parasitic junction capacitance is reduced, the change in capacitance value due to the signal level is reduced, and the MOS capacitance can be improved in performance.

As a result, the difference between the design value and the actually measured value in the high-frequency characteristics is reduced, the accuracy of the integrating capacitor is improved, and the like, and the design difficulty can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of FIG.

FIG. 3 is a structural example diagram of a MOS capacitor mounted in a conventional semiconductor integrated circuit.

FIG. 4 is an equivalent circuit diagram of FIG.

[Explanation of symbols]

11 Semiconductor Substrate 12 P Well 13 N Well 14 Dielectric Layer 15,21 N ⁺ Region 16,20 P ⁺ Region 17,22 First Electrode 18,23 Second Electrode 19,24 Third Electrode

Claims (1)

[Scope of utility model registration request] 1. A semiconductor substrate in which a P well and an N well are formed symmetrically and a dielectric layer is formed on the surface, and N ⁺ regions and P ⁺ regions are diffused and formed in the P well.
A first electrode is formed so as to face the N ⁺ region through the dielectric layer, and a second electrode is connected to the N ⁺ region through a hole provided in the dielectric layer. A first MOS having a third electrode connected to the P ⁺ region through a hole formed in the layer, and a P ⁺ region and an N ⁺ region formed by diffusion in the N well,
A first electrode is formed so as to face the P ⁺ region through the dielectric layer, and a second electrode is connected to the P ⁺ region through a hole provided in the dielectric layer. A second MOS in which a third electrode is connected to the N ⁺ region through a hole provided in the layer, and the first electrode and the second electrode of each MOS are connected in common, and A semiconductor device, wherein the third electrode of the first MOS is held at a low voltage, and the third electrode of the second MOS is held at a high voltage.