JPS6048106B2 - semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit having a 505 structure in which required circuit elements are formed by forming island-shaped semiconductor regions (islands) on an insulating substrate. The present invention relates to a protection circuit that protects the gate of an insulated gate transistor from high voltage.

Generally, bulk-type MOs, that is, MOs using silicon (Si) substrates.
In the SIC, as shown in FIG. 1, a protection circuit B is provided to prevent high voltage from being applied from the input terminal IN of the internal circuit A.

This is a MOS transistor T. This is because the gate insulating film (for example, SiO) is as thin as about 700A, and there is a risk that the gate may suffer dielectric breakdown due to high voltage caused by static electricity from the input terminal IN.To prevent this, a resistor is installed in the protection circuit B. A series resistance R with a value of about IKΩ, and a protection transistor T connected between the gate of the transistor T2 and the ground.
Set i. Although the transistor Tl also has a MOS structure,
A field oxide film with a thickness of about 7000 Å is used for this gate insulating film, and an aluminum layer used for wiring systems is used for the gate electrode. Therefore, the threshold value of the protection transistor Tl is about 1 day that of the internal transistor T2 using a silicon gate (Vth of Tl is 10
~15 [V], that of T2 is about 0.8 [V]). During normal operation, the transistor Tl is off, but when an abnormal voltage is applied to the input terminal (■), it turns on, causing a voltage drop across the resistor R. is generated and the gate of transistor L is kept at a low potential to protect it. By the way, in SOSIC, as shown in FIG. 2, a silicon semiconductor layer is grown on an insulating substrate 2 made of sapphire or the like, and the active region, that is, the field area around the element formation region, is removed by etching or is etched by half and then oxidized. an insulating layer 14 of silicon dioxide;
The active region is made into an island, a gate insulating film 10 and a polycrystalline silicon gate electrode 12 are provided at the center of the surface of the island 4, and source and drain regions 6 and 8 are formed by impurity diffusion or ion implantation using this as a mask. Thus, one MOS transistor is formed.

This transistor is called the transistor T of the internal circuit A in FIG. However, since the gate insulating film 10 is thin and the gate withstand voltage is low, it is unsuitable for use as the transistor T of the protection circuit B, since there is a risk that the gate insulating film 10 may be destroyed. Therefore, we would like to form a transistor T1 similar to that shown in FIG. 1 by using the thick field oxide film 14 around the island 4 as in the case of a bulk MOSIC, but in the SOS structure, the insulating substrate 2 is directly under the oxide film 14. This is not possible since there are no silicon semiconductor parts present in the semiconductor. For this reason, a circuit as shown in FIG. 3 is generally used as the protection circuit B of the SOSMOSIC.

In addition to the series resistor R1, this uses two silicon gate MOS transistors T3 and T4 (assumed to be p-channel) similar to the internal circuit A. The transistor T3 connects the resistor R1 to the input terminal 1N. Between the gate G2 of the transistor T2 and the positive electric current Cc connected through the
Also, transistor T4 is connected between the gate G2 and ground. The gate of the transistor T3 and its source are connected to the power supply Vcc, and the gate of the transistor T4 and its source are connected to the gate G2. Therefore, under normal conditions, that is, when the voltage Vi at the input terminal IN is at a level between the power supply Vcc and the ground, the transistors T3 and T
4 are all off. Voltage Vj is Vi>Vcc>0
Or, when Vi becomes Vi (0, more specifically, the voltage Vi becomes V
When the voltage exceeds cc+1Vth31 (■Th3 is the threshold voltage of transistor T3), transistor T3 turns on and drops the voltage Vi from input terminal 1N to the power supply Vcc side, and the voltage at input terminal 1N becomes -1Vth4! (Vth4 is the threshold voltage of transistor T4) When the voltage drops below (Vth4 is the threshold voltage of transistor T4), transistor T is turned on and drops the voltage to the input terminal 1N to ground. The transistors T3 and T4 may be n-channel type, in which case the gate of T3 is moved to the G2 side,
T, you just need to connect it to the ground side. In this way, the gate of transistor T2 of internal circuit A is protected, but since the gate insulating film of transistors T3, T, is thin like transistor T2 of the internal circuit, if a high voltage is applied to input terminal 1N, the gate of transistor T2 is protected. Drain of T3, T4,
There is a high risk of dielectric breakdown between the gates. The present invention attempts to solve the problem peculiar to the SOS structure that a field oxide film cannot be used and to configure a protection transistor without complicating the manufacturing process. a first resistor inserted between; a MIS transistor whose drain or source is connected to the input terminal of the protected element; and whose source or drain is connected to a reference potential; and the gate of the MIS transistor. It is characterized by comprising a capacitor inserted between the input terminal and a second resistor or a diode inserted between the gate of the MIS type transistor and the reference potential, as shown below. This will be explained in detail with reference to an example.

FIGS. 4a to 4c are an equivalent circuit diagram, a sectional view, and a plan view showing an embodiment of the present invention. The transistor T5 in FIG. 4a is an ordinary enhancement type silica gate MOS transistor formed in the same process as the transistor T2 of the internal circuit A, and its gate insulating film is not particularly thick. However, its gate is grounded through a resistor R2 of about 1 MΩ and connected to the input terminal 1N through a capacitor C1, and due to this structure, the transistor T5 has the same function as the transistor T1 in FIG. It is equipped with abilities. In other words, since the gate of the transistor T5 is connected through the resistor R2, the transistor T5 normally remains off, but when a high voltage is applied to the input terminal 1N, the voltage is transferred to the capacitor C1 as shown by the dotted line. The voltage is divided by the gate-source capacitance q of the transistor T, and applied to the gate of the transistor T5, turning it on. The input overvoltage that turns on the transistor T5 is therefore determined by the voltage dividing ratio of the capacitors Q, C2, etc. and the threshold voltage of the transistor T5, so these are set appropriately. When transistor T5 is turned on, the voltage towards the gate of transistor T2 of internal circuit A is dropped to ground through Rl, T5. As a result, the gate of the transistor T2 is protected, and the voltage applied to the original gate insulating film of the transistor T5 (10 in FIG. 4b) is small, so that the transistor T5 is also not destroyed. The specific structure of this element is as shown in FIGS. 4B and 4e.

As shown in FIG. 4b, the transistor T5 has a cross-sectional structure similar to that in FIG. 18 are provided. P.S.G.
The film 16 is generally used as a base insulating layer for aluminum wiring in the IC manufacturing process, and by using this as a dielectric and using a part of the aluminum wiring as the electrode 18, the electrode 18 and the gate electrode 12 are connected. A capacitor C1 is formed between them. The source 6 of the transistor T5 is grounded (GND) through an aluminum wiring 20, which is generally referred to as a reference potential, and the drain 8 is connected to the input terminal 1N through an aluminum wiring 22 through a resistor R1, and connected to the transistor in the internal circuit through an aluminum wiring 24. Connected to the gate of T2.

The gate of transistor T5 is grounded via resistor R2, but this is omitted in FIG. 4b. FIG. 4c shows this in a plan view, where the resistor R1 is a diffused resistor connected to the drain 8, and its both ends are connected to the wiring 2 at points Pl and P2.
Contacted on 2nd and 24th. Further, the resistor R2 is a diffused resistor that is an extension of a part of the polycrystalline silicon gate 12, and one end thereof is contacted to the wiring 20 at a point P. The aluminum electrode 18 connects one end of the wiring 22 to the gate 1.
2 and so as to partially overlap the source and drains 6 and 8. Note that the point P4 is a portion where the source 6 and the wiring 20 are in contact, and the gate oxide film 10 and the PSG film 18 are omitted in the drawing. The resistors Rl and R2 may be formed by depositing and patterning a high-resistance metal material. Looking at FIG. 4b, even if the gate electrode 12 is removed to leave only the high PSG film 16 and the electrode 18 is attached thereon, the high Th protection transistor using the feed insulating film as shown in FIG. 1 can be obtained. I understand.

However, as mentioned above, source/drain diffusion is performed in self-alignment using the gate electrode as a mask, and removing the gate electrode 12 may make source/drain diffusion impossible or require a special process for SO.
This will disturb the SMOSIC manufacturing process. Therefore, in the stacked gate type protection transistor shown in FIG. The electrode 18 is part of the wiring and does not disturb the SOSMOSIC manufacturing process at all. FIGS. 5A and 5B are an equivalent circuit diagram and a sectional view of essential parts showing another embodiment of the present invention.

In this embodiment, the resistor R2 in FIG. 4a is replaced with a diode D1, and as shown in FIG. 4b, the anode side (p+ type region 26) of the diode D1 is connected to the wiring 20 (see FIG.
and ground through the cathode side (n+ type region 28
) is connected to the end of the bulge-shaped polycrystalline silicon layer 12 constituting the gate electrode. Note that when silicon dioxide having the same thickness as the island is used as the field insulation, the n+ layer 12 and the like naturally lie on the silicon dioxide layer. Since this diode D1 has a lot of leakage and easily breaks down at a low voltage, the gate of the transistor T5 is constantly kept at ground potential, and the transistor T5 remains off, and when a high voltage is applied to the input terminal 1N. For example, diode D1 breaks down and its cathode-anode voltage is applied to the gate of transistor T5, so that the same operation as in FIG. 4 is performed. As described above, according to the present invention, a circuit that protects the internal circuit of an SOSMOSIC can be formed simultaneously in the process of forming the internal circuit without changing the process, and in a manner equivalent to the protection circuit in a bulk MOSIC. There are advantages that can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a protection circuit in MOSIC using a silicon substrate, Fig. 2 is a cross-sectional view showing a MOS transistor with an SOS structure, Fig. 3 is a circuit diagram showing an example of a conventional protection circuit in SOSIC, 4A, b, and c are equivalent circuit diagrams, cross-sectional views, and plan views showing one embodiment of the present invention, and FIGS. 5A, b are equivalent circuit diagrams and principal part views showing other embodiments of the present invention. There is no problem. In the figure, A is the internal circuit, T2 is the MOS transistor at its input stage, B is the protection circuit, Rl and R2 are resistors, and C1 is the PS
A capacitor using G film, T5 is a transistor similar to the internal circuit, 2 is an insulating substrate, 4 is a silicon island,
10 is a gate insulating film, 12 is a silicon gate, 16 is P
The SG film 18 is an aluminum electrode.

Claims (1)

[Claims] 1 MIS type in which a first resistor is inserted between an input terminal and an input terminal of a protected element, a drain or source is connected to the input terminal of the protected element, and a source or drain is connected to a reference potential. A transistor, a capacitor inserted between the gate of the MIS transistor and the input terminal, and a second resistor or diode inserted between the gate of the MIS transistor and the reference potential. A semiconductor integrated circuit characterized by: