JPH0456469B2 - - Google Patents
Info
- Publication number
- JPH0456469B2 JPH0456469B2 JP57012309A JP1230982A JPH0456469B2 JP H0456469 B2 JPH0456469 B2 JP H0456469B2 JP 57012309 A JP57012309 A JP 57012309A JP 1230982 A JP1230982 A JP 1230982A JP H0456469 B2 JPH0456469 B2 JP H0456469B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- input protection
- region
- protection resistor
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 51
- 230000005669 field effect Effects 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 13
- 230000005496 eutectics Effects 0.000 claims description 9
- 239000012535 impurity Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 32
- 239000011229 interlayer Substances 0.000 description 8
- 238000000605 extraction Methods 0.000 description 7
- 229910018125 Al-Si Inorganic materials 0.000 description 4
- 229910018520 Al—Si Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Protection Of Static Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、半導体装置に関し、特に絶縁基板上
の半導体層に設けられた入力保護回路を改良した
半導体装置に係わる。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device in which an input protection circuit provided in a semiconductor layer on an insulating substrate is improved.
（従来の技術）］
従来、絶縁基板（例えばサフアイア基板）上の
半導体層に設けられた入力保護回路は、第１図に
示すように入力保護抵抗R1、保護用電界効果ト
ランジスタ（以下単にトランジスタと略す）T1
およびキヤパシタC1から構成されている。(Prior Art) Conventionally, an input protection circuit provided in a semiconductor layer on an insulating substrate (for example, a sapphire substrate) has an input protection resistor R 1 and a protection field effect transistor (hereinafter simply a transistor) as shown in FIG. ) T 1
and capacitor C1 .
しかしながら、前記構成の入力保護回路におい
てトランジスタT1は絶縁基板上の半導体層に設
けられているため、そのチヤンネル基部はフロー
テイング状態になる。すなわち、前記トランジス
タのゲート電極はソース領域の端子に接続されて
いるため、前記ソランジスタは、通常OFF状態
になつているが、数Ｖ（例えば5V）の電圧が入力
端子I1に印加された程度でもチヤンネル基部がフ
ローテイング状態になるため、インパクト・アイ
オニゼーシヨン電流、いわゆるキンク現象による
電流が流れる。特に、半導体装置の微細化が進
み、トランジスタのチヤンネル長が短くなつた場
合には、シヨートチヤンネル効果を防ぐためにチ
ヤンネル基部の不純物濃度を高くする必要があ
る。かかる場合には、前記キンク現象はますます
顕著になる。したがつて、入力保護回路としては
その機能を果たすが、入力リーク電流が増大する
という問題がある。 However, in the input protection circuit configured as described above, since the transistor T1 is provided in a semiconductor layer on an insulating substrate, its channel base is in a floating state. That is, since the gate electrode of the transistor is connected to the terminal of the source region, the transistor is normally in an OFF state, but when a voltage of several volts (for example, 5V) is applied to the input terminal I1 . However, since the base of the channel is in a floating state, an impact ionization current, a current due to the so-called kink phenomenon, flows. Particularly, as the miniaturization of semiconductor devices progresses and the channel length of transistors becomes shorter, it is necessary to increase the impurity concentration at the base of the channel in order to prevent the short channel effect. In such a case, the kink phenomenon becomes more and more noticeable. Therefore, although it functions as an input protection circuit, there is a problem in that input leakage current increases.
（発明が解決しようとする課題）
本発明は、入力保護機能を果たすことは勿論、
入力リーク電流の低減化が可能な入力保護回路を
備えた半導体装置を提供しようとするものであ
る。(Problems to be Solved by the Invention) The present invention not only fulfills the input protection function, but also
The present invention aims to provide a semiconductor device equipped with an input protection circuit capable of reducing input leakage current.
（課題を解決するための手段）
本願第１の発明は、絶縁基板上の半導体層に設
けられた入力保護抵抗と、前記半導体層に設けら
れ、前記入力保護抵抗に接続された電界効果トラ
ンジスタと、前記半導体層に設けられ、前記入力
保護抵抗に前記トランジスタに対して並列接続さ
れるように接続されたキヤパシタとからなる入力
保護回路を備えた半導体装置において、
前記電界効果トランジスタは、前記半導体層に
設けられた、前記入力保護抵抗に接続されたドレ
イン領域と、前記半導体層に前記ドレイン領域と
電気的に分離して設けられたソース領域と、前記
ソース、ドレイン領域間を含む前記半導体層上に
ゲート絶縁膜を介して設けられたゲート電極と、
前記ソース領域とゲート電極に亘る領域にコンタ
クトホールを通して接続された金属配線と、前記
ソース領域から前記ゲート電極下のチヤンネル基
部にまで到達され、前記チヤンネル基部にソース
電位を与えるための前記配線の金属と前記ソース
領域の半導体層との共晶層とを有することを特徴
とする半導体装置である。(Means for Solving the Problems) A first invention of the present application includes: an input protection resistor provided in a semiconductor layer on an insulating substrate; and a field effect transistor provided in the semiconductor layer and connected to the input protection resistor. , a semiconductor device including an input protection circuit provided in the semiconductor layer and comprising a capacitor connected to the input protection resistor in parallel with the transistor, wherein the field effect transistor is provided in the semiconductor layer. a drain region connected to the input protection resistor provided in the semiconductor layer; a source region provided in the semiconductor layer electrically separated from the drain region; and a region on the semiconductor layer including between the source and drain regions. a gate electrode provided through a gate insulating film;
A metal wiring connected to a region spanning the source region and the gate electrode through a contact hole, and a metal of the wiring that reaches from the source region to the channel base below the gate electrode and provides a source potential to the channel base. and a eutectic layer with the semiconductor layer of the source region.
本願第２の発明は、絶縁基板上の半導体層に設
けられた入力保護抵抗と、前記半導体層に設けら
れ、前記入力保護抵抗に接続された電界効果トラ
ンジスタと、前記半導体層に設けられ、前記入力
保護抵抗に前記トランジスタに対して並列接続さ
れるように接続されたキヤパシタとからなる入力
保護回路を備えた半導体装置において、
前記電界効果トランジスタは、前記半導体層に
設けられ、前記入力保護抵抗に接続されたドレイ
ン領域と、前記半導体層に前記ドレイン領域と電
気的に分離して設けられたソース領域と、前記ソ
ース、ドレイン領域間を含む前記半導体層上にゲ
ート絶縁膜を介して設けられたゲート電極と、前
記ソース領域の少なくとも一部に形成されたチヤ
ンネル基部と同一導電型の不純物領域と、前記不
純物領域、前記ソース領域およびゲート電極に亘
る領域にコンタクトホールを通して接続され、前
記チヤンネル基部にソース電位を与えるための金
属とを有することを特徴とする半導体装置であ
る。 A second invention of the present application provides an input protection resistor provided in a semiconductor layer on an insulating substrate, a field effect transistor provided in the semiconductor layer and connected to the input protection resistor, and a field effect transistor provided in the semiconductor layer and connected to the input protection resistor. In a semiconductor device including an input protection circuit including an input protection resistor and a capacitor connected in parallel to the transistor, the field effect transistor is provided in the semiconductor layer, and the field effect transistor is connected to the input protection resistor. a connected drain region, a source region provided in the semiconductor layer electrically separated from the drain region, and a source region provided on the semiconductor layer including between the source and drain regions via a gate insulating film. a gate electrode, an impurity region formed in at least a portion of the source region and having the same conductivity type as the channel base, and an impurity region connected to the impurity region, the source region, and the gate electrode through a contact hole, and connected to the channel base. A semiconductor device characterized by having a metal for providing a source potential.
（作用）
本発明によれば、前記入力保護回路を構成する
前記トランジスタの前記チヤンネル基部にソース
電位を与えることによつて、前記チヤンネル基部
がフローテイング状態になるのを回避でき、ひい
てはキンク現象による入力リーク電流の発生を低
減することが可能となる。(Function) According to the present invention, by applying a source potential to the channel base of the transistor constituting the input protection circuit, it is possible to avoid the channel base from becoming in a floating state, and furthermore, it is possible to avoid the floating state due to the kink phenomenon. It becomes possible to reduce the occurrence of input leakage current.
（実施例）
以下、本発明の実施例を図面を参照して詳細に
説明する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
実施例 １
第２図は、本発明の半導体装置に組み込まれた
入力保護回路の回路図である。第２図中のR2は、
後述する絶縁基板の半導体層（図示せず）表面に
形成された拡散層または多結晶シリコンからなる
入力保護抵抗である。C2は、前記半導体層に形
成され、前記入力保護抵抗R2に接続されるキヤ
パシタンスである。T2は、後述する島状半導体
層に設けられ、前記入力保護抵抗R2に前記キヤ
パシタンスC2に対して並列接続されるように接
続されたｎチヤンネルトランジスタであり、前記
トランジスタT2はチヤンネル基部が接地されて
いる。Embodiment 1 FIG. 2 is a circuit diagram of an input protection circuit incorporated in a semiconductor device of the present invention. R 2 in Figure 2 is
This is an input protection resistor made of a diffusion layer or polycrystalline silicon formed on the surface of a semiconductor layer (not shown) of an insulating substrate, which will be described later. C2 is a capacitance formed in the semiconductor layer and connected to the input protection resistor R2 . T 2 is an n-channel transistor provided in an island-shaped semiconductor layer, which will be described later, and connected to the input protection resistor R 2 in parallel to the capacitance C 2 , and the transistor T 2 is located at the channel base. is grounded.
前記トランジスタT2は、第３図ａ，ｂに示す
構造を有する。すなわち、図中の１は絶縁基板で
ある。前記絶縁基板１上には、フイールド酸化膜
（素子分離領域）２で分離された島状半導体層３
が設けられている。前記半導体層３には、互いに
電気的に分離されたn+型のソース、ドレイン領
域４，５が設けられている。前記ソース、ドレイ
ン領域４，５間のp-型チヤンネル基部６を含む
領域上には、ゲート酸化膜７を介して多結晶シリ
コンからなるゲート電極８が設けられている。な
お、前記ゲート電極８の右端側は拡大され、この
拡大部８ａ下にも前記チヤンネル基部６が延出し
ていると共に前記基部６と前記拡大部８ａの間に
も前記ゲート酸化膜７が介在されている。 The transistor T2 has the structure shown in FIGS. 3a and 3b. That is, 1 in the figure is an insulating substrate. On the insulating substrate 1, there is an island-shaped semiconductor layer 3 separated by a field oxide film (element isolation region) 2.
is provided. The semiconductor layer 3 is provided with n + -type source and drain regions 4 and 5 that are electrically isolated from each other. A gate electrode 8 made of polycrystalline silicon is provided on a region including the p - type channel base 6 between the source and drain regions 4 and 5 with a gate oxide film 7 interposed therebetween. Note that the right end side of the gate electrode 8 is enlarged, and the channel base 6 extends below the enlarged portion 8a, and the gate oxide film 7 is also interposed between the base 6 and the enlarged portion 8a. ing.
前記半導体層３および前記フイールド酸化膜２
上には、例えばSiO2からなる層間絶縁膜９が被
覆されている。前記層間絶縁膜９の前記ソース領
域４と前記ゲート電極８の拡大部８ａに亘る領域
には、コンタクトホール１０が開孔されている。
また、前記層間絶縁膜９の前記ドレイン領域５の
一部に対応する領域にもコンタクトホール１０′
が開孔されている。前記層間絶縁膜９上には、
Al配線１１が設けられている。前記Al配線１１
は、前記コンタクトホール１０を通して前記ソー
ス領域４とゲート電極８の拡大部８ａとに接続さ
れている。つまり、前記ソース領域４とゲート電
極８の拡大部８ａとは前記Al配線１１により相
互に接続されている。なお、前記層間絶縁膜９上
には前記ドレイン領域５とコンタクトホール１
０′を通して接続されるAl配線（図示せず）が設
けられている。前記Al配線は、前記入力保護抵
抗R2に接続されている。 The semiconductor layer 3 and the field oxide film 2
An interlayer insulating film 9 made of, for example, SiO 2 is coated thereon. A contact hole 10 is formed in a region of the interlayer insulating film 9 spanning the source region 4 and the enlarged portion 8 a of the gate electrode 8 .
Further, a contact hole 10' is also formed in a region of the interlayer insulating film 9 corresponding to a part of the drain region 5.
is drilled. On the interlayer insulating film 9,
Al wiring 11 is provided. The Al wiring 11
is connected to the source region 4 and the enlarged portion 8a of the gate electrode 8 through the contact hole 10. That is, the source region 4 and the enlarged portion 8a of the gate electrode 8 are connected to each other by the Al wiring 11. Note that the drain region 5 and the contact hole 1 are formed on the interlayer insulating film 9.
An Al wiring (not shown) connected through 0' is provided. The Al wiring is connected to the input protection resistor R2 .
前記Al配線１１と前記ソース領域４とは、シ
ンターを行うことによりAl−Si共晶層１２が形
成され、オーミツクコンタクトなされている。こ
こで、さらに前記n+型ソース領域４表面に生成
した前記Al−Si共晶が前記ゲート電極８の拡大
部８ａ下の前記p-型チヤンネル基部６にまで到
達するように前記シンターをコントロールするこ
とによつて、前記チヤンネル基部６が第３図ｂに
示すようにAl−Si共晶層１２を介して前記ソー
ス領域４側に接続される。 The Al wiring 11 and the source region 4 are sintered to form an Al--Si eutectic layer 12 and are in ohmic contact. Here, the sintering is further controlled so that the Al-Si eutectic generated on the surface of the n + type source region 4 reaches the p - type channel base 6 below the enlarged portion 8a of the gate electrode 8. In this way, the channel base 6 is connected to the source region 4 through the Al--Si eutectic layer 12, as shown in FIG. 3b.
このような構成により、第２図図示の回路図に
おけるトランジスタT2のチヤンネル基部はn+型
ソース領域４表面のAl−Si共晶層１２が前記ゲ
ート電極８の拡大部８ａ下のp-型チヤンネル基
部６部分にまで到達されることによつてソースの
端子に接続され、前記チヤンネル基部６は所望の
電位（ソース電位）が与えられる。 With such a configuration, the channel base of the transistor T 2 in the circuit diagram shown in FIG . By reaching the channel base 6 portion, it is connected to the source terminal, and the channel base 6 is given a desired potential (source potential).
したがつて、今、入力端子I2にサージ状の高い
電圧が印加されると、前記入力保護抵抗R2、キ
ヤパシタC2は平滑回路を形成しているため、前
記入力端子I2に与えられた立上がりの早い電圧は
出力端子O2に立上がりの穏やかなものとなつて
現われる。また、正の電位に対しては前記トラン
ジスタT2のドレインブレータダウンにより、負
の電位に対しては前記トランジスタT2がONにな
つて電流が流れ、その電流と入力保護抵抗R2と
による電圧降下により、それぞれ前記出力端子
O2には高い電圧が現われなくなる。その結果、
このような入力保護回路では入力保護機能を果た
す。 Therefore, if a surge-like high voltage is now applied to the input terminal I2 , the input protection resistor R2 and capacitor C2 form a smoothing circuit, so that the voltage applied to the input terminal I2 is The voltage that rises quickly appears at the output terminal O2 as a voltage that rises slowly. In addition, for a positive potential, the drain breaker of the transistor T 2 is turned down, and for a negative potential, the transistor T 2 is turned on and a current flows, and a voltage due to the current and the input protection resistor R 2 is generated. By dropping the respective output terminals
High voltages no longer appear on O 2 . the result,
Such an input protection circuit performs an input protection function.
一方、前記入力端子I2に通常の入力信号電位
（例えば5V）が印加された場合には、前記トラン
ジスタT2はプレークダウンしないために信号は
そのまま前記出力端子O2に現われる。この場合、
前記トランジスタT2のチヤンネル基部６は第３
図ａ，ｂで説明したようにAl−Si共晶層１２に
よつてn+型ソース領域４に接続され、所望のソ
ース電位が与えられる。つまり、前記チヤンネル
基部６は接地されれているため、前記チヤンネル
基部６で生じたインパクト・アイオニゼーシヨン
によるキヤリアは前記ソース領域４側に吸収され
るため、キンク現象は起こらず、入力リーク電流
の増大を防止できる。 On the other hand, when a normal input signal potential (for example, 5V) is applied to the input terminal I2 , the signal appears at the output terminal O2 as it is because the transistor T2 does not break down. in this case,
The channel base 6 of the transistor T 2 is the third
As explained in FIGS. a and b, it is connected to the n + type source region 4 by the Al--Si eutectic layer 12, and a desired source potential is applied. In other words, since the channel base 6 is grounded, carriers due to impact ionization generated at the channel base 6 are absorbed into the source region 4 side, so no kink phenomenon occurs and input leakage current can prevent an increase in
また、第３図ａ，ｂに示すようにソース領域４
とゲート電極８の拡大部８ａに亘つてコンタクト
ホール１０を設け、前記ソース領域４とチヤンネ
ル基部６とをAl−Si共晶の拡散により形成され
たAl−Si共晶層１２で接続する構造にすること
によつて、特別のチヤンネル基部をゲート電極下
から引き出す必要がないため、トランジスタの面
積増大を招くことなく、チヤンネル基部６をソー
ス領域４と同電位にすることができる。 In addition, as shown in FIGS. 3a and 3b, the source region 4
A contact hole 10 is provided across the enlarged portion 8a of the gate electrode 8, and the source region 4 and the channel base 6 are connected by an Al-Si eutectic layer 12 formed by diffusion of Al-Si eutectic. By doing so, it is not necessary to draw out a special channel base from under the gate electrode, so that the channel base 6 can be made to have the same potential as the source region 4 without increasing the area of the transistor.
実施例 ２
第４図ａは、本実施例２における入力保護回路
を構成する電界効果トランジスタの平面図、同図
ｂは同図ａのＢ−Ｂ線に沿う断面図である。な
お、第４図ａ，ｂにおいて前述した第３図ａ，ｂ
と同様な部材は同符号を付して説明を省略する。Embodiment 2 FIG. 4a is a plan view of a field effect transistor constituting an input protection circuit according to the second embodiment, and FIG. 4b is a cross-sectional view taken along line BB in FIG. 4a. In addition, FIG. 3 a, b mentioned above in FIG. 4 a, b
The same members are given the same reference numerals and the description thereof will be omitted.
前記トランジスタは、n+型ソース領域４内に
p+型基部取出し領域１３をp-型チヤンネル基部
６に接続するように設け、前記ソース領域４、基
部取り出し領域１３およびゲート電極８の拡大部
８ａに亘る層間絶縁膜９の領域にコンタクトホー
ル１０を開孔し、前記コンタクトホール１０を通
して前記ソース領域４、基部取出し領域１３およ
びゲート電極８の拡大部８ａに接続されるAl配
線１１を前記層間絶縁膜９に設けた構造になつて
いる。つまり、前記チヤンネル基部６は前記基部
取出し領域１３、コンタクトホール１０および
Al配線１１を通して前記ソース領域４に接続さ
れ、前記ソース領域４と同電位が与えられるよう
になつている。なお、前記層間絶縁膜９上にはド
レイン領域５とコンタクトホール１０′を通して
接続されるAl配線（図示せず）が設けられ、か
つ前記Al配線は第２図に示す入力保護回路の入
力保護抵抗R2に接続されている。 The transistor has an n + type source region 4
A p + type base extraction region 13 is provided so as to be connected to the p − type channel base 6, and a contact hole 10 is provided in a region of the interlayer insulating film 9 spanning the source region 4, the base extraction region 13, and the enlarged portion 8a of the gate electrode 8. The structure is such that the interlayer insulating film 9 is provided with an Al wiring 11 which is opened and connected to the source region 4, the base extraction region 13, and the enlarged portion 8a of the gate electrode 8 through the contact hole 10. That is, the channel base 6 includes the base extraction region 13, the contact hole 10 and
It is connected to the source region 4 through the Al wiring 11, and is provided with the same potential as the source region 4. Note that an Al wiring (not shown) is provided on the interlayer insulating film 9 and is connected to the drain region 5 through a contact hole 10', and the Al wiring is connected to an input protection resistor of the input protection circuit shown in FIG. Connected to R 2 .
このような構成によれば、トランジスタ領域と
は別の箇所に基部取出し端子を特別に設ける必要
がないため、トランジスタの面積増大を招くこと
なく、チヤンネル基部６をソース領域４と同電位
にすることができる。 According to such a configuration, there is no need to specially provide a base extraction terminal at a location different from the transistor region, so the channel base 6 can be made to have the same potential as the source region 4 without increasing the area of the transistor. Can be done.
なお、前記実施例２においてソース領域４の一
部にp+型基部取出し領域１３を設けたが、ソー
ス領域４全体に設けてもよい。 In the second embodiment, the p + type base extraction region 13 is provided in a part of the source region 4, but it may be provided in the entire source region 4.
また、前記実施例１、２ではトランジスタとし
てｎチヤンネルの場合について説明したが、ｐチ
ヤンネル相補型のトランジスタを用いても同様な
効果を有する。 Further, in the first and second embodiments, an n-channel transistor is used as the transistor, but the same effect can be obtained even if a p-channel complementary transistor is used.
（発明の効果）
以上詳述したように、本発明によれば入力保護
機能を果たすことは勿論、入力リーク電流の低減
化が可能な高性能の入力保護回路を備えた半導体
装置を提供できる。(Effects of the Invention) As described in detail above, according to the present invention, it is possible to provide a semiconductor device equipped with a high-performance input protection circuit that not only fulfills the input protection function but also can reduce input leakage current.
第１図は従来の絶縁基板上の半導体層に設けら
れた入力保護回路を示す回路図、第２図は本発明
の実施例１における入力保護回路を示す回路図、
第３図ａは第２図の入力保護回路を構成する電界
効果トランジスタを示す平面図、同図ｂは同図ａ
のＢ−Ｂ線に沿う断面図、第４図ａは本実施例２
における入力保護回路を構成する電界効果トラン
ジスタの平面図、同図ｂは同図ａのＢ−Ｂ線に沿
う断面図である。
１……絶縁基板、３……島状の半導体層、４…
…n+型ソース領域、５……n+型ドレイン領域、
６……p-型チヤンネル基部、８……ゲート電極、
８ａ……拡大部、１０，１０′……コンタクトホ
ール、１１……Al配線、１２……Al−Si共晶層、
１２′……p+型基部取出し領域。
FIG. 1 is a circuit diagram showing a conventional input protection circuit provided in a semiconductor layer on an insulating substrate, and FIG. 2 is a circuit diagram showing an input protection circuit in Embodiment 1 of the present invention.
Fig. 3a is a plan view showing a field effect transistor constituting the input protection circuit of Fig. 2, and Fig.
A cross-sectional view taken along line B-B of FIG.
FIG. 3B is a plan view of a field effect transistor constituting the input protection circuit in FIG. 1... Insulating substrate, 3... Island-shaped semiconductor layer, 4...
...n + type source region, 5...n + type drain region,
6...p - type channel base, 8... gate electrode,
8a... Enlarged part, 10, 10'... Contact hole, 11... Al wiring, 12... Al-Si eutectic layer,
12'...p + type base extraction area.
Claims (1)
抵抗と、前記半導体層に設けられ、前記入力保護
抵抗に接続された電界効果トランジスタと、前記
半導体層に設けられ、前記入力保護抵抗に前記ト
ランジスタに対して並列接続されるように接続さ
れたキヤパシタとからなる入力保護回路を備えた
半導体装置において、 前記電界効果トランジスタは、前記半導体層に
設けられ、前記入力保護抵抗に接続されたドレイ
ン領域と、前記半導体層に前記ドレイン領域と電
気的に分離して設けられたソース領域と、前記ソ
ース、ドレイン領域間を含む前記半導体層上にゲ
ート絶縁膜を介して設けられたゲート電極と、前
記ソース領域とゲート電極に亘る領域にコンタク
トホールを通して接続された金属配線と、前記ソ
ース領域から前記ゲート電極下のチヤンネル基部
にまで到達され、前記チヤンネル基部にソース電
位を与えるための前記配線の金属と前記ソース領
域の半導体層との共晶層とを有することを特徴と
する半導体装置。 ２ 絶縁基板上の半導体層に設けられた入力保護
抵抗と、前記半導体層に設けられ、前記入力保護
抵抗に接続された電界効果トランジスタと、前記
半導体層に設けられ、前記入力保護抵抗に前記ト
ランジスタに対して並列接続されるように接続さ
れたキヤパシタとからなる入力保護回路を備えた
半導体装置において、 前記電界効果トランジスタは、前記半導体層に
設けられ、前記入力保護抵抗に接続されたドレイ
ン領域と、前記半導体層に前記ドレイン領域と電
気的に分離して設けられたソース領域と、前記ソ
ース、ドレイン領域間を含む前記半導体層上にゲ
ート絶縁膜を介して設けられたゲート電極と、前
記ソース領域の少なくとも一部に形成されたチヤ
ンネル基部と同一導電型の不純物領域と、前記不
純物領域、前記ソース領域およびゲート電極に亘
る領域にコンタクトホールを通して接続され、前
記チヤンネル基部にソース電位を与えるための金
属配線とを有することを特徴とする半導体装置。[Scope of Claims] 1. An input protection resistor provided in a semiconductor layer on an insulating substrate, a field effect transistor provided in the semiconductor layer and connected to the input protection resistor, and a field effect transistor provided in the semiconductor layer and connected to the input protection resistor. In a semiconductor device including an input protection circuit including an input protection resistor and a capacitor connected in parallel to the transistor, the field effect transistor is provided in the semiconductor layer, and the field effect transistor is connected to the input protection resistor. a connected drain region, a source region provided in the semiconductor layer electrically separated from the drain region, and a source region provided on the semiconductor layer including between the source and drain regions via a gate insulating film. a gate electrode; a metal wiring connected through a contact hole to a region spanning the source region and the gate electrode; A semiconductor device comprising a eutectic layer of metal of the wiring and a semiconductor layer of the source region. 2. An input protection resistor provided in a semiconductor layer on an insulating substrate, a field effect transistor provided in the semiconductor layer and connected to the input protection resistor, and a field effect transistor provided in the semiconductor layer and connected to the input protection resistor. In the semiconductor device, the field effect transistor includes a drain region provided in the semiconductor layer and a drain region connected to the input protection resistor. , a source region provided in the semiconductor layer electrically separated from the drain region, a gate electrode provided on the semiconductor layer including between the source and drain regions with a gate insulating film interposed therebetween, and the source. An impurity region formed in at least a part of the region and having the same conductivity type as the channel base, and a region extending between the impurity region, the source region, and the gate electrode through a contact hole, and for applying a source potential to the channel base. A semiconductor device characterized by having metal wiring.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230982A JPS58151062A (en) | 1982-01-28 | 1982-01-28 | Semiconductor device |
| FR8222037A FR2520556B1 (en) | 1982-01-28 | 1982-12-29 | SEMICONDUCTOR DEVICE FORMED ON AN INSULATING SUBSTRATE |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1230982A JPS58151062A (en) | 1982-01-28 | 1982-01-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58151062A JPS58151062A (en) | 1983-09-08 |
| JPH0456469B2 true JPH0456469B2 (en) | 1992-09-08 |
Family
ID=11801709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1230982A Granted JPS58151062A (en) | 1982-01-28 | 1982-01-28 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS58151062A (en) |
| FR (1) | FR2520556B1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62104173A (en) * | 1985-10-31 | 1987-05-14 | Fujitsu Ltd | Semiconductor device |
| GB2211989A (en) * | 1987-11-05 | 1989-07-12 | Marconi Electronic Devices | Field effect transistors |
| FR2648623B1 (en) * | 1989-06-19 | 1994-07-08 | France Etat | INSULATED MOS TRANSISTOR STRUCTURE WITH SOURCE-CONNECTED BOX SOCKET AND MANUFACTURING METHOD |
| FR2789519B1 (en) * | 1999-02-05 | 2003-03-28 | Commissariat Energie Atomique | MOS TRANSISTOR WITH A DYNAMIC THRESHOLD VOLTAGE EQUIPPED WITH A CURRENT LIMITER, AND METHOD OF MAKING SUCH A TRANSISTOR |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279786A (en) * | 1975-12-26 | 1977-07-05 | Fujitsu Ltd | Semiconductor memory device |
| JPS52144278A (en) * | 1976-05-27 | 1977-12-01 | Toshiba Corp | Circuit for protecting input with respect to mos integrated circuit |
| JPS5366178A (en) * | 1976-11-26 | 1978-06-13 | Toshiba Corp | Input protecting circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2284983A1 (en) * | 1974-09-13 | 1976-04-09 | Commissariat Energie Atomique | MOS transistor - with smoothly changing impurities concn from drain to substrate by electric field strength manipulation |
| US4302765A (en) * | 1978-09-05 | 1981-11-24 | Rockwell International Corporation | Geometry for fabricating enhancement and depletion-type, pull-up field effect transistor devices |
-
1982
- 1982-01-28 JP JP1230982A patent/JPS58151062A/en active Granted
- 1982-12-29 FR FR8222037A patent/FR2520556B1/en not_active Expired
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5279786A (en) * | 1975-12-26 | 1977-07-05 | Fujitsu Ltd | Semiconductor memory device |
| JPS52144278A (en) * | 1976-05-27 | 1977-12-01 | Toshiba Corp | Circuit for protecting input with respect to mos integrated circuit |
| JPS5366178A (en) * | 1976-11-26 | 1978-06-13 | Toshiba Corp | Input protecting circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58151062A (en) | 1983-09-08 |
| FR2520556A1 (en) | 1983-07-29 |
| FR2520556B1 (en) | 1986-04-25 |
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