JP3361382B2 - Transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

This invention relates to transistors,
In particular, it relates to improvement of breakdown voltage between the drain and the substrate.

[0002]

2. Description of the Related Art Aluminum gate M as a switching element
OS transistors are used. In order to improve the reliability as a switching element, it is necessary to increase the breakdown voltage of the transistor. A transistor having a thick oxide film near the drain is known as a high breakdown voltage MOS transistor.

The structure of a conventional high breakdown voltage aluminum gate MOS transistor is shown in FIG. FIG. 6A is a schematic view of the conventional high breakdown voltage aluminum gate MOS transistor 2 seen from the upper surface, and FIG. 6B is a schematic view of the JJ cross section. This conventional aluminum gate MOS transistor 2 is a P-channel aluminum gate MOS transistor. Board 4
Is composed of an N-type semiconductor.

As shown in FIG. 6B, a source region 6 and a drain region 8 made of a P-type semiconductor are formed in the substrate 4 with a predetermined distance. Source area 6
The upper surface of the drain region 8 is almost covered with the field oxide film 10.

The upper portion of the gate region 12 sandwiched between the source region 6 and the drain region 8 near the contact portion 12a with the drain region 8 has an extended portion 10a of the field oxide film 10.
Is covered with. The upper surface of the other part of the gate region 12 is
It is covered with the gate oxide film 14. A gate electrode 16 is provided on the upper surface of the gate region 12 via the extension 10 a of the field oxide film 10 and the gate oxide film 14. The gate electrode 16 is made of aluminum.

As shown in FIG. 6A, a channel stopper region 22 is formed so as to surround the source region 6, the drain region 8 and the gate region 12. The channel stopper region 22 is made of an N-type semiconductor having an impurity concentration higher than that of the substrate 4, and is formed to a predetermined depth from the upper surface of the substrate 4 as shown in FIG. 9B.

In FIG. 6B, when the drain voltage VDD is applied to the drain region 8 of the conventional high breakdown voltage aluminum gate MOS transistor 2 and the source region 6, the gate electrode 16 and the substrate 4 are grounded (see FIG. 7A). The operation will be described. This is a state in which the conventional high breakdown voltage aluminum gate MOS transistor 2 is turned off. In this state, as shown in FIG. 6B, a depletion layer 18 having no carriers is formed so as to surround the drain region 8.

The depletion layer 18 is formed to have a substantially uniform thickness around the drain region 8 in the vicinity of the contact region 12a of the gate region 12 with the drain region 8 as in other portions (FIGS. 6B and 18a). reference). This is the contact area 12
This is because the extension portion 10a of the field oxide film 10 is formed immediately above a, and thus it is unlikely to be affected by the electric field due to the gate electrode 16.

That is, the extension portion 10a is not provided (see FIG. 6).
The depletion layer 18 is formed more uniformly than in the case of a general aluminum gate MOS transistor (shown by a broken line in B) (see FIGS. 6B and 18b). Therefore, the contact area 12
The electric field concentration in a can be relaxed. Therefore, it is possible to prevent local breakdown in the vicinity of the contact portion 12a, and as a result, it is possible to increase the breakdown voltage at the time of OFF.

[0010]

However, the conventional high breakdown voltage aluminum gate MOS transistor 2 as described above is used.
Had the following problems. For the gate electrode 16,
When the voltage VG equal to or higher than the threshold value is applied, the conventional high breakdown voltage aluminum gate MOS transistor 2 is turned on.

As shown in FIG. 7B, when the substrate 4 is not grounded, a high breakdown voltage is exhibited as in the case of OFF when the drain voltage VDD rises. This is because the extension 10a of the field oxide film 10 is formed immediately above the contact area 12a (see FIG. 6B) as in the case described above, so that the concentration of the electric field in the contact area 12a is relaxed. .

However, as shown in FIG. 8A, when the substrate 4 is grounded, the breakdown phenomenon occurs at a lower drain voltage than when the substrate 4 is not grounded (the case of FIG. 7B). The operation when the substrate 4 is grounded will be described with reference to FIG.
FIG. 9A is a conventional high breakdown voltage aluminum gate MO shown in FIG. 6A.
It is a schematic diagram of a JJ cross section of the S transistor 2 at the time of ON.

When a negative gate voltage VG equal to or higher than the threshold value is applied to the gate electrode 16, the gate region 12 in contact with the gate oxide film 14 is a hole having positive charges having a polarity opposite to that of the gate voltage VG. It is filled. Therefore, the portion filled with the holes exhibits the same behavior as the P-type semiconductor. A part of the substrate 4 which is an N-type semiconductor is inverted to P-type while the gate voltage VG is applied. This state is called a strong inversion state, and the inverted layer is called a channel 20.

In FIG. 9, a certain number of holes are indicated by "x". That is, in the channel 20, a portion having a large number of “x” has a high hole concentration,
The portion where the number of x ″ is small indicates that the hole concentration is low.

As shown in FIG. 9A, the drain region 8 and the source region 6, both of which are made of P-type semiconductor, have P
Connected by a channel 20 inverted to the mold, thus
The drain region 8 and the source region 6 are in a conductive state. In this case, the breakdown voltage between the drain region 8 and the source region 6 shows a high value due to the presence of the extension portion 10a of the field oxide film 10 as in the case where the substrate 4 is not grounded (see FIG. 7B).

FIG. 9B shows a KK cross section (see FIG. 6A) in this state. The channel 20 has a high hole concentration over the entire area below the gate oxide film 14.
The channel stopper region 22 is provided to limit the range in which the channel 20 is formed, and is made of an N-type semiconductor as described above.

On the other hand, the substrate 4 has a channel stopper region 2
It is grounded via 2 to the ground. Therefore, the breakdown phenomenon is considered to occur along the route SS shown in FIG. 6A. A cross section along the path SS is shown in FIG. 9C.

As described above, the drain voltage VDD is applied to the drain region 8. The drain region 8 is P
The channel 20 is in conduction with the inverted channel 20 and is in contact with the channel stopper region 22 which is grounded.

Therefore, the contact portion between the channel 20 and the channel stopper region 22 has a PN reverse junction. Therefore, the breakdown voltage between the drain region 8 and the channel stopper region 22 (that is, the substrate 4) depends on the hole concentration of the channel 20 and the impurity concentration of the channel stopper region 22 at the contact portion between the channel 20 and the channel stopper region 22. Will be dependent.

On the other hand, as described above, the concentration of holes in the channel 20 at the contact portion is high. Therefore, in FIG. 9C, the breakdown phenomenon of the contact portion between the channel 20 and the channel stopper region 22 occurs before the contact portion between the drain 8 and the channel 20 is destroyed. Therefore, the breakdown voltage between the drain region 8 and the substrate 4 when the substrate 4 is grounded is lower than the breakdown voltage between the drain region 8 and the source region 6 when the substrate 4 is not grounded.

An object of the present invention is to improve such a conventional transistor and to improve the breakdown voltage between the drain and the substrate at the time of strong inversion.

[0022]

A transistor of the present invention is provided in a substrate and is formed in a mother region formed of a semiconductor of the first conductivity type, at a predetermined position in the mother region, and at a predetermined position from the upper surface of the mother region. A source region formed of a semiconductor of the second conductivity type that is provided to a depth, and provided in the mother region at a position that is a predetermined distance from the source region and a predetermined depth from the upper surface of the mother region. A drain region formed of a second conductivity type semiconductor, a part of the mother region, the gate region formed between the source region and the drain region and adjacent to the source region and the drain region, and the gate region A gate electrode provided on the upper surface of the gate electrode via an insulating film and formed in the mother region, and at a position adjacent to the end of the gate region that is not in contact with the source region and the drain region, a predetermined depth from the upper surface of the mother region. Provided across In a transistor having a channel stopper region formed of a semiconductor of the first conductivity type having an impurity concentration higher than that of the mother region, the transistor contacts the insulating film in the gate region when a voltage higher than a threshold voltage is applied to the gate electrode. It is characterized in that the carrier concentration of the channel generated in the portion in the vicinity of the contact portion with the channel stopper region is lower than the carrier concentration in the portion other than the vicinity of the channel contact portion.

In the transistor of the present invention , the thickness of the insulating film in contact with the channel in the vicinity of the contact portion is made thicker than the thickness of the insulating film in the portion in contact with the channel other than in the vicinity of the contact portion, so that the channel It is characterized in that the carrier concentration in the vicinity of the contact portion with the stopper region is lower than the carrier concentration in the portion other than the vicinity of the contact portion of the channel.

In the transistor of the present invention , the insulating film is a silicon oxide film, and the film thickness of the insulating film in contact with the channel in the vicinity of the contact portion is almost the same as the film thickness of the silicon oxide film for element isolation provided on the upper surface of the substrate. The feature is that they are the same.

[0025]

According to the transistor of the present invention , the carrier concentration in the vicinity of the contact portion with the channel stopper region of the channel generated in the portion of the gate region contacting the insulating film when a voltage higher than the threshold value is applied to the gate electrode It is characterized in that the carrier concentration is lower than the carrier concentration in the portion other than the vicinity of the contact portion.

That is, when a voltage higher than the threshold value is applied to the gate electrode, the channel is made of a semiconductor which is inverted from the first conductivity type to the second conductivity type and the semiconductor is made of the first conductivity type. The contact portion with the channel stopper region has a PN reverse junction. Therefore, by lowering the carrier concentration near the contact part of the channel,
The expansion of the depletion layer near the contact portion can be increased.

In the transistor of the present invention , the thickness of the insulating film in contact with the channel in the vicinity of the contact portion is made thicker than the thickness of the insulating film in the portion in contact with the channel other than in the vicinity of the contact portion, so that the channel It is characterized in that the carrier concentration in the vicinity of the contact portion with the stopper region is lower than the carrier concentration in the portion other than the vicinity of the contact portion of the channel.

Therefore, since the channel portion in contact with the thick insulating film has a large distance from the gate electrode, it is less susceptible to the voltage applied to the gate electrode, and the carrier concentration is low.

In the transistor of the present invention , the insulating film is a silicon oxide film, and the film thickness of the insulating film in contact with the channel in the vicinity of the contact portion is almost the same as the film thickness of the silicon oxide film for element isolation provided on the upper surface of the substrate. The feature is that they are the same.

Therefore, in the same step as the step of forming the silicon oxide film for element isolation, it is possible to form a thick insulating film in contact with the channel near the contact portion.

[0031]

1 and 2 show the structure of an aluminum gate MOS transistor which is a transistor according to an embodiment of the present invention. 2 shows the aluminum gate MOS transistor 3
2 is a schematic view of the upper part of FIG. 2 viewed from above, and FIG.
The cross section, FIG. 1B, is a schematic view of the MM cross section. The aluminum gate MOS transistor 32 is a P-channel aluminum gate MOS transistor.

As shown in FIG. 1A, the substrate 3 which is the mother region.
Reference numeral 4 is an N-type semiconductor which is a semiconductor of the first conductivity type.

A source region 36 is formed at a predetermined position on the substrate 34 from the upper surface of the substrate 34 to a predetermined depth. The source region 36 is P, which is a second conductivity type semiconductor.
Type semiconductor. A drain region 38 made of a P-type semiconductor is formed in the substrate 34 at a position spaced apart from the source region 36 by a predetermined distance from the upper surface of the substrate 34 to a predetermined depth.

The upper surfaces of the source region 36 and the drain region 38 are almost covered with a field oxide film 40 which is a silicon oxide film for element isolation.

Of the gate region 42 sandwiched between the source region 36 and the drain region 38, the upper surface of the vicinity 42a of the first contact portion which is the contact portion with the drain region 38 is the first extension 40a of the field oxide film 40. Is covered. The upper surface of the other part of the gate region 42 is covered with a gate oxide film 44 composed of a silicon oxide film thinner than the field oxide film.

A gate electrode 46 is provided on the upper surface of the gate region 42 with an extension 40a of the field oxide film 40 and a gate oxide film 44 interposed therebetween. The gate electrode 46 is
It is made of aluminum.

As shown in FIG. 2, a channel stopper region 52 is formed so as to surround the source region 36, the drain region 38 and the gate region 42. The channel stopper region 52 has an N concentration higher than that of the substrate 34.
Substrate 3 as shown in FIG. 1B.
It is formed from the upper surface of 4 to a predetermined depth.

As shown in FIG. 1B, in the gate region 42 sandwiched by the channel stopper regions 52, the upper surface of the second contact portion vicinity 42b, which is the contact portion with the channel stopper region 52, is the second surface of the field oxide film 40. It is covered by the extension 40b. The upper surface of the other part of the gate region 42 is covered with the gate oxide film 44.

Next, the operation of the aluminum gate MOS transistor 32 according to this embodiment will be described with reference to FIG. In the drain region 38 shown in FIG. 1A, the drain voltage V
When DD is applied and the source region 36, the gate electrode 46, and the substrate 34 are grounded (see FIG. 7A), the voltage VG equal to or higher than the threshold value is applied to the gate electrode 46, and the substrate 34 is grounded. If not (see Figure 7B)
In the same manner as in the conventional high breakdown voltage aluminum gate MOS transistor 2 described above,
Shows high breakdown voltage. This is similar to the above-mentioned conventional example in that the extension portion 40 of the field oxide film 40 is provided immediately above the vicinity 42a of the first contact portion.
This is because the formation of a reduces the concentration of the electric field in the vicinity 42a of the first contact portion.

Next, the operation when the voltage VG above the threshold value is applied to the gate electrode 46 and the substrate 34 is grounded (see FIG. 8A) will be described with reference to FIG. When a negative gate voltage VG equal to or higher than the threshold value is applied to the gate electrode 46, as in the case of the conventional high breakdown voltage aluminum gate MOS transistor 2 described above, the gate region 42 in contact with the gate oxide film 44 has a P type The resulting channel 50 is inverted.

As shown in FIG. 1A, drain region 38,
The breakdown voltage between the source regions 36 exhibits a high value due to the presence of the first extension 40a of the field oxide film 40, as in the case described above.

MM cross section in this state (see FIG. 2)
Is shown in FIG. 1B. As described above, in this embodiment, the gate region 4 sandwiched between the channel stopper regions 52 is used.
The upper surface of the second contact portion vicinity 42b, which is a contact portion with the channel stopper region 52, of the second electrode 2 is covered with the second extension portion 40b of the field oxide film 40, and the upper surfaces of other portions of the gate region 42 are , Covered with the gate oxide film 44.

Therefore, in the channel 50, the hole concentration is high below the thin gate oxide film 44 because it is easily affected by the voltage applied to the gate electrode 46.
On the other hand, the second extension portion 4 of the thick field oxide film 40
The vicinity of the second contact portion 42b, which is below 0b, is unlikely to be affected by the voltage applied to the gate electrode 46, and thus has a low hole concentration.

Further, as in the above-mentioned conventional example, the substrate 34 is grounded through the channel stopper region 52, so that the channel stopper region 52 made of an N-type semiconductor and the P-type inverted drain region are formed. The contact portion between the channel 38 and the channel 50 in the conductive state is a PN reverse junction.

Therefore, the breakdown voltage between the drain region 38 and the channel stopper region 52 (that is, the substrate 34) is determined by the concentration of holes in the channel 50 at the contact portion between the channel 50 and the impurity in the channel stopper region 52. Depends on concentration.

Therefore, as shown in FIG. 1B, in the aluminum gate MOS transistor 32 according to this embodiment in which the hole concentration in the vicinity of the second contact portion 42b is low, the hole concentration in the vicinity of the contact portion is high ( (See FIG. 9B) As compared with the conventional high breakdown voltage aluminum gate MOS transistor 2, the breakdown voltage between the drain region 38 and the substrate 34 at the time of strong inversion can be increased.

FIG. 8B is a diagram showing a part of the circuit when the aluminum gate MOS transistor according to this embodiment is used in the liquid crystal drive circuit. In a liquid crystal drive circuit, a high voltage may be applied to the gate with the source open, so that the breakdown voltage between the drain and the substrate becomes a particular problem. Therefore, the aluminum gate MO according to the present invention
The S-transistor is particularly effective for such a liquid crystal drive circuit.

Next, FIGS. 3 and 4 show a part of the flow of the manufacturing process of the aluminum gate MOS transistor 32 according to one embodiment of the present invention. 3A, 3C, 4E, and 4G are sectional views taken along line LL in FIG.
4F and 4H are views showing the MM cross section in FIG.

First, as in the case of the conventional aluminum gate MOS transistor, the field oxide film 40 is formed on the substrate 34, and the source region 36, the drain region 38, and the channel stopper region 52 are formed in the substrate 34. (See Figures 3A, B).

Next, on the field oxide film 40, the substrate 34 is formed.
An opening 48 for a gate reaching to is reached by etching (see FIGS. 3C and 3D). In this case, as shown in FIG. 3C,
The drain-side end 48a of the opening 48 is moved inward by a predetermined amount a from the end of the drain 38, and the stopper-side end 48b of the opening 48 is moved by a predetermined amount from the end of the channel stopper region 52, as shown in FIG. 3D. b Move it inside.

As shown in FIGS. 1A and 1B, the film thickness is increased above the first contact portion vicinity 42a and the second contact portion vicinity 42b in the gate region 42 by bringing the film thicknesses toward the inner side by the predetermined amounts a and b. First extension 40 of thick field oxide 40
a and the second extension 40b are left.

The predetermined amount a and the predetermined amount b are determined by the film thickness of the field oxide film 40, the width of the gate region 42, the purpose of use of the device, and the like. In the present embodiment, the predetermined amount a is about 2 μm, but the present invention is not limited to this value. Further, if the predetermined amount a and the predetermined amount b are increased, the breakdown voltage between the drain region 38 and the substrate 34 can be increased as described above, but the resistance (during the strong inversion) between the drain region 38 and the source region 36 ( Since the ON resistance) rises (see FIG. 1), it is desirable to determine the predetermined amount b according to the purpose of use from the balance between the breakdown voltage and the ON resistance.

In this step, it is only necessary to partially change the etching pattern used in the conventional aluminum gate MOS transistor. Therefore, high breakdown voltage can be realized without increasing the manufacturing cost.

Next, a gate oxide film 44 is formed at the bottom of the opening 48 by thermal oxidation (FIGS. 4E and 4F). In this embodiment, the field oxide film 40 has a thickness of about 7
000 angstroms, the thickness of the gate oxide film 44 is
It is about 900 Å. However, the present invention is not limited to these values.

Next, the field oxide film 40 is provided with a stopper opening 54, a source opening 56 and a drain opening 58 which reach the channel stopper region 52, the source region 36 and the drain region 38, respectively. After that, the ground electrode 60, the source electrode 62, the drain electrode 64, and the gate electrode 46 are formed on the respective openings and the gate oxide film 44, and finally, the entire upper surfaces thereof are covered with the protective film 66 (FIGS. 4G and 4H). ).

Next, referring to FIGS. 5A and 5B, an LDD type aluminum gate MO which is a transistor according to another embodiment of the present invention.
The structure of an S transistor is shown. FIG. 5A is a schematic view of the LDD type aluminum gate MOS transistor 72 seen from the upper surface, and FIG. 5B is a schematic view of the QQ cross section. The RR cross section is the same as that shown in FIG. 1B.

The LDD type aluminum gate MOS transistor 72 is a P channel aluminum gate MOS transistor. As shown in FIG. 5A, a source buffer region 74 and a drain buffer region 76 are provided so as to surround the drain region 38 and the source region 36. The source buffer region 74 and the drain buffer region 76 are made of a P-type semiconductor having an impurity concentration lower than that of the source region 38 and the drain region 36, and are provided especially for relaxing the electric field between the gate region 42 and the drain region 38. Has been.

The predetermined amount b is set with the end of the channel stopper region 52 as a reference, as in the above embodiment (see FIG. 1B). As described above, by providing the predetermined amount b, the breakdown voltage between the drain region 38 and the substrate 34 at the time of strong inversion can be increased as in the above-described embodiment.

Further, FIG. 5C shows a DDD type aluminum gate M.
6 is a schematic view of a QQ cross section of an OS transistor 82. FIG. The top view and the RR cross section are the same as those shown in FIGS. 5A and 1B. The present invention can be applied to the DDD type aluminum gate MOS transistor 82 in exactly the same manner as in the case of the LDD type aluminum gate MOS transistor 72 described above.

Incidentally, in the embodiment shown in FIG.
As shown in A, by providing a predetermined amount a, the upper surface of the vicinity of the first contact portion 42a of the gate region 42, which is the contact portion with the drain region 38, is extended by the first extension of the thick field oxide film 40. Although it is covered by the portion 40a, the present invention is not limited to this, and the first extension portion 40a is used.
It can also be applied when there is no.

For example, in the liquid crystal drive circuit shown in FIG. 8B, when a high voltage is applied to the gate, the electric field is originally not likely to be concentrated between the drain and the gate.
Therefore, the effect of alleviating the concentration of the electric field by the first extension 40a is low.

Therefore, in such a case, FIG.
As shown in FIG. 5, the drain region 38 and the substrate 34 are formed only by the second extension 40b of the field oxide film 40 provided on the upper surface of the vicinity 42b of the gate region 42 that is in contact with the channel stopper region 52. The breakdown voltage between them can be increased. However, by providing the first extension portion 40a as well, it is convenient that the breakdown voltage can be increased even when the gate voltage is low or the gate is grounded.

In each of the above-mentioned embodiments, FIG.
As shown in A and B, the upper surfaces of the vicinity 42a of the first contact portion and the vicinity 42b of the second contact portion are covered with the first extension portion 40a and the second extension portion 40b having the same film thickness as the field oxide film 40. The first extension 40a or the second extension 4
The film thickness of 0b may be formed to be different from the film thickness of the field oxide film 40.

However, by making these film thicknesses substantially the same, it is convenient because the first extension 40a and the second extension 40b can be formed at the same time in the step of forming the field oxide film 40.

Further, the insulating film for element isolation, the gate region 4
2 as a thick insulating film and a thin insulating film covering the upper part of the silicon oxide film (field oxide film 40, first extension portion 40).
Although the a, the second extension 40b and the gate oxide film 44) are used, an insulating film other than the silicon oxide film, for example, a silicon nitride film may be used for some or all of them.

Further, in each of the above-mentioned embodiments, FIG.
As shown in A and B, by covering the upper surfaces of the vicinity 42a of the first contact portion and the vicinity 42b of the second contact portion with the first extension portion 40a and the second extension portion 40b which are thicker than the gate oxide film 44, , 42a near the first contact portion and 4 near the second contact portion
Although the influence of the voltage applied to the gate electrode 46 on 2b is reduced, the present invention is not limited to this.

For example, the portions corresponding to the first extension portion 40a and the second extension portion 40b are deleted (the portion shown by the broken line in the drawing is the outline of the insulating film), and the gate electrode 46 itself is made small. The effect of the voltage applied to the gate electrode 46 on the vicinity 42a of the first contact portion and the vicinity 42b of the second contact portion can be reduced. However, by covering the upper surfaces of the vicinity 42a of the first contact portion and the vicinity 42b of the second contact portion with the first extension portion 40a and the second extension portion 40b having a large film thickness, the dimensional accuracy such as the predetermined amount a and the predetermined amount b is improved. It can be raised, which is convenient.

Further, in each of the above-mentioned embodiments, FIG.
As shown in FIG. 5A, the source region 36 and the drain region 3
8 and the gate region 42, the channel stopper region 52 is formed so as to surround the channel stopper region 5.
The shape of 2 is not limited to this, and it may be provided only in the vicinity of the contact portion with the gate region 42, for example. However, as shown in FIGS. 2 and 5A, by providing the source region 36, the drain region 38, and the gate region 42 so as to surround them, it is possible to prevent generation of a parasitic transistor between adjacent transistors. , Convenient.

Further, in each of the above-described embodiments, FIG.
As shown in FIGS. 5A and 5B, the case where the mother region is the substrate 34 itself has been described as an example. However, in addition to this, the mother region is formed over a certain range in the substrate. There is also a well area.

Further, in each of the above-described embodiments, the P-channel MOS transistor has been described as an example, but the present invention can be similarly applied to the N-channel MOS transistor.

Furthermore, the present invention is not limited to aluminum gate MOS transistors, but can be applied to transistors having gates of other types such as polysilicon and silicide.

[0072]

According to the transistor of the present invention , the carrier concentration in the vicinity of the contact portion with the channel stopper region of the channel generated in the portion of the gate region contacting the insulating film when a voltage higher than the threshold value is applied to the gate electrode. It is characterized in that the carrier concentration is lower than the carrier concentration in the portion other than the vicinity of the contact portion of the channel.

That is, when a voltage equal to or higher than the threshold value is applied to the gate electrode, the channel is made of a semiconductor which is inverted from the first conductivity type to the second conductivity type and the semiconductor is made of the first conductivity type. The contact portion with the channel stopper region has a PN reverse junction. Therefore, by lowering the carrier concentration near the contact portion of the channel, it is possible to increase the spread of the depletion layer near the contact portion.
Therefore, the breakdown voltage between the drain and the substrate at the time of strong inversion can be improved.

In the transistor of the present invention , the thickness of the insulating film in contact with the channel in the vicinity of the contact portion is made thicker than the thickness of the insulating film in the portion in contact with the channel other than in the vicinity of the contact portion, so that the channel It is characterized in that the carrier concentration in the vicinity of the contact portion with the stopper region is lower than the carrier concentration in the portion other than the vicinity of the contact portion of the channel.

That is, since the channel portion in contact with the thick insulating film has a large distance from the gate electrode, it is less likely to be affected by the voltage applied to the gate electrode, so that the carrier concentration becomes low. Therefore, the breakdown voltage between the drain and the substrate at the time of strong inversion can be improved by a simple method of thickening the insulating film.

In the transistor of the present invention , the insulating film is a silicon oxide film, and the film thickness of the insulating film in contact with the channel in the vicinity of the contact portion is almost the same as the film thickness of the silicon oxide film for element isolation provided on the upper surface of the substrate. The feature is that they are the same.

That is, in the same step as the step of forming a silicon oxide film for element isolation, it is possible to form a thick insulating film in contact with the channel near the contact portion. Therefore, since it is only necessary to partially change the conventional mask pattern, the breakdown voltage between the drain and the substrate at the time of strong inversion can be improved without increasing the manufacturing cost.

[Brief description of drawings]

FIG. 1 is a sectional view of a MOS transistor according to an embodiment of the present invention.

FIG. 2 is a top view of a MOS transistor according to an embodiment of the present invention.

FIG. 3 and

FIG. 4 is a diagram showing a part of a process of manufacturing a MOS transistor according to an embodiment of the present invention.

FIG. 5 is a diagram showing a structure of a MOS transistor according to another embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a conventional MOS transistor.

FIG. 7 and

FIG. 8 is a diagram showing an example of a circuit using a MOS transistor.

FIG. 9 is a diagram showing an operating state of a conventional MOS transistor.

[Explanation of symbols]

34 ... Substrate 38 ... Drain region 40 ... Field oxide film 40b ... Second extension 42 ... Gate area 42b ... near the second contact portion 46 .... Gate electrodes 50 ... Channel 52 ... Channel stopper area

Claims (2)

(57) [Claims] 1. A mother region provided in a substrate and formed of a semiconductor of the first conductivity type, provided at a predetermined position in the mother region over a predetermined depth from an upper surface of the mother region. A source region formed of a semiconductor of a second conductivity type, provided in the mother region at a position spaced a predetermined distance from the source region, and provided to a predetermined depth from the upper surface of the mother region, A drain region formed of a conductive type semiconductor, a part of the mother region, a gate region formed between the source region and the drain region and adjacent to the source region and the drain region, the gate A gate electrode provided on the upper surface of the region through an insulating film, formed in the mother region, at a position adjacent to an end of the gate region that is not in contact with the source region and the drain region, the mother region upon A channel stopper region formed of a semiconductor of the first conductivity type having an impurity concentration higher than that of the mother region, and a voltage higher than a threshold voltage is applied to the gate electrode. In such a case, the carrier concentration in the vicinity of the contact portion with the channel stopper region of the channel generated in the portion in contact with the insulating film in the gate region is lower than the carrier concentration in the portion other than the vicinity of the contact portion of the channel. The gate region sandwiched between the source region and the drain region.
First contact which is a contact portion with the drain region of the gate region
The upper surface near the area is covered with the first extension of the field oxide film.
Of the gate region sandwiched between the channel stopper regions
The second contact part, which is the contact part with the channel stopper region
Cover the upper surface in the vicinity with the second extension of the field oxide,
The upper surface of the other part of the gate region is covered with field acid.
A transistor characterized by being covered with a gate oxide film thinner than the oxide film . 2. The transistor according to claim 2, wherein the insulating film is a silicon oxide film, and the film thickness of the insulating film in contact with the channel near the contact portion is the silicon oxide for element isolation provided on the upper surface of the substrate. The film thickness is almost the same as the film thickness.