JPH02122648A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress droppage of source-drain voltage withstandability and to enable stable blow-off of only selected fuse by setting the width of a drain side dope layer in a first transistor region to a wide value regardless of the width of gate side wall. CONSTITUTION:A resist film 6c is formed to cover the gate side wall 8 at the drain side of a first transistor region 3a. Then As ions are injected into the resist film 6c, gate electrodes 5a, 5b and a gate side wall 8 to form a high impurity source-drain layer 9. 10<15>/cm<2> of dose is preferably employed. The width of drain side dopes layer 7c can be set to a wide value through this process regardless of the width of the gate side wall 8, and the width of the source side doped layer 7a can be set to a narrow width being determined by the width of the gate side wall 8. By such arrangement, a fuse transistor 3a having source-drain voltage withstandability higher than 14V can be integrated together with surrounding transistors 3b.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method of manufacturing a semiconductor device, and in particular to a method of integrating fuse transistors, to prevent a decrease in the source/drain breakdown voltage of the fuse transistor that occurs due to miniaturization, An object of the present invention is to provide a method for manufacturing a semiconductor device capable of stably blowing a fuse, comprising: - a first transistor region on a conductive semiconductor substrate and a second transistor region on a conductive semiconductor substrate;
A doped layer is formed in the first transistor region by forming a gate insulating film and a gate electrode in the transistor region, and selectively introducing an opposite conductivity type impurity while masking the second transistor region with a resist film. After removing the resist film, masking the first transistor region with a resist film and selectively introducing impurities of opposite conductivity type, the second transistor region is doped with impurities from the doped layer. After forming a highly doped layer and removing the resist film, the first and second layers are formed.
By forming gate sidewalls on the sidewalls of the gate electrode in the first transistor region, and masking the vicinity of the drain side of the gate electrode in the first transistor region with a resist film, and selectively introducing impurities of opposite conductivity type,
The method includes a step of forming source/drain diffusion layers such that the width of the doped layer on the drain side of the gate electrode is wider than the width of the doped layer on the source side.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of integrating fuse transistors.

[Conventional technology]

Semiconductor integrated circuits such as DRAMs having redundant circuits usually include a fuse circuit, and a method is used in which the use or non-use of the redundant circuit is set by selectively blowing out the fuses. FIG. 2 shows a fuse circuit. In the figure, in order to flow the current necessary to blow the fuse 32, the fuse transistor 3
While applying a control signal to the gate electrode of 1,
A source-drain voltage of 4V must be applied. Therefore, in order to blow only the selected fuse and not blow out the unselected fuses, the source/drain breakdown voltage of the fuse transistor 31 needs to be at least 14V or more. Further, although peripheral transistors such as a sense amplifier and an output circuit are formed on the same semiconductor substrate in the semiconductor integrated circuit, the source-drain voltage applied to these peripheral transistors is approximately 5V at most.
A breakdown voltage of 10V or higher is not required. On the other hand, while fuse transistors do not require high speed, peripheral transistors are required to have high speed.

As described above, although fuse transistors and peripheral transistors have different required characteristics, conventionally they have been formed by the same process and have the same structure.

[Problem to be solved by the invention]

However, as the demand for smaller and faster semiconductor devices has increased, the dimensions of each part of transistors have been made smaller (and source/drain breakdown voltages have decreased, causing various problems).

FIG. 3 is a schematic cross-sectional view showing the main parts of a conventional transistor, in which 21 is a semiconductor substrate, 22 is a gate insulating film,
23 is a gate electrode, 24 is a gate side wall, 25 is a source/drain layer with a high impurity concentration, and 26 is a doped layer with a low impurity concentration. With reference to the figure, the following will briefly explain how the source/drain breakdown voltage decreases with miniaturization.

The transistor shown in the figure has a so-called LDD (lightly doped drain) structure. That is,
A doped layer 26 with a low impurity is provided at the end of the channel to prevent the source/drain layer 25 with a high impurity concentration from coming into direct contact with the channel, thereby relaxing the electric field in the drain depletion layer and improving the source/drain breakdown voltage. I'm letting you do it. However, the doped layer 26 is formed by diffusion using the gate electrode 23 as a mask, and the source/drain layer 25 is formed by diffusion using the gate electrode 23 and the gate sidewall 24 as a mask. 25 extends to the doped layer 26 side and erodes it,
The width of the doped layer 26 becomes narrower. As a result, the electric field within the drain depletion layer is not sufficiently relaxed, resulting in a decrease in source-drain breakdown voltage. On the other hand, since the width of the gate sidewall 24 depends on the thickness of the gate electrode 23, it becomes narrower as the gate electrode 23 becomes thinner, and as a result, the width of the doped layer 26 becomes narrower and the electric field in the drain depletion layer becomes stronger. Become. Furthermore, by making the gate oxide film 4 thinner, the electric field in the drain depletion layer becomes stronger. Therefore, D.R.
As the gate electrode 23 and gate oxide film 4 become thinner due to miniaturization of AM, etc., the source/drain breakdown voltage of the fuse transistor also decreases, and breakdown occurs even at the voltage of 12 to 14 V required to blow the fuse. This results in the problem that unselected fuses may also be blown.

Therefore, the present invention aims to prevent the source/drain breakdown voltage of fuse transistors from decreasing due to miniaturization of DRAMs, etc.
An object of the present invention is to provide a method for manufacturing a semiconductor device that can stably blow out a fuse.

[Means to solve the problem]

The above-mentioned problems include - a step of forming a gate insulating film and a gate electrode in a first transistor region and a second transistor region on a conductivity type semiconductor substrate; and a step of masking the second transistor region with a resist film and forming a gate electrode of an opposite conductivity type. A step of forming a doped layer in the first transistor region by selectively introducing impurities, and a step of forming a doped layer in the first transistor region after removing the resist film.
forming a doped layer having a higher impurity concentration than the doped layer in the second transistor region by masking the transistor region with a resist film and selectively introducing impurities of opposite conductivity type; After removing
A step of forming gate sidewalls on the sidewalls of the gate electrodes in the first and second transistor regions, and masking the vicinity of the drain side of the gate electrodes in the first transistor region with a resist film to selectively remove impurities of opposite conductivity type. A semiconductor comprising the step of forming a source/drain diffusion layer so that the width of the doped layer on the drain side of the gate electrode is wider than the width of the doped layer on the source side. The problem is solved by a method of manufacturing the device.

[For production]

According to the present invention, the width of the doped layer on the drain side in the first transistor region can be set to a wide value regardless of the width of the gate sidewall. Therefore, even if the width of the gate sidewall is narrow, the doped layer on the drain side will not be absorbed by the source/drain diffusion layer, and therefore the electric field in the drain depletion layer will not become excessive. Furthermore, since the doped layer in the first transistor region has a lower impurity concentration than the doped layer in the second transistor region, the doped layer in the first transistor region has a lower impurity concentration than the doped layer in the second transistor region. , the electric field within the drain depletion layer is further relaxed.

The effect of electric field relaxation as described above prevents the source/drain breakdown voltage of the first transistor region from decreasing, and
In the second transistor region, since a conventional LDD structure is used, high-speed performance does not deteriorate. Furthermore, since the width of the doped layer on the source side of the first transistor region is set in a self-aligned manner to a narrow value determined by the width of the gate sidewall, the current drive capability does not decrease even in the first transistor region. do not have.

〔Example〕

FIG. 1 is a schematic sectional view for explaining one embodiment of the present invention.

First, as shown in FIG. 5A, a gate insulating film 4 and gate electrodes 5a, 5b are formed on the fuse transistor region 3a and the peripheral transistor region 3b on the p-type Si substrate 1.
form. The gate insulating film 4 is, for example, a p-type Si substrate 1.
It is a 5i02 film obtained by thermally oxidizing the gate electrode 5a,
5b is made of polysilicon formed by CVD, for example.

Next, as shown in FIG. 5B, the peripheral transistor region 3b is covered with a resist film 6b using a normal photolithography method, and the fuse transistor region is formed by P ion implantation using the resist film 6b and the gate electrode 5a as a mask. By selectively introducing P ions into 3a, the doped layer 7
a, form 7c. The dose amount was 10"/am".

Next, after removing the resist film 6b, as shown in FIG.
a, and by ion implantation of P, the peripheral transistor region 3 is formed using the resist film 6a and the gate electrode 15b as a mask.
P ions are selectively introduced into the doped layer 7b to form a doped layer 7b. The dose at this time is 10% higher than the above dose.
"/cm2, and the impurity concentration of the doped layers ?a, 7c of the first transistor region 3a was set to a lower value than the impurity concentration of the doped layer 7b of the second transistor region 3b.

Next, after removing the resist film 6a, a SiO2 film is deposited over the entire surface of the substrate by the CVD method, and the 5i02 film is deposited thicker on the side walls of the gate electrodes 5a and 5b than on other flat areas. Therefore, by simply etching the SiO□ film using the RIE method, gate sidewalls 8 having a width determined by the thickness of the gate electrodes are formed on the sidewalls of the gate electrodes 5a and 5b in a self-aligned manner, as shown in (6) of the same figure. be done.

Next, as shown in FIG. 3E, a resist film 6c is formed to cover the gate sidewall 8 on the drain side of the first transistor region 3a. Thereafter, using the resist film 6c, gate electrodes 5a, 5b, and gate sidewalls 8 as masks, As
ion implantation is performed to form source/drain layers 9 with high impurity content. The dose amount at this time was 10''/cm''. Through this step, the width of the doped layer 7c on the drain side can be set wide regardless of the width of the gate sidewall 8, and the width of the doped layer 7a on the source side can be set to a narrow value determined by the width of the gate sidewall 8. Finally, as shown in the same figure (f), PSGSiO1 is used as an interlayer insulating film.
A contact hole is formed over the entire surface of the substrate. Then, a wiring layer of Al film 11 is formed through the contact hole.

By the above method, it was possible to integrate a fuse transistor with a source-drain breakdown voltage of 14 V or more together with peripheral transistors.

〔Effect of the invention〕

According to the present invention, it is possible to suppress a decrease in the source/drain breakdown voltage of a fuse transistor that occurs with the miniaturization of DRAMs and the like, and it is possible to stably blow only selected fuses.

[Brief explanation of drawings]

FIGS. 1(a) to 1(f) are process diagrams showing embodiments of the present invention,
FIG. 2 is a diagram showing a fuse circuit, and FIG. 3 is a diagram showing problems with a conventional transistor. In the figure, 1.21 is a semiconductor substrate, 2 is a field oxide film, 3a is a first transistor region, 3b is a second transistor region, 4.22 is a gate insulating film, 5a, 5b, 23 are gate electrodes, 6a , 6b, 6c are resist films, ? a, 7b, 7c, and 26 are doped layers; 8.24 is a gate side wall; 9.25 is a source/drain layer; 10 is a PSG film; 11 is an A1 film; 31 is a fuse transistor; and 32 is a fuse. Diagram (¥41) The book is groaning It's r Sawa Shi row E demonstration aT[T]

Claims (1)

[Claims] A gate insulating film (4) and gate electrodes (5a, 5b) are formed in a first transistor region (3a) and a second transistor region (3b) on a semiconductor substrate (1) of one conductivity type. and forming the second transistor region (3b) with a resist film (6b).
By selectively introducing impurities of opposite conductivity type while masking with
7a, 7c), and after removing the resist film (6b), selectively introducing impurities of opposite conductivity type by masking the first transistor region (3a) with the resist film (6a). As a result, the doped layers (7a, 7) are applied to the second transistor region (3b).
c) forming a doped layer (7b) with a higher impurity concentration, and after removing the resist film (6a), forming a gate electrode (7b) in the first and second transistor regions (3a, 3b);
forming gate sidewalls (8) on the sidewalls of the first transistor region (3a);
By masking the vicinity of the drain side of the gate electrode (5a) with a resist film (6c) and selectively introducing impurities of opposite conductivity type, the doped layer (7c) on the drain side of the gate electrode (5a) is formed.
) is wider than the width of the doped layer (7a) on the source side.