KR100365483B1 - Method for manufacturing semiconductor apparatus - Google Patents

Abstract

In the case of forming a P-type diffusion region continuous with the source / drain regions in the N-well, boron fluoride is implanted without covering the P-well with a mask. Further, in the case of forming the N-type diffusion region continuous to the source / drain region in the P-well, phosphorus is implanted over the N-well by covering it with the mask. Here, the dosage of phosphorus is smaller than the dosage of boron fluoride injected without using a mask.

Description

[0001] METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS [0002]

The present invention relates to a contact process, and more particularly, to a method of manufacturing a semiconductor device used in a re-diffusion ion implantation process.

2. Description of the Related Art In recent years, the contact diameter has been reduced in accordance with miniaturization of a semiconductor device, and moreover, a contact in which a part of a contact is placed on a field insulating film (oxide film) However, since the contact area between the contact and the diffusion layer is reduced by placing a part of the contact on the field insulating film, the resistance of the contact is increased and a junction leakage occurs. Here, after the contact is opened to drop the contact resistance, ion implantation for re-diffusion is required to form a re-diffusion layer which is in contact with the contact continuously with the diffusion layer. Hereinafter, the N ⁺ type and P ⁺ type re-diffusion regions will be described.

30, an N well 16 and a P well 17 are formed in the semiconductor substrate 11. A plurality of field insulating films 24 are formed on the surfaces of the N wells 16 and the P wells 17, Is formed. A gate electrode 31a is formed on the N well 16 and the P well 17 via a gate insulating film not shown and a wiring such as a pass gate electrode 31b is formed on the field insulating film 24. A P-type source / drain region 36a is formed in the N-well 16 located on both sides of the gate electrode 31a, and a P-type source / drain region 36a is formed in the P-well 17 located on both sides of the gate electrode 31a An N-type source / drain region 39a is formed. On the entire surface of the semiconductor substrate 11, an interlayer insulating film 40 made of CVDSiO ₂ film containing phosphorus or boron is formed. The surface of the interlayer insulating film 40 is planarized by the CMP (Chemical Mechanical Polish) method. A plurality of contact holes 42 exposing the surfaces of the P-type source / drain region 36a, the N-type source / drain region 39a, and the pass gate electrode 31b are formed in the interlayer insulating film 40 have.

Thereafter, a patterned resist 53 is formed on the entire surface, and boron fluoride (BF ₂ ), for example, is implanted into the N well 16 from the contact hole 42. As a result, the P-type redistribution region 43 is formed on the surface of the N-well 16 at the bottom of the contact hole 42. Thereafter, the resist 53 is removed.

Next, as shown in Fig. 31, a resist 54 is formed and patterned. Phosphorus (P), for example, is implanted into the P-well 17 from the contact hole 42 by using the patterned resist 54. [ Thereby, the N-type redistribution region 45 is formed on the surface of the P-well 17 at the bottom of the contact hole 42. [

As described above, the contact resistance is reduced by forming the P-type redistribution region 43 and the N-type redistiff diffusion region 45 at the bottom of the contact hole 42 to enlarge the contact area with the contact.

However, in the case of forming the P-type redistribution region 43 in the conventional manufacturing process, the N-well 16 is formed by covering the P-well 17 with a mask and forming the N- The image is covered with a mask. That is, a process of forming and removing the resist 53, 54 as a mask is generated. Therefore, there is a problem that the ion implantation process becomes long. Further, dusts are easily generated by forming and removing the resists 53 and 54, resulting in a reduction in the yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device in which the ion implantation process is facilitated.

1 is a sectional view of a manufacturing process of a semiconductor device according to a first embodiment of the present invention,

FIG. 2 is a sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention,

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, continuing from FIG. 2,

4 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention,

FIG. 5 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, continuing from FIG. 4,

FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention,

FIG. 7 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, continuing from FIG. 6,

8 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention following FIG. 7,

FIG. 9 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention,

FIG. 10 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention,

11 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention,

FIG. 12 is a sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 11,

FIG. 13 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention following FIG. 12,

FIG. 14 is a sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 13,

FIG. 15 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 14,

FIG. 16 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, subsequent to FIG. 15,

FIG. 17 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 16,

FIG. 18 is a sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 17,

FIG. 19 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 18,

FIG. 20 is a sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 19,

FIG. 21 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 20,

FIG. 22 is a cross-sectional view of the manufacturing process of the semiconductor device according to the first embodiment of the present invention, which follows FIG. 21,

23 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment of the present invention following FIG. 16,

FIG. 24 is a cross-sectional view of the manufacturing process of the semiconductor device according to the second embodiment of the present invention continued from FIG. 23,

FIG. 25 is a cross-sectional view of the manufacturing process of the semiconductor device according to the third embodiment of the present invention, which follows FIG. 16,

FIG. 26 is a cross-sectional view of the manufacturing process of the semiconductor device according to the third embodiment of the present invention continued from FIG. 25,

FIG. 27 is a cross-sectional view of the manufacturing process of the semiconductor device according to the third embodiment of the present invention continued from FIG. 25,

Fig. 28 is a view showing the dose amount and the condition of the acceleration voltage when forming the diffusion region, Fig.

29 is a schematic view of a manufacturing process for comparing the conventional and the present invention,

30 is a cross-sectional view of a manufacturing process of a semiconductor device according to the prior art,

31 is a cross-sectional view of a manufacturing process of a semiconductor device according to the prior art following FIG.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first well region of a first conductivity type and a second well region of a second conductivity type in a surface region of a semiconductor substrate; First and second transistors each having a first and a second diffusion layer of a first conductivity type are formed in a second well region, and at least the first and second diffusion layers of the first and second transistors are formed, A method for manufacturing a semiconductor device having an insulating film with exposed contact holes, comprising the steps of: injecting a first ion from the contact hole to the entire surface of the semiconductor substrate; Forming a first re-diffusion region of a first conductivity type and a second conductivity type in a second well region of the semiconductor substrate; forming a first re- Ions are implanted into the second well region, And forming a second redistribution region of a first conductivity type that is continuous with the second diffusion layer. The second ion implantation condition in the case of forming the second redistiffance region is that the acceleration voltage is 30 to 50 keV , And a dose amount of 6.0 × 10 ^{14 to} 1.5 × 10 ¹⁵ cm ^-2 .

In the case of forming the first redistribution region, it is preferable that the first ion is implanted at an acceleration voltage of 60 keV and a dose amount of 3.0 x 10 ¹⁵ cm ^-2 .

A second semiconductor device manufacturing method according to the present invention is characterized in that a first well region of a first conductivity type and a second well region of a second conductivity type are formed in a surface region of a semiconductor substrate, First and second transistors each having first and second diffusion layers of a first conductivity type and second and first conductivity type are formed respectively and at least a contact hole for exposing the first and second diffusion layers of the first and second transistors A method of manufacturing a semiconductor device having an insulating film, the method comprising: forming a mask covering the second well region of the semiconductor substrate; implanting first ions into the first well region from the contact hole using the mask A step of forming a first re-diffusion region of a second conductivity type continuous with the first diffusion region in the first well region, a step of removing the mask, and a step of forming a second diffusion region of the second conductivity type on the entire surface of the semiconductor substrate from the contact hole, Ions are implanted into the second well region And forming a second redistribution region of the first conductivity type that is continuous with the second diffusion layer, wherein the dose amount when the second ions are implanted in the step of forming the second redistribution region is Diffusion layer is smaller than the dose when the first ions are implanted in the step of forming the first re-diffusion layer.

In the production method of the second semiconductor device, wherein the second ion implantation conditions in the case of forming a second re-diffusion region is the accelerating voltage is from 30 to 50keV, a dose amount is ^{6.0 × 10 14 ~ 1.5 × 10} 15 cm - ² , and the first ion is implanted under the conditions of an acceleration voltage of 60 keV and a dose of 3.0 x 10 ¹⁵ cm ^-2 when the first redistribution region is formed.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

The first embodiment is a semiconductor device having a stacked structure and is characterized in that ion implantation is performed without using a mask at the time of forming the P-type redistribution region 43. [

As shown in FIG. 1, a silicon oxide film 12 is formed on, for example, a P-type semiconductor substrate 11. Next, ions are implanted to form the N-type impurity region 13 on the surface of the semiconductor substrate 11. [ In this case, the ion implantation conditions are, for example, when the kind of ions is phosphorous (P), the acceleration voltage is 160 keV, and the dose is 5.6 x 10 ¹² cm ^-2 .

As shown in Fig. 2, a resist 14 is formed on the silicon oxide film 12 and patterned. Ions are implanted by using the patterned resist 14 as a mask to form a P-type impurity region 15 on the surface of the semiconductor substrate 11. [ In this case, the ion implantation conditions are, for example, when the ion is boron (B), the acceleration voltage is 160 keV and the dose is 1.55 x 10 ¹³ cm ^-2 . Thereafter, the resist 14 is removed.

Impurities in the N type impurity region 13 and the P type impurity region 15 are diffused to form the N well 16 and the P well 17 on the surface of the semiconductor substrate 11 as shown in FIG. Thereafter, the silicon oxide film 12 is removed.

A silicon oxide film 18 is formed on the semiconductor substrate 11 and a first polysilicon film 19 is formed on the silicon oxide film 18. Then, A silicon nitride film 20 is formed on the first polysilicon film 19 and a second polysilicon film 21 is formed on the silicon nitride film 20. A resist 22 is formed on the second polysilicon film 21 and patterned. The second polysilicon film 21 is removed by RIE (Reactive Ion Etching) using the patterned resist 22 as a mask. Thereafter, the resist 22 is removed.

As shown in Fig. 5, the second polysilicon film 21 is oxidized, and the polysilicon film 23 is formed. The silicon nitride film 20 is removed by, for example, RIE using the oxidized polysilicon film 23 as a mask. Thereafter, the polysilicon film 23 is removed by, for example, wet etching or the like.

The field insulating film 24 is formed on the surface of the semiconductor substrate 11 on which the silicon nitride film 20 is not formed, as shown in Fig.

The silicon nitride film 20, the first polysilicon film 19 and the silicon oxide film 18 are removed by CDE (chemical dry etching) as shown in Fig. 7, and the field insulating film 24 is not formed The surfaces of the N well 16 and the P well 17 are exposed.

A gate oxide film 25 is formed on the entire surface and a polysilicon film 26 is formed on the gate oxide film 25 as shown in Fig. Next, a tungsten silicon (WSi) film 27 is formed on the polysilicon film 26 by, for example, sputtering. A silicon oxide film 28 is formed on the tungsten silicon film 27 and a silicon nitride film 29 is formed on the silicon oxide film 28. A resist 30 is formed on the silicon nitride film 29 and patterned.

The silicon nitride film 29, the silicon oxide film 28, the tungsten silicon film 27 and the polysilicon film 26 are removed by RIE, for example, by using the patterned resist 30 as a mask do. As a result, the gate electrode 31 of the P-channel transistor and the N-channel transistor is formed. Thereafter, the resist 30 is removed, and wet processing is performed on the entire surface.

10, a silicon oxide film 32 is formed on the entire surface, and a polysilicon film is formed on the silicon oxide film 32. [ Thereafter, the polysilicon film is removed by RIE, for example, and a gate side wall 33 made of a polysilicon film is formed on the side surface of the gate electrode 31.

As shown in Fig. 11, a resist 34 is formed on the entire surface and is patterned. Ions are implanted using this patterned resist 34 as a mask and a P-type high-concentration source / drain region 35 is formed in the surface region of the N-well 16. [ At this time, when the ion is boron fluoride (BF ₂ ), for example, the acceleration voltage is 45 keV and the dosage is 3.0 x 10 ¹⁵ cm ^-2 .

As shown in Fig. 12, the gate side wall 33 is removed by CDE, for example. Next, ions are implanted and a source / drain region 36 having a lower concentration than that of the P-type source / drain region 35 is formed in the surface region of the N-well 16. At this time, the conditions of the ion implantation are, for example, when the kind of ions is boron fluoride, the acceleration voltage is 35 keV, and the dosage is 1.0 x 10 ¹⁴ cm ^-2 . Thereafter, the resist 34 is removed.

As shown in Fig. 13, a resist 37 is formed on the entire surface and is patterned. Ions are implanted using the patterned resist 37 as a mask to form an N-type high-concentration source / drain region 38 in the surface region of the P-well 17. [ At this time, the conditions for the ion implantation are, for example, in the case where the kind of the ions is arsenic (As), the acceleration voltage is 60 keV, and the dosage is 5.0 × 10 ¹⁵ cm ^-2 .

As shown in Fig. 14, the gate side wall 33 is removed by CDE, for example. Next, phosphorus is introduced as an ion implantation, and arsenic is introduced thereafter. As a result, a source / drain region 39 having a lower concentration than that of the N-type source / drain region 38 is formed in the surface region of the P- At this time, in the case of phosphorous, the acceleration voltage is 40 keV and the dose amount is 4.0 × 10 ¹³ cm ^-2 in the case of phosphorus. In the case of arsenic, the acceleration voltage is 60 keV and the dose amount is 2.0 × 10 ¹⁴ cm ^-2 . Thereafter, the resist 37 is removed, and the entire surface is annealed.

As shown in FIG. 15, an interlayer insulating film 40 made of a CVDSiO ₂ film containing phosphorus or boron is formed on the entire surface, and then the interlayer insulating film 40 is planarized by, for example, CMP. Furthermore, the interlayer insulating film 40 is not limited to the CVDSiO ₂ film containing phosphorus or boron, and may be aluminum, BPSG, or the like.

In the above process, the P-type high-concentration and low-concentration source / drain regions 35 and 36 are used as the P-type source / drain regions 36a and the N-type high- Drain region 39a. The gate electrode 31 is denoted by 31a and the pass gate electrode formed on the field insulating film 24 at the time of forming the gate electrode 31 is denoted by 31b.

As shown in Fig. 16, a resist 41 is formed on the interlayer insulating film 40 and patterned. The interlayer insulating film 40 is etched, for example, by RIE using the patterned resist 41 as a mask. As a result, the surfaces of the source / drain regions 36a and 39a and the pass gate electrode 31b are exposed, and the contact hole 42 is formed. Thereafter, the resist 41 is removed. Furthermore, the mask for forming the contact hole 42 may use a different resist on the field insulating film 24 and the source / drain diffusion regions 36a and 39a. The shape, size, length, etc. of the contact hole 42 can be variously modified as long as the effect of the present invention is not impaired.

17, ions are injected from the contact holes 42 without masking the P-wells 17, so that source / drain regions (not shown) are formed on the surface of the N-well 16 at the bottom of the contact holes 42 36a and a continuous P-type redistribution region 43 are formed. The conditions for this ion implantation are, for example, when the kind of ions is boron fluoride, the acceleration voltage is 60 keV, and the dosage is 3.0 x 10 ¹⁵ cm ^-2 . At this time, although ions are also implanted into the P-well 17, the P-type re-diffusion region is not formed by the conditions described later (shown in FIG. 28).

As shown in Fig. 18, a resist 44 is formed on the interlayer insulating film 40 and patterned. Ions are injected from the contact hole 42 by using the patterned resist 44 as a mask to form a contact hole 42 in the form of a continuous N-type contact with the source / drain region 39a on the surface of the P- A rediffusion region 45 is formed. At this time, the ion implantation conditions are, for example, in the case where the kind of ions is phosphorus, the acceleration voltage is 40 keV, and the dosage is 8.0 × 10 ¹⁴ cm ^-2 . Thereafter, the resist 44 is removed.

As shown in Fig. 19, the titanium nitride film 46 is formed on the entire surface by, for example, sputtering. Next, a tungsten (W) film 47 is formed on the titanium nitride film 46 by CVD (Chemical Vapor Deposition), and the contact hole 42 is buried. Thereafter, the tungsten film 47 is planarized by CDE, and the surface of the titanium nitride film 46 is exposed.

An aluminum film 48 is formed on the entire surface by sputtering, for example, and a titanium nitride film 49 is formed on the aluminum film 48 as shown in Fig. Next, a patterned resist (not shown) is formed on the titanium nitride film 49, and the titanium nitride films 46, 49 and the aluminum film 48 are removed by RIE, for example, And a wiring connected to the tungsten film 47 in the contact hole 42 is formed.

As shown in FIG. 21, for example, a first TEOS (Tetra Ethyl Ortho Silicate) film 50 is formed on the entire surface, and the first TEOS film 50 is planarized by CMP. Thereafter, the second TEOS film 51 is formed on the first TEOS film 50.

Finally, vias and wiring are formed to form a three-layer metal wiring as shown in Fig.

FIG. 28 shows ion implantation conditions at the time of forming the re-diffusion region 45 shown in FIG. In Fig. 28, the abscissa is the dose amount, and the ordinate is the acceleration voltage.

As shown in Fig. 28, region A shows a region where a good contact can not be obtained because of high contact resistance. The region B shows a region where junction leakage occurs because the dose amount of ion implantation is high. The region C shows a region where the process margin is good. That is, in the present embodiment, the ion implantation conditions in the case of forming the re-diffusion region 45 are such that the acceleration voltage is 30 to 50 keV, the dose amount is 6.0 × 10 ¹⁴ to 1.5 × 10 ¹⁵ cm ^-2 (region C) The best case is when the acceleration voltage is 40 keV and the dose amount is 8.0 × 10 ¹⁴ cm ^-2 .

According to the first embodiment, when the P-type redistiffance region 43 is formed on the surface of the N-well 16, it is not necessary to form a mask on the P-well 17.

Therefore, in the case of forming the N-type diffused region 43 like the process flow shown in FIG. 29, ions are implanted into the entire surface without forming a mask. Therefore, in the conventional manufacturing process, it is possible to omit three steps of resist coating, exposure, development (n ⁺ SAC / PEP), resist ashing (asher) The process becomes easy.

Further, since the occurrence of dust can be reduced by reducing the number of times of removing the mask, the yield can be improved.

In the first embodiment, the order of the process shown in Fig. 17 and the process shown in Fig. 18 may be changed. Even in this case, the same effect as the above-mentioned effect is obtained.

Second Embodiment

The second embodiment differs from the first embodiment in that an N-type redistiffusion region is formed and then a P-type redistribution region is formed. In the second embodiment, description of steps similar to those of the first embodiment will be omitted, and only other steps will be described.

First, as shown in Figs. 1 to 16, a contact hole 42 is formed similarly to the first embodiment. Thereafter, the resist 41 is removed.

23, ions are injected from the contact hole 42 without masking the N well 16 to form a source / drain (not shown) on the surface of the P well 17 at the bottom of the contact hole 42, The N-type redistribution region 45 continuous with the region 39a is formed. The conditions for this ion implantation are, for example, in the case where the kind of ions is phosphorus, the acceleration voltage is 40 keV, and the dose amount is 8.0 x 10 ¹⁴ cm ^-2 .

24, a resist 44 is formed on the interlayer insulating film 40 and patterned. Ions are injected from the contact hole 42 by using the patterned resist 44 as a mask so that a P-type continuous with the source / drain region 36a is formed on the surface of the N well 16 at the bottom of the contact hole 42, A re-diffusion region 43 is formed. At this time, the conditions of the ion implantation are, for example, when the kind of ions is boron fluoride, the acceleration voltage is 60 keV, and the dosage is 3.0 x 10 ¹⁵ cm ^-2 . Thereafter, the resist 44 is removed. Moreover, the P-type redistribution region 43 and the N-type redistribution region 45 are formed by the above-described Conditions 1 and 2. [

Thereafter, as in the first embodiment, as shown in Figs. 19 to 22, a semiconductor device having a laminated structure is formed.

According to the second embodiment, an effect similar to that of the first embodiment can be obtained even when the kind of ions implanted in the formation of the re-diffusion region is changed.

Third Embodiment

In the third embodiment, unlike the first embodiment, a P-type redistribution region is formed by using a mask, and an N-type redistiffusion region is formed without using a mask. In the third embodiment, description of the same steps as those of the first embodiment will be omitted and only other steps will be described.

First, as shown in Figs. 1 to 16, a contact hole 42 is formed similarly to the first embodiment. Thereafter, the resist 41 is removed.

Next, as shown in Fig. 25, a resist 53 is formed on the interlayer insulating film 40 and patterned. Thereafter, ions are implanted from the contact hole 42 to form a P-type diffused region 43 continuous with the source / drain region 36a on the surface of the N-well 16 at the bottom of the contact hole 42 . The conditions for this ion implantation are, for example, when the kind of ions is boron fluoride, the acceleration voltage is 60 keV, and the dosage is 3.0 x 10 ¹⁵ cm ^-2 . Thereafter, the resist 53 is removed.

26, ions are injected from the contact hole 42 without using the N well 16 as a mask so that the source / drain region (the source / drain region) is formed on the surface of the P well 17 at the bottom of the contact hole 42 39a and the N-type redistribution regions 45 are formed. The conditions for this ion implantation are, for example, in the case where the kind of ions is phosphorus, the acceleration voltage is 40 keV, and the dose amount is 8.0 x 10 ¹⁴ cm ^-2 . Thereafter, RTA (Rapid Thermal Annealing) is performed. Moreover, the P-type redistribution region 43 and the N-type redistribution region 45 are formed by the above-described Conditions 1 and 2. [ Although the ions are also implanted into the pass gate electrode 31b, if ions are implanted under the conditions 1 and 2 described above, there is no deterioration of the performance of the device.

Thereafter, as shown in Figs. 19 to 22, a semiconductor device having a laminated structure is formed similarly to the first embodiment.

According to the third embodiment, the same effects as those of the first embodiment can be obtained. Furthermore, after forming the P-type redistribution region 43, the N-type redistiff diffusion region 45 can be formed without masking the pass gate electrode 31b. Therefore, since the step of forming the mask of the pass gate electrode 31b can be omitted, the manufacturing process is facilitated.

27, after the resist 52 is formed on the pass gate electrode 31b, ion implantation for forming the N-type re-diffusion region 45 may be performed. In this case, the same effect as that of the first embodiment can be obtained.

In the first to third embodiments, the masking process in the case of forming the P-type diffused region 43 or the N-type diffused region 45 by using the conditions 1 and 2 can be saved, For example, when the source / drain regions are formed using the conditions 1 or 2, it is possible to reduce the mask process in the case of forming the source / drain regions.

The kind of ions in the case of forming the re-diffusion regions 43 and 45 is not limited to P or BF ₂ . When the kind of ions is changed, the numerical value of the region C is variously changed to such an extent as to prevent the increase of the contact resistance and the generation of the leakage current.

As described above, according to the present invention, it becomes possible to provide a method of manufacturing a semiconductor device in which the ion implantation process is facilitated.

Claims (7)

A first well region of the first conductivity type and a second well region of the second conductivity type are formed in the surface region of the semiconductor substrate and a first and second well regions of the second conductivity type are formed in the first and second well regions, The method comprising the steps of: forming first and second transistors each having a first diffusion layer and a second diffusion layer, and forming at least an insulation film having contact holes exposing the first and second diffusion layers of the first and second transistors, Implanting a first ion into the entire surface of the semiconductor substrate from the contact hole to form a first re-diffusion region of a second conductivity type in succession to the first diffusion region in the first well region; A step of forming a mask covering the first well region of the semiconductor substrate, And a step of implanting second ions from the contact holes into the second well region using the mask and forming a second re-diffusion region of the first conductivity type in succession to the second diffusion region in the second well region Lt; / RTI > Wherein the second ion implantation condition for forming the second redistribution region is an acceleration voltage of 30 to 50 keV and a dose amount of 6.0 × 10 ^{14 to} 1.5 × 10 ¹⁵ cm ^-2 . The manufacturing method of a semiconductor device according to claim 1, wherein the first ion implantation condition for forming the first redistribution region is an acceleration voltage of 60 keV and a dose amount of 3.0 x 10 ¹⁵ cm ^-2 . The method according to claim 1, wherein the first ion implantation condition for forming the first redistiff diffusion region is such that the acceleration voltage is 60 keV and the dose amount is 3.0 x 10 ¹⁵ cm ^-2 , The second ion is implanted at an acceleration voltage of 40 keV and a dose of 8.0 x 10 < ¹⁴ > cm < ^{2 &} gt ^; . A first well region of a first conductivity type and a second well region of a second conductivity type are formed in a surface region of the semiconductor substrate and a first and a second conductivity type first and second well regions are formed in the first and second well regions, The first and second transistors having the first diffusion layer and the second diffusion layer are formed respectively and at least an insulating film having contact holes exposing the first and second diffusion layers of the first and second transistors is formed, Forming a mask covering the second well region of the semiconductor substrate; Implanting a first ion into the first well region from the contact hole using the mask to form a first re-diffusion region of the second conductivity type in the first well region and continuing with the first diffusion layer; Removing the mask, And a step of implanting a second ion from the contact hole into the entire surface of the semiconductor substrate and forming a second re-diffusion region of the first conductivity type in the second well region in succession to the second diffusion layer , The dose amount in the case of implanting the second ions in the step of forming the second redistribution region is smaller than the dose amount in the case of implanting the first ions in the step of forming the first redistribution layer Wherein the semiconductor device is a semiconductor device. The method of claim 4, wherein the second ion implantation conditions in the case of forming the second diffusion region is re-accelerating voltage is from 30 to 50keV, a dose amount is 6.0 × 10 ¹⁴ to 1.5 × 10 ¹⁵ cm ^-2, the second Wherein the first ion is implanted under the conditions of an acceleration voltage of 60 keV and a dose amount of 3.0 x 10 < ¹⁵ > cm < ^{2 &} gt ^; . 5. The method according to claim 4, wherein the second ion implantation condition for forming the second redistiff diffusion region is an acceleration voltage of 40 keV and a dose amount of 8.0 x 10 < ¹⁴ & injection conditions of first ions method of manufacturing a semiconductor device, characterized in that the acceleration voltage is 60keV, a dose amount is 3.0 × 10 ¹⁵ cm ^-2. The manufacturing method of a semiconductor device according to claim 1, wherein a dose amount of the first ions when forming the first redistribution region is 3.0 x 10 ¹⁵ cm ^-2 ± 50%.