KR100308086B1 - Method for manufacturing of Semiconductor Device - Google Patents
Method for manufacturing of Semiconductor Device Download PDFInfo
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- KR100308086B1 KR100308086B1 KR1019990047987A KR19990047987A KR100308086B1 KR 100308086 B1 KR100308086 B1 KR 100308086B1 KR 1019990047987 A KR1019990047987 A KR 1019990047987A KR 19990047987 A KR19990047987 A KR 19990047987A KR 100308086 B1 KR100308086 B1 KR 100308086B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000000034 method Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 35
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 19
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 239000012535 impurity Substances 0.000 claims abstract description 12
- -1 nitrogen ions Chemical class 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 23
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
본 발명은 아날로그 디바이스에서는 전류이득을 향상시키고 ESD 보호회로 영역에서는 래치-업을 더욱 활성화시켜 ESD 보호 특성을 향상시키도록 한 반도체 소자의 제조방법에 관한 것으로서, 반도체 기판에 아날로그 디바이스와 ESD 보호회로 및 로직 디바이스를 형성하는 반도체 소자의 제조방법에 있어서, 반도체 기판에 일정한 간격을 갖는 복수개의 소자 격리막을 형성하는 단계와, 상기 아날로그 디바이스와 ESD 보호회로가 형성될 영역의 반도체 기판에 니트로겐 이온을 주입하여 니트로겐 불순물 영역을 형성하는 단계와, 상기 반도체 기판에 선택적으로 불순물 이온을 주입하여 상기 소자 격리막 사이의 반도체 기판 표면내에 제 1 도전형 웰 영역과 제 2 도전형 웰 영역을 각각 형성하는 단계를 포함하여 형성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device that improves current gain in an analog device and further activates latch-up in an ESD protection circuit area, thereby improving ESD protection characteristics. A method of manufacturing a semiconductor device for forming a logic device, comprising: forming a plurality of device isolation layers having a predetermined interval on a semiconductor substrate, and implanting nitrogen ions into a semiconductor substrate in a region where the analog device and the ESD protection circuit are to be formed; Forming a nitrogen impurity region, and selectively implanting impurity ions into the semiconductor substrate to form a first conductivity type well region and a second conductivity type well region in the semiconductor substrate surface between the device isolation layers, respectively. It is characterized by including the formation.
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 전류이득 및 ESD(Electro Static Discharge) 보호특성을 향상시키는데 적당한 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for improving current gain and electrostatic discharge (ESD) protection characteristics.
일반적으로 ASIC(Application Specific Integrated Circuit)에는 로직 디바이스(Logic Device)와 아날로그 디바이스(Analog Device)를 같이 형성해야 한다. 로직 디바이스에서는 웰(Well) 저항을 감소시켜 래치-업(Latch-Up)을 억제해야 하고, 아날로그 디바이스에는 웰 저항을 크게 하여 전류이득을 증가시켜야 한다.In general, an application specific integrated circuit (ASIC) requires a logic device and an analog device. Logic devices must reduce latch resistance by reducing the well resistance, while analog devices must increase current gain by increasing the well resistance.
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 제조방법을 설명하면 다음과 같다.Hereinafter, a manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1e는 종래의 반도체 소자의 제조방법을 나타낸 공정단면도이다.1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 산화막(12)과 질화막(13)을 차례로 형성하고, 사진석판술 및 식각공정을 이용하여 소자 격리막이 형성될 반도체 기판(11)의 표면이 노출되도록 상기 질화막(13) 및 산화막(12)을 선택적으로 패터닝한다.As shown in FIG. 1A, an oxide film 12 and a nitride film 13 are sequentially formed on the semiconductor substrate 11, and the surface of the semiconductor substrate 11 on which the device isolation film is to be formed using photolithography and etching processes. The nitride film 13 and the oxide film 12 are selectively patterned so as to be exposed.
이어, 상기 패터닝된 질화막(13) 및 산화막(12)을 마스크로 이용하여 노출된 반도체 기판(11)을 선택적으로 제거하여 소정깊이를 갖는 트랜치(Trench)(14)를 형성한다.Subsequently, the exposed semiconductor substrate 11 is selectively removed using the patterned nitride layer 13 and the oxide layer 12 as a mask to form a trench 14 having a predetermined depth.
도 1b에 도시한 바와 같이, 상기 트랜치(14)를 포함한 반도체 기판(11)의 전면에 갭-필(Gap-fill) 물질로 HDP(High Density Plasma)막(15)을 형성한다.As shown in FIG. 1B, a high density plasma (HDP) film 15 is formed of a gap-fill material on the entire surface of the semiconductor substrate 11 including the trench 14.
도 1c에 도시한 바와 같이, 상기 HDP막(15)의 전면에 CMP(Chemical Mechanical Polishing)공정을 실시하여 상기 트랜치(14)의 내부에 PGI(ProfileGrooved Isolation) 구조를 갖는 소자 격리막(15a)을 형성한다.As illustrated in FIG. 1C, a chemical mechanical polishing (CMP) process is performed on the entire surface of the HDP film 15 to form a device isolation layer 15a having a PG (Profile Grooved Isolation) structure inside the trench 14. do.
도 1d에 도시한 바와 같이, 상기 질화막(13)을 습식식각으로 제거하고, 상기 반도체 기판(11)의 전면에 제 1 포토레지스트막(16)을 도포한 후, 노광 및 현상공정으로 제 1 포토레지스트막(16)을 패터닝한다.As shown in FIG. 1D, the nitride film 13 is removed by wet etching, the first photoresist film 16 is coated on the entire surface of the semiconductor substrate 11, and then the first photo is subjected to an exposure and development process. The resist film 16 is patterned.
이어, 상기 패터닝된 제 1 포토레지스트막(16)을 마스크로 이용하여 전면에 n형 불순물 이온을 주입하여 상기 반도체 기판(11)의 표면내에 n-웰 영역(17)을 형성한다.Subsequently, n-type impurity ions are implanted into the entire surface by using the patterned first photoresist film 16 as a mask to form n-well regions 17 in the surface of the semiconductor substrate 11.
도 1e에 도시한 바와 같이, 상기 제 1 포토레지스트막(16)을 제거하고, 상기 반도체 기판(11)의 전면에 제 2 포토레지스트막(18)을 도포한 후, 노광 및 현상공정으로 제 2 포토레지스트막(18)을 패터닝한다.As shown in FIG. 1E, the first photoresist film 16 is removed, the second photoresist film 18 is coated on the entire surface of the semiconductor substrate 11, and then the second photoresist film 18 is exposed and developed. The photoresist film 18 is patterned.
이어, 상기 패터닝된 제 2 포토레지스트막(18)을 마스크로 이용하여 전면에 p형 불순물 이온을 주입하여 상기 반도체 기판(11)의 표면내에 p-웰 영역(19)을 형성한다.Subsequently, p-type impurity ions are implanted into the entire surface by using the patterned second photoresist film 18 as a mask to form a p-well region 19 in the surface of the semiconductor substrate 11.
이후 공정은 도면에 도시하지 않았지만, 제 2 포토레지스트막(18)을 제거한 후, 통상적인 공정을 진행하여 ESD 보호회로, 아날로그 디바이스, 로직 디바이스를 반도체 기판(11)에 형성한다.Subsequently, although not shown in the drawing, the second photoresist film 18 is removed, and then a conventional process is performed to form an ESD protection circuit, an analog device, and a logic device on the semiconductor substrate 11.
그러나 상기와 같은 종래의 반도체 소자의 제조방법에 있어서 다음과 같은 문제점이 있었다.However, in the conventional method of manufacturing a semiconductor device as described above has the following problems.
즉, 웰을 깊게 형성하여 웰 저항을 감소시키고자 하면 전류 이득이 감소하여아날로그 디바이스를 정상적으로 구현할 수 없으며, 웰을 얕게 형성하여 웰 저항을 증가시키면 로직 디바이스에서 래치-업 특성이 저하된다.In other words, if the well is deeply formed to reduce the well resistance, current gain decreases, and thus the analog device cannot be implemented normally. If the well is shallow, increasing the well resistance lowers the latch-up characteristic of the logic device.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로 니트로겐(Nitrogen) 이온을 주입하여 아날로그 디바이스 및 ESD 보호회로 영역에 얕은 웰을 형성하여 아날로그 디바이스에서는 전류이득을 향상시키고 ESD 보호회로 영역에서는 래치-업을 더욱 활성화시켜 ESD 보호 특성을 향상시키도록 한 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the conventional problems as described above to form a shallow well in the analog device and ESD protection circuit region by implanting nitrogen ions to improve the current gain in the analog device and ESD protection circuit region An object of the present invention is to provide a method for manufacturing a semiconductor device that further activates latch-up to improve ESD protection characteristics.
도 1a 내지 도 1e 종래의 반도체 소자의 제조방법을 나타낸 공정단면도1A to 1E are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21 : 반도체 기판 22 : 산화막21 semiconductor substrate 22 oxide film
23 : 질화막 24 : 트랜치23 nitride layer 24 trench
25 : HDP막 25a : 소자 격리막25: HDP film 25a: device isolation film
26 : 제 1 포토레지스트막 27 : 니트로겐 불순물 영역26: first photoresist film 27: nitrogen impurity region
28 : 제 2 포토레지스트막 29 : n-웰 영역28: second photoresist film 29: n-well region
30 : 제 3 포토레지스트막 31 ; p-웰 영역30: third photoresist film 31; p-well region
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 제조방법은 반도체 기판에 아날로그 디바이스와 ESD 보호회로 및 로직 디바이스를 형성하는 반도체 소자의 제조방법에 있어서서, 반도체 기판에 일정한 간격을 갖는 복수개의 소자 격리막을 형성하는 단계와, 상기 아날로그 디바이스와 ESD 보호회로가 형성될 영역의 반도체 기판에 니트로겐 이온을 주입하여 니트로겐 불순물 영역을 형성하는 단계와, 상기 반도체 기판에 선택적으로 불순물 이온을 주입하여 상기 소자 격리막 사이의 반도체 기판 표면내에 제 1 도전형 웰 영역과 제 2 도전형 웰 영역을 각각 형성하는 단계를 포함하여 형성함을 특징으로 한다.A semiconductor device manufacturing method according to the present invention for achieving the above object in the semiconductor device manufacturing method for forming an analog device, an ESD protection circuit and a logic device on a semiconductor substrate, a plurality of having a predetermined interval on the semiconductor substrate Forming a device isolation layer, implanting nitrogen ions into a semiconductor substrate in a region where the analog device and the ESD protection circuit are to be formed, and forming a nitrogen impurity region, and selectively implanting impurity ions into the semiconductor substrate Forming a first conductivity type well region and a second conductivity type well region in the surface of the semiconductor substrate between the device isolation layers.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 제조방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 의한 반도체 소자의 제조방법을 나타낸 공정단면도이다.2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)상에 산화막(22)과 질화막(23)을 차례로 형성하고, 사진석판술 및 식각공정을 이용하여 소자 격리막이 형성될 반도체 기판(21)의 표면이 노출되도록 상기 질화막(23) 및 산화막(22)을 선택적으로 패터닝한다.As shown in FIG. 2A, an oxide film 22 and a nitride film 23 are sequentially formed on the semiconductor substrate 21, and the surface of the semiconductor substrate 21 on which the device isolation film is to be formed using photolithography and etching processes. The nitride film 23 and the oxide film 22 are selectively patterned so as to be exposed.
이어, 상기 패터닝된 질화막(23) 및 산화막(22)을 마스크로 이용하여 노출된 반도체 기판(21)을 선택적으로 제거하여 소정깊이를 갖는 트랜치(Trench)(24)를 형성한다.Subsequently, the exposed semiconductor substrate 21 is selectively removed by using the patterned nitride film 23 and the oxide film 22 as a mask to form a trench 24 having a predetermined depth.
도 2b에 도시한 바와 같이, 상기 트랜치(24)를 포함한 반도체 기판(21)의 전면에 갭-필(Gap-fill) 물질로 HDP(High Density Plasma)막(25)을 형성한다.As shown in FIG. 2B, a high density plasma (HDP) film 25 is formed of a gap-fill material on the entire surface of the semiconductor substrate 21 including the trench 24.
도 2c에 도시한 바와 같이, 상기 HDP막(25)의 전면에 CMP(Chemical Mechanical Polishing)공정을 실시하여 상기 트랜치(24)의 내부에 PGI(Profile Grooved Isolation) 구조를 갖는 소자 격리막(25a)을 형성한다.As shown in FIG. 2C, a CMP (Chemical Mechanical Polishing) process is performed on the entire surface of the HDP film 25 to form a device isolation layer 25a having a PGI (Profile Grooved Isolation) structure in the trench 24. Form.
도 2d에 도시한 바와 같이, 상기 질화막(23)을 습식식각으로 제거하고, 상기 반도체 기판(21)의 전면에 제 1 포토레지스트막(26)을 도포한 후, 노광 및 현상공정으로 로직 디바이스 영역에만 남도록 제 1 포토레지스트막(26)을 패터닝한다.As shown in FIG. 2D, the nitride film 23 is removed by wet etching, the first photoresist film 26 is coated on the entire surface of the semiconductor substrate 21, and then the logic device region is exposed and developed. The first photoresist film 26 is patterned so as to remain only.
이어, 상기 패터닝된 제 1 포토레지스트막(26)을 마스크로 이용하여 니트로겐(Nitrogen) 이온을 주입하여 상기 반도체 기판(21)내에 니트로겐 불순물 영역(27)을 형성한다.Subsequently, nitrogen ions are implanted using the patterned first photoresist layer 26 as a mask to form a nitrogen impurity region 27 in the semiconductor substrate 21.
즉, ESD 보호회로와 아날로그 디바이스가 형성될 영역에만 니트로겐 이온을 주입한다.That is, nitrogen ions are implanted only in the area where the ESD protection circuit and the analog device are to be formed.
도 2e에 도시한 바와 같이, 상기 제 1 포토레지스트막(26)을 제거하고, 상기 반도체 기판(21)의 전면에 제 2 포토레지스트막(28)을 도포한 후, 노광 및 현상공정으로 제 2 포토레지스트막(28)을 패터닝한다.As shown in FIG. 2E, the first photoresist film 26 is removed, and the second photoresist film 28 is applied to the entire surface of the semiconductor substrate 21. The photoresist film 28 is patterned.
이어, 상기 패터닝된 제 2 포토레지스트막(28)을 마스크로 이용하여 전면에 n형 불순물 이온을 주입하여 상기 반도체 기판(21)의 표면내에 n-웰 영역(29)을 형성한다.Subsequently, n-type impurity ions are implanted into the entire surface by using the patterned second photoresist layer 28 as a mask to form an n-well region 29 in the surface of the semiconductor substrate 21.
여기서 상기 n-웰 영역(29)은 니트로겐 이온주입에 의해 비대칭으로 형성된다. 즉, 니트로겐 이온이 주입된 영역의 n-웰 영역(29)은 니트로겐 이온이 주입되지 않는 영역의 n-웰 영역(29)보다 얕게 형성된다.The n-well region 29 is asymmetrically formed by nitrogen ion implantation. That is, the n-well region 29 of the region into which nitrogen ions are implanted is formed shallower than the n-well region 29 of the region into which nitrogen ions are not implanted.
도 2f에 도시한 바와 같이, 상기 제 2 포토레지스트막(28)을 제거하고, 상기 반도체 기판(21)의 전면에 제 3 포토레지스트막(30)을 도포한 후, 노광 및 현상공정으로 제 3 포토레지스트막(30)을 패터닝한다.As shown in FIG. 2F, the second photoresist film 28 is removed, and the third photoresist film 30 is applied to the entire surface of the semiconductor substrate 21. The photoresist film 30 is patterned.
이어, 상기 패터닝된 제 3 포토레지스트막(30)을 마스크로 이용하여 전면에 p형 불순물 이온을 주입하여 상기 반도체 기판(21)의 표면내에 p-웰 영역(31)을 형성한다.Subsequently, p-type impurity ions are implanted into the entire surface by using the patterned third photoresist layer 30 as a mask to form a p-well region 31 in the surface of the semiconductor substrate 21.
여기서 상기 p-웰 영역(31)은 니트로겐 이온주입에 의해 비대칭으로 형성된다. 즉, 니트로겐 이온이 주입된 영역의 p-웰 영역(31)은 니트로겐 이온이 주입되지 않는 영역의 p-웰 영역(31)보다 얕게 형성된다.The p-well region 31 is asymmetrically formed by nitrogen ion implantation. That is, the p-well region 31 of the region into which the nitrogen ions are implanted is formed shallower than the p-well region 31 of the region into which the nitrogen ions are not implanted.
이후 공정은 도면에 도시하지 않았지만, 제 3 포토레지스트막(30)을 제거한 후, 통상적인 공정을 진행하여 ESD 보호회로, 아날로그 디바이스, 로직 디바이스를반도체 기판(21)에 형성한다.Although the process is not shown in the drawings, after the third photoresist film 30 is removed, a conventional process is performed to form an ESD protection circuit, an analog device, and a logic device on the semiconductor substrate 21.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 제조방법은 다음과 같은 효과가 있다.As described above, the method for manufacturing a semiconductor device according to the present invention has the following effects.
첫째, 비대칭 웰(Asymmetric Well)을 이용하여 로직 디바이스와 아날로그 디바이스를 동시에 구현하고, ESD 보호회로 특성을 개선할 수 있다.First, asymmetric wells can be used to implement both logic and analog devices simultaneously and improve ESD protection circuit characteristics.
둘째, 비대칭 웰을 이용하여 아날로그 디바이스를 구현하기 위해 웰 저항을 크게 할 경우에 나타나는 로직 디바이스에서의 래치-업 특성 저하를 방지할 수 있다.Second, asymmetric wells can be used to prevent the latch-up degradation of logic devices that appear when the well resistance is increased to implement analog devices.
셋째, 비대칭 웰을 이용하여 로직 디바이스를 구현하기 위해 웰 저항을 작게 할 경우에 나타나는 아날로그 디바이스에서의 전류이득 저하를 방지할 수 있다.Third, it is possible to prevent current gain deterioration in an analog device that appears when the well resistance is small to implement a logic device using an asymmetric well.
넷째, 비대칭 웰을 이용하여 ESD 보호회로 영역에서 래치-업이 쉽게 발생하도록 하여 ESD 보호회로를 통하여 큰 전류를 흘려서 큰 전류가 회로에 인풋(input)으로 흘러가는 것을 방지하여 ESD 특성을 개선할 수 있다.Fourth, by using asymmetric wells, latch-up can easily occur in the ESD protection circuit area, and large current can flow through the ESD protection circuit to prevent large current from flowing into the circuit to improve ESD characteristics. have.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5336915A (en) * | 1991-01-09 | 1994-08-09 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having analog circuit and digital circuit formed on one chip |
| JPH0758289A (en) * | 1993-08-09 | 1995-03-03 | Toshiba Corp | Semiconductor device |
| US5491358A (en) * | 1993-07-09 | 1996-02-13 | Kabushiki Kaisha Toshiba | Semiconductor device having an isolating portion between two circuit regions |
| KR19980066161A (en) * | 1997-01-20 | 1998-10-15 | 김광호 | Electrostatic Discharge Protection Circuit of Semiconductor Device with Separate Power Line |
| KR19980065222A (en) * | 1997-01-06 | 1998-10-15 | 김광호 | Electrostatic protection device |
| US5932914A (en) * | 1996-07-25 | 1999-08-03 | Nec Corporation | Semiconductor protection device formed inside a well having contact with a buried layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5336915A (en) * | 1991-01-09 | 1994-08-09 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device having analog circuit and digital circuit formed on one chip |
| US5491358A (en) * | 1993-07-09 | 1996-02-13 | Kabushiki Kaisha Toshiba | Semiconductor device having an isolating portion between two circuit regions |
| JPH0758289A (en) * | 1993-08-09 | 1995-03-03 | Toshiba Corp | Semiconductor device |
| US5932914A (en) * | 1996-07-25 | 1999-08-03 | Nec Corporation | Semiconductor protection device formed inside a well having contact with a buried layer |
| KR19980065222A (en) * | 1997-01-06 | 1998-10-15 | 김광호 | Electrostatic protection device |
| KR19980066161A (en) * | 1997-01-20 | 1998-10-15 | 김광호 | Electrostatic Discharge Protection Circuit of Semiconductor Device with Separate Power Line |
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