KR100247704B1 - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device Download PDF

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KR100247704B1
KR100247704B1 KR1019970078773A KR19970078773A KR100247704B1 KR 100247704 B1 KR100247704 B1 KR 100247704B1 KR 1019970078773 A KR1019970078773 A KR 1019970078773A KR 19970078773 A KR19970078773 A KR 19970078773A KR 100247704 B1 KR100247704 B1 KR 100247704B1
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forming
impurity region
well
trench
region
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KR1019970078773A
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Korean (ko)
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KR19990058630A (en
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이주형
김영관
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Abstract

본 발명은 웰 간에 발생되는 랫치업을 방지하기에 적당한 반도체장치의 제조방법에 관한 것으로, 반도체기판 상에 소자 격리영역을 정의하는 트렌치를 형성하는 공정과, 트렌치의 일측에 제 1도전형인 제 1불순물영역을 형성하는 공정과, 트렌치의 타측에 제 2도전형인 제 2불순물영역을 형성하는 공정과, 트렌치를 채우도록 갭필층을 형성하는 공정과, 제 1불순물영역을 포함하는 부위에 제 1도전형인 제 1웰을 형성하는 공정과, 제 2불순물영역을 포함하는 부위에 제 2도전형인 제 2웰을 형성하는 공정과, 제 1웰 하부에 제 1도전형인 제 3불순물영역을 형성하는 공정과, 제 2웰 하부에 제 2도전형인 제 4불순물영역을 형성하는 공정을 구비한 것이 특징이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for preventing latch-ups occurring between wells, comprising: forming a trench defining an element isolation region on a semiconductor substrate; and a first conductive type on one side of the trench. Forming an impurity region, forming a second impurity region of a second conductivity type on the other side of the trench, forming a gap fill layer to fill the trench, and forming a first conductive region in the region including the first impurity region Forming a first well of a type; forming a second well of a second conductivity type in a portion including the second impurity region; forming a third impurity region of a first conductivity type in a lower portion of the first well; And forming a fourth impurity region of a second conductivity type under the second well.

따라서, 본 발명에서는 P형콘택층에 오버-슈트를 가했을 때의 P형 콘택층과 제 2불순물영역을 따라서 전류밀도가 분산되어 P+ 트리거링에 의한 PNPN 랫치업 발생을 억제하며, N형 콘택층에 언더-슈트를 가할 때 N형 콘택층과 제 1불순물영역을 따라서 전류밀도가 분산되어 N+트리거링에 의한 NPNP 랫치업 발생을 억제하는 잇점이 있다.Therefore, in the present invention, when the over-shoot is applied to the P-type contact layer, the current density is distributed along the P-type contact layer and the second impurity region, thereby suppressing the occurrence of PNPN latch-up due to P + triggering, The current density is distributed along the N-type contact layer and the first impurity region when the under-shoot is applied, thereby suppressing NPNP latchup generation due to N + triggering.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히, 웰 간의 랫치업(latch-up)을 방지하기에 적당한 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device suitable for preventing latch-up between wells.

CMOS IC 는 N채널 MOS 트랜지스터와 P채널 MOS 트랜지스터의 조합으로 구성되어 있으며, 소자가 고집적화됨에 따라, CMOS 공정 과정에서 이들 각각의 NMOS 와 PMOS 트랜지스터가 근접된 위치에 형성된다. 따라서, CMOS 트랜지스터가 온상태로 될 때, 다 수의 PN 접합을 가지고 있으며 그들로 구성되는 기생적인 쌍극성 구조, 즉, NMOS 와 PMOS 트랜지스터 간에 생기는 N 층과 P 층간의 결합(N-P-N-P 또는 P-N-P-N)을 초래할 수 있다.The CMOS IC is composed of a combination of an N-channel MOS transistor and a P-channel MOS transistor. As the device is highly integrated, each of the NMOS and PMOS transistors is formed at a position close to each other during the CMOS process. Thus, when the CMOS transistors are turned on, they have a number of PN junctions, and the parasitic bipolar structure composed of them, that is, the coupling between the N and P layers (NPNP or PNPN) that occurs between the NMOS and PMOS transistors. Can cause.

CMOS IC 의 정상동작 상태에서 PN 접합은 모두 역바이어스의 상태이며 기생 바이폴러 트랜지스터에도 전류가 흐르도록 베이스전압은 가해지고 있지는 않는다.In normal operation of a CMOS IC, the PN junctions are all reverse biased, and the base voltage is not applied to the parasitic bipolar transistor to allow current to flow.

그러나, 정해진 동작범위를 벗어나면 정상적인 상태에서는 역바이어스 상태에 있는 PN 접합이 순바이어스 상태로 되거나, 과대한 전류가 반도체기판 내를 흘러 전위차를 일으키거나 하여 기생 바이폴러 트랜지스터를 도통상태로 해서 랫치업을 발생시키는 데, 이러한 랫치업을 방지하고자 하는 많은 연구가 종래에 개발되었다.However, beyond the specified operating range, under normal conditions, the PN junction in the reverse bias state becomes a forward bias state, or excessive current flows through the semiconductor substrate, causing a potential difference, and latching the parasitic bipolar transistor into a conductive state. Many studies have been developed in the past to attempt to prevent such latchup.

도 1a 내지 도 1c 는 종래기술에 따른 반도체장치의 제조를 위한 공정도이다.1A to 1C are process drawings for manufacturing a semiconductor device according to the prior art.

도 1a 와 같이, P형의 반도체기판(100)상에 패드산화막(102)을 형성한 후, 그 상부에 질화막(104)을 적층하여 형성한다. 이 패드산화막(102)으로는 반도체기판(100) 위에 얇은 산화막을 형성시키는 통상의 방법대로 SiO2층을 형성한다. 여기에서, 패드산화막(102)은 후속 공정인 질화막 성장 시에 질화막에 의한 반도체기판(100) 표면의 결점결함이 유발되는 현상을 정지시키고, 또한, 반도체기판(100)과 질화막(104) 사이에 개재되어 완충역할을 한다.As shown in FIG. 1A, after the pad oxide film 102 is formed on the P-type semiconductor substrate 100, the nitride film 104 is formed on the upper portion of the pad oxide film 102. As the pad oxide film 102, a SiO 2 layer is formed by a conventional method of forming a thin oxide film on the semiconductor substrate 100. Here, the pad oxide film 102 stops a phenomenon in which defects on the surface of the semiconductor substrate 100 are caused by the nitride film during the growth of the nitride film, which is a subsequent process, and stops the phenomenon between the semiconductor substrate 100 and the nitride film 104. Intervene as a buffer.

이어서, 질화막(104) 상에 포토레지스트(photoresist)를 도포한 후에 노광 및 현상하여 필드영역을 노출시키도록 패터닝하여 액티브마스크(106)을 제조한다. 이 액티브마스크(106)에 의해 액티브영역이 보호되어 있는 상태이다.Subsequently, after the photoresist is applied onto the nitride film 104, the photoresist is exposed and developed to be patterned to expose the field region, thereby manufacturing an active mask 106. The active region is protected by the active mask 106.

도 1b 와 같이, 액티브마스크(106)를 식각마스크로 이용하여 질화막(104) 및 반도체기판(100)의 소정깊이까지 식각하여 트렌치(t1)를 형성한다. 이어서, 표면산화시키어 트랜치(t1)의 측면을 산화시킨다. 이 후, 액티브마스크(106)를 제거한다.As shown in FIG. 1B, the trench t1 is formed by etching the nitride film 104 and the predetermined depth of the semiconductor substrate 100 using the active mask 106 as an etching mask. Subsequently, surface oxidation is performed to oxidize the side surface of the trench t1. Thereafter, the active mask 106 is removed.

도 1c 와 같이, 반도체기판(100)상에 산화실리콘 등의 절연물질을 형성한 후, 에치백하여 트랜치(t1) 내부를 채우는 갭필층(P1)을 형성함으로써 표면을 평탄화한다. 이어서, 질화막(104)을 제거한다.As shown in FIG. 1C, after forming an insulating material such as silicon oxide on the semiconductor substrate 100, the surface is planarized by etching back to form a gap fill layer P1 filling the trench t1. Next, the nitride film 104 is removed.

NMOS가 형성될 부위를 마스크(110)로 가린 후, PMOS가 형성될 부위에 인(phosphor) 등의 N형 불순물이온을 주입하여 N웰(112)을 형성한다.After masking the portion where the NMOS is to be formed by the mask 110, an N well 112 is formed by implanting an N-type impurity ion such as phosphorous into the portion where the PMOS is to be formed.

그리고 N웰(112)의 갭필층(P1)양측에 서로 다른 도전형인 N+콘택층(116)과 P+콘택층(118)을 형성한다. 이 후, PMOS가 형성될 부위를 마스크(120)로 가린 후, NMOS가 형성될 부위에 보론(boron) 등의 P형 불순물이온을 주입하여 P웰(122)을 형성하고, 마찬가지 방법으로 P웰의 갭필층 양측에 서로 다른 도전형인 P+콘택층(124)과 N+콘택층(126)을 형성한다.In addition, N + contact layers 116 and P + contact layers 118 having different conductivity types are formed on both sides of the gap fill layer P1 of the N well 112. Subsequently, the PMOS region is formed by mask 120 and then P-type impurity ions such as boron are implanted into the NMOS region to form the P well 122. P + contact layers 124 and N + contact layers 126 of different conductivity types are formed on both sides of the gap fill layer.

그러나, 종래의 방법에서는 소자가 고집적화됨에 따라, 소자격리영역이 작아져서 P웰의 보론이 트랜치 내의 갭필층인 산화막으로 확산되고 N웰 쪽의 인성분이 P웰 쪽으로 확산되어 N웰과 P웰의 NMOS 사이의 공핍층이 붙어서 펀치스루를 발생시키었다. 그리고 PNPN 의 수직으로 일어나는 랫치업이 웰 격리 밑으로 측면 랫치가 발생하게 되는 문제점이 있었다.However, in the conventional method, as the device is highly integrated, the device isolation region becomes smaller, so that the boron of the P well diffuses into the oxide film, which is a gap fill layer in the trench, and the phosphorus component on the N well side diffuses into the P well, so that the N well and the N well of the P well The depletion layer between them stuck and produced a punchthrough. And there was a problem that the vertical latching of the PNPN occurs side lateral latch below the well isolation.

상기의 문제점을 해결하고자, 본 발명의 목적은 웰 간에 발생되는 랫치업을 방지하는 반도체장치의 제조방법을 제공하려는 것이다.In order to solve the above problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device to prevent the latch-up generated between the wells.

본 발명의 반도제장치의 제조방법은 반도체기판 상에 소자 격리영역을 정의하는 트렌치를 형성하는 공정과, 트렌치의 일측에 제 1도전형인 제 1불순물영역을 형성하는 공정과, 트렌치의 타측에 제 2도전형인 제 2불순물영역을 형성하는 공정과, 트렌치를 채우도록 갭필층을 형성하는 공정과, 제 1불순물영역을 포함하는 부위에 제 1도전형인 제 1웰을 형성하는 공정과, 제 2불순물영역을 포함하는 부위에 제 2도전형인 제 2웰을 형성하는 공정과, 제 1웰 하부에 제 1도전형인 제 3불순물영역을 형성하는 공정과, 제 2웰 하부에 제 2도전형인 제 4불순물영역을 형성하는 공정을 구비한 것이 특징이다.A method of manufacturing a semiconductor device according to the present invention includes forming a trench defining a device isolation region on a semiconductor substrate, forming a first impurity region of a first conductivity type on one side of the trench, and forming a trench on the other side of the trench. Forming a second conductive impurity region, forming a gap fill layer to fill the trench, forming a first well of the first conductivity type in a portion including the first impurity region, and forming a second impurity Forming a second well of a second conductivity type in a region including a region, forming a third impurity region of a first conductivity type in a lower portion of the first well, and a fourth impurity of a second conductivity type in a lower portion of the second well; It is characterized by including the step of forming a region.

도 1a 내지 도 1c 는 종래기술에 따른 반도체장치의 소자격리를 위한 공정도이다.1A to 1C are process diagrams for device isolation of a semiconductor device according to the prior art.

도 2a 내지 도 2j 는 본 발명에 따른 반도체장치의 소자격리를 위한 공정도이다.2A to 2J are process diagrams for device isolation of a semiconductor device according to the present invention.

도 3a 내지 도 3f 는 본 발명에 따른 에너지 밴드 다이어그램이다.3A-3F are energy band diagrams in accordance with the present invention.

*도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100, 200. 반도체기판 102, 202. 패드산화막100, 200. Semiconductor substrate 102, 202. Pad oxide film

104, 204. 질화막 220, 230. 불순물영역104, 204. Nitride films 220, 230. Impurity regions

P1, P2. 갭필층 t1, t2. 트렌치P1, P2. Gap fill layers t1, t2. Trench

106, 110, 206, 210, 214. 마스크106, 110, 206, 210, 214.Mask

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하겠다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 도 2e 는 본 발명에 따른 반도체장치의 소자격리를 위한 공정도이다.2A to 2E are process diagrams for device isolation of a semiconductor device according to the present invention.

도 2a 와 같이, P형의 반도체기판(200)에 패드산화막(202) 및 질화막(204)을 순차적으로 적층하여 형성한다. 이 패드산화막(202)으로는 반도체기판(200) 위에 얇은 산화막을 형성시키는 통상의 화학기상증착(CVD: Chemical Vapor Deposition)방법을 이용하여 SiO2층을 형성한다. 여기에서, 패드산화막(202)은 후속 공정인 질화막 성장 시에 질화막에 의한 반도체기판(200) 표면의 결점결함이 유발되는 현상을 정지시키고, 반도체기판(200)과 질화막(204) 사이에 개재되어 완충역할을 한다.As shown in FIG. 2A, the pad oxide film 202 and the nitride film 204 are sequentially stacked on the P-type semiconductor substrate 200. As the pad oxide film 202, a SiO 2 layer is formed using a conventional chemical vapor deposition (CVD) method in which a thin oxide film is formed on the semiconductor substrate 200. Here, the pad oxide film 202 stops a phenomenon in which defects on the surface of the semiconductor substrate 200 are caused by the nitride film during nitride film growth, which is a subsequent process, and is interposed between the semiconductor substrate 200 and the nitride film 204. It acts as a buffer.

이어서, 질화막(204) 상에 포토레지스트를 도포한 후에 노광 및 현상하여 소자의 필드영역을 노출시키고 액티브영역을 덮도록 패터닝하여 제1마스크(206)을 제조한다.Subsequently, after the photoresist is applied on the nitride film 204, the photoresist is exposed and developed to expose the field region of the device, and patterned to cover the active region, thereby manufacturing the first mask 206.

도 2b 와 같이, 제 1마스크(206)를 식각 마스크로 이용하여 질화막(204) 및 패드산화막(202) 및 반도체기판(200)의 소정깊이까지 식각하여 트렌치(t2)를 형성한다. 이어서, 반도체기판(200)을 표면산화시킴으로써 트렌치(t2)의 측면을 산화시킨다. 이 후, 제 1마스크(206)를 제거한다.As illustrated in FIG. 2B, the trench t2 is formed by etching to the predetermined depth of the nitride film 204, the pad oxide film 202, and the semiconductor substrate 200 using the first mask 206 as an etching mask. Next, the side surface of the trench t2 is oxidized by surface oxidation of the semiconductor substrate 200. Thereafter, the first mask 206 is removed.

도 2c 와 같이, P형의 반도체기판(200)에 포토레지스트를 도포한 후, 노광 및 현상함으로써 트렌치를 포함하여 PMOS 가 형성될 부위 및 NMOS 가 형성될 부위를 가리되, PMOS 가 형성될 부위와 NMOS 가 형성될 부위의 경계면의 트렌치(t2)에서 PMOS가 형성될 부위쪽을 노출시키도록 패터닝하여 제 2마스크(208)를 제조한다.As shown in FIG. 2C, after the photoresist is applied to the P-type semiconductor substrate 200, the photoresist is exposed and developed to cover the portion where the PMOS is to be formed and the portion where the NMOS is to be formed, including the trench, A second mask 208 is fabricated by patterning to expose the side of the site where the PMOS is to be formed in the trench t2 of the interface of the site where the NMOS will be formed.

이 제 2마스크(208)를 이온 블로킹 마스크로 이용하여 고농도의 N형 불순물이온을 주입함으로써 제 1불순물영역(220)을 형성한다.The first impurity region 220 is formed by implanting a high concentration of N-type impurity ions using the second mask 208 as an ion blocking mask.

도 2d 와 같이, 제 2마스크(208)를 제거한다.As shown in FIG. 2D, the second mask 208 is removed.

제 1불순물영역(220)이 형성된 P형의 반도체기판(200)에 포토레지스트를 도포한 후, 노광 및 현상함으로써, 상술한 제 2마스크(208)와 반대로, 트렌치를 포함하여 PMOS 가 형성될 부위 및 NMOS 가 형성될 부위를 가리되, PMOS 가 형성될 부위와 NMOS 가 형성될 부위의 경계면의 트렌치(t2)에서 NMOS가 형성될 부위쪽을 노출시키도록 패터닝하여 제 3마스크(210)를 제조한다. 이 제 3마스크(210)를 이온 블로킹 마스크로 이용하여 고농도의 P형 불순물이온을 주입함으로써 제 2불순물영역(230)을 형성한다.The photoresist is applied to the P-type semiconductor substrate 200 on which the first impurity region 220 is formed, and then exposed and developed, whereby the PMOS is formed including the trench, as opposed to the second mask 208 described above. And a portion to cover the portion where the NMOS is to be formed, and to pattern the portion to expose the portion of the portion where the NMOS is to be formed in the trench t2 of the interface between the portion where the PMOS is to be formed and the portion where the NMOS is to be formed. . The second impurity region 230 is formed by implanting a high concentration of P-type impurity ions using the third mask 210 as an ion blocking mask.

도면에 도시되어 있듯이, 서로 반대 도전형의 불순물이온이 고농도로 주입된 제 1불순물영역(220)과 제 2불순물영역(230)은 소자의 필드영역을 정의하는 트렌치 하부에 각각 형성되어져 있다.As shown in the figure, the first impurity region 220 and the second impurity region 230 in which the impurity ions of the opposite conductivity type are injected at a high concentration are formed under the trench defining the field region of the device, respectively.

도 2e 와 같이, 제 3마스크(210)를 제거한다.As shown in FIG. 2E, the third mask 210 is removed.

제 1, 제 2불순물영역(220)(230)이 형성된 반도체기판(200)상에 산화실리콘 등의 절연물질을 형성한 후에 에치백하여 트랜치(t2) 내부를 채우는 갭필층(P2)을 형성한다. 이어서, 질화막(204)을 제거한다.An insulating material such as silicon oxide is formed on the semiconductor substrate 200 on which the first and second impurity regions 220 and 230 are formed, and then etched back to form a gap fill layer P2 filling the trench t2. . Next, the nitride film 204 is removed.

그리고 반도체기판(200)에 포토레지스트를 도포한 후, 노광 및 현상하여 PMOS 가 형성될 부위는 노출시키고 NMOS가 형성될 부위를 가리도록 패터닝함으로써 제 4마스크(214)를 제조한다. 이 제 4마스크(214)를 이온 블로킹 마스크로 이용하여 PMOS 가 형성될 부위에 N형의 불순물이온을 주입함으로써 N웰(212)을 형성한다.After the photoresist is applied to the semiconductor substrate 200, the fourth mask 214 is manufactured by exposing and developing the semiconductor substrate 200 to expose the portion where the PMOS is to be formed and to pattern the portion where the NMOS is to be formed. Using the fourth mask 214 as an ion blocking mask, an N well 212 is formed by injecting N-type impurity ions into a portion where a PMOS is to be formed.

도 2f 와 같이, 제 4마스크(214)를 제거한다.As shown in FIG. 2F, the fourth mask 214 is removed.

그리고 반도체기판(200)에 포토레지스트를 도포한 후, 노광 및 현상하여 NMOS 가 형성될 부위는 노출시키고 PMOS가 형성될 부위를 가리도록 패터닝함으로써 제 5마스크(216)를 제조한다. DL 제 5마스크(216)를 이온 블로킹 마스크로 이용하여 NMOS 가 형성될 부위에 P형의 불순물이온을 주입함으로써 P웰(218)을 형성한다.After the photoresist is applied to the semiconductor substrate 200, the fifth mask 216 is manufactured by exposing and developing the semiconductor substrate 200 to expose the portion where the NMOS is to be formed and to pattern the portion where the PMOS is to be formed. The P well 218 is formed by injecting P-type impurity ions into a portion where an NMOS is to be formed using the DL fifth mask 216 as an ion blocking mask.

N, P웰(212)(218) 형성공정이 완료되면, 1000 ∼ 1100℃ 정도의 고온에서 빠른 열처리(RTA:Rapidly Temperature Anneal)를 진행시킨다.When the N, P wells 212 and 218 forming process is completed, a rapid heat treatment (RTA: Rapid Temperature Anneal) is performed at a high temperature of about 1000 to 1100 ° C.

도 2g 와 같이, 제 5마스크(216)을 제거한다.As shown in FIG. 2G, the fifth mask 216 is removed.

그리고 반도체기판(200)에 포토레지스트를 도포한 후, 노광 및 현상하여 PMOS 가 형성될 부위는 노출시키고 NMOS가 형성될 부위를 가리도록 패터닝함으로써 제 6마스크(240)를 제조한다. 이 제 6마스크(240)를 이온 블로킹 마스크로 하여 N형의 불순물이온을 주입함으로써 제 3불순물영역(242)을 형성한다.After the photoresist is applied to the semiconductor substrate 200, the sixth mask 240 is manufactured by exposing and developing the semiconductor substrate 200 to expose the portion where the PMOS is to be formed and to pattern the portion where the NMOS is to be formed. The third impurity region 242 is formed by implanting N-type impurity ions using the sixth mask 240 as an ion blocking mask.

도 2h 와 같이, 제 6마스크(240)를 제거한다.As shown in FIG. 2H, the sixth mask 240 is removed.

그리고 반도체기판(200)에 포토레지스트를 도포한 후, 노광 및 현상하여 NMOS 가 형성될 부위는 노출시키고 PMOS가 형성될 부위를 가리도록 패터닝함으로써 제 7마스크(246)를 제조한다. 이 제 7마스크(246)를 이온 블로킹 마스크로 하여 P형의 불순물이온을 주입함으로써 제 4불순물영역(244)을 형성한다.After the photoresist is applied to the semiconductor substrate 200, the seventh mask 246 is manufactured by exposing and developing the semiconductor substrate 200 to expose the portion where the NMOS is to be formed and to pattern the portion where the PMOS is to be formed. The fourth impurity region 244 is formed by implanting P-type impurity ions using the seventh mask 246 as an ion blocking mask.

도 2i 와 같이, 제 7마스크(246)을 제거한다. 그리고 N웰(212)에서 갭필층(P2) 및 P웰(218)에서 갭필층(P2) 일측에 고농도의 N형 콘택층(248)(252)을 형성한다.As shown in FIG. 2I, the seventh mask 246 is removed. A high concentration of N-type contact layers 248 and 252 is formed on one side of the gap fill layer P2 in the N well 212 and the gap fill layer P2 in the P well 218.

도 2j 와 같이, 마찬가지 방법으로 N웰(212)에서 갭필층(P2) 및 P웰(218)의 갭필층(P2) 타측에 고농도의 P형 콘택층(250)(254)을 형성한다.As shown in FIG. 2J, a high concentration of P-type contact layers 250 and 254 is formed in the N well 212 on the other side of the gap fill layer P2 and the gap fill layer P2 of the P well 218.

이 때, N형 콘택층(248)(252) 및 P형 콘택층(250)(254)의 농도는 1E10 ∼ 1E20 이다.At this time, the concentrations of the N-type contact layers 248 and 252 and the P-type contact layers 250 and 254 are 1E10 to 1E20.

따라서, 이 후의 공정을 통해 형성된 NMOS 와 PMOS 트랜지스터 간의 P형 콘택층(250)과 N웰(212)과 P웰(218)과 N형 콘택층(252) 사이에 PNPN 또는 NPNP 가 초래된다.Therefore, PNPN or NPNP is caused between the P-type contact layer 250 and the N-well 212 and the P-well 218 and the N-type contact layer 252 between the NMOS and the PMOS transistor formed through the subsequent process.

도 3a 내지 도 3f 는 본 발명에 따른 에너지 밴드 다이어그램이다.3A-3F are energy band diagrams in accordance with the present invention.

도 3a는 평형상태의 PNPN 에너지 밴드 다이어그램으로, P형콘택층(250)은 P+로 도핑되므로 다수 개의 정공을 가지고, 제 1 및 제 3 불순물영역(220)(242)은 N+로 도핑되므로 다 수개의 전자를 가지며, 또한, N웰(212)은 N-이므로 제 1 및 제 3 불순물영역(220)(242) 보다 적은 수의 전자를 갖는다. 상기에서 반도체장치가 평형상태이므로 PNPN 에너지 밴드 다이어그램은 전자와 정공의 이동이 없다. 도면에서, P+(Vout)로 표시된 부위는 P형콘택층(250)이고, N+ 는 제 1 및 제 3 불순물영역(220)(242)이고, P+ 는 제 2불순물영역(230)이다.3A is an equilibrium PNPN energy band diagram. Since the P-type contact layer 250 is doped with P +, it has a plurality of holes, and the first and third impurity regions 220 and 242 are doped with N +. Electrons, and the N well 212 is N−, and thus has fewer electrons than the first and third impurity regions 220 and 242. Since the semiconductor device is in an equilibrium state, the PNPN energy band diagram does not move electrons and holes. In the drawing, a portion indicated by P + (Vout) is a P-type contact layer 250, N + is a first and third impurity regions 220 and 242, and P + is a second impurity region 230. In FIG.

도 3b는 P형콘택층(250)에 오버-슈트(over-shoot)를 가했을 때의 PNPN 에너지 밴드 다이어그램이다. 상기에서 P형콘택층(250)에 전압을 인가하여 오버-슈트되면 에너지 레벨이 낮아진다. 그러므로, P형콘택층(250)의 정공이 N웰(212)로 확산되고 N웰(212)의 전자가 P형콘택층(250)으로 확산된다. 따라서, P콘택층(250)은 전류밀도가 분산된다.3B is a PNPN energy band diagram when an over-shoot is applied to the P-type contact layer 250. When the voltage is applied to the P-type contact layer 250 and over-shooted, the energy level is lowered. Therefore, holes in the P-type contact layer 250 diffuse into the N well 212 and electrons in the N well 212 diffuse into the P-type contact layer 250. Therefore, the current density of the P contact layer 250 is dispersed.

도 3c 는 P형 콘택층(250)에서 홀 드리프트전류가 제 2불순물영역(230)으로 가서 제 2불순물영역(230)을 따라 전류가 분산될 때의 PNPN 에너지 밴드 다이어그램으로, 제 2불순물영역(230)을 따라서 전류밀도가 분산된다.3C is a PNPN energy band diagram when the hole drift current in the P-type contact layer 250 goes to the second impurity region 230 and current is dispersed along the second impurity region 230. 230, current density is dispersed.

따라서, 도 3b 및 도 3c 에서 살펴보듯이, P형 콘택층(250)과 제 2불순물영역(230)을 따라서 전류밀도가 분산되어 P+ 트리거링(triggering)에 의한 PNPN 랫치업 발생을 억제한다.Accordingly, as shown in FIGS. 3B and 3C, current densities are distributed along the P-type contact layer 250 and the second impurity region 230, thereby suppressing PNPN latch-up generation due to P + triggering.

도 3d 는 평형상태의 NPNP 에너지 밴드 다이어그램으로, N형 콘택층(252)은 N+로 도핑되므로 다수 개의 전자를 가지고, 제 2 및 제 4 불순물영역(230)(244)은 P+로 도핑되므로 다 수개의 정공을 가지며, 또한, P웰(218)은 P-이므로 제 2 및 제 4 불순물영역(230)(244) 보다 적은 수의 정공를 갖는다.3D is an equilibrium NPNP energy band diagram, in which the N-type contact layer 252 is doped with N + and thus has a plurality of electrons, and the second and fourth impurity regions 230 and 244 are doped with P +. Holes and the P well 218 is P−, and thus has fewer holes than the second and fourth impurity regions 230 and 244.

도 3e 는 N형 콘택층(252)에 언더-슈트를 가할 때 NPNP 에너지 밴드 다이어그램이다.3E is an NPNP energy band diagram when applying an under-shoot to the N-type contact layer 252.

상기에서 N형 콘택층(252)에 전압을 인가하여 언더-슈트되면 에너지 레벨이 낮아진다. 그러므로, N형 콘택층(252)의 전자가 P웰(218)로 확산되고 P웰(218)의 정공이 N형 콘택층(252)로 확산된다. 따라서, N형 콘택층(252)은 전류밀도가 분산된다.When the voltage is applied to the N-type contact layer 252 and under-shoot, the energy level is lowered. Therefore, electrons in the N-type contact layer 252 diffuse into the P well 218 and holes in the P-well 218 diffuse into the N-type contact layer 252. Therefore, the N-type contact layer 252 is dispersed in the current density.

도 3f 는 N형 콘택층(252)에서 전자 드리프트전류가 제 1불순물영역(220)으로 가서 제 1불순물영역(220)을 따라 전류가 분산될 때의 NPNP 에너지 밴드 다이어그램이다.FIG. 3F is an NPNP energy band diagram when the electron drift current in the N-type contact layer 252 goes to the first impurity region 220 and current is dispersed along the first impurity region 220.

따라서, 도 3e 및 도 3f에서 살펴보듯이, N형 콘택층(252)와 제 1불순물영역(220)을 따라서 전류밀도가 분산되어 N+트리거링(triggering)에 의한 NPN P 랫치업 발생을 억제한다.Accordingly, as shown in FIGS. 3E and 3F, current densities are distributed along the N-type contact layer 252 and the first impurity region 220 to suppress NPN P latch-up generation due to N + triggering.

상술한 바와 같이, 본 발명에서는 P형 콘택층에 오버-슈트를 가했을 때의 P형 콘택층과 제 2불순물영역을 따라서 전류밀도가 분산되어 P+ 트리거링에 의한 PNPN 랫치업 발생을 억제하며, N형 콘택층에 언더-슈트를 가할 때 N형 콘택층과 제 1불순물영역을 따라서 전류밀도가 분산되어 N+트리거링에 의한 NPNP 랫치업 발생을 억제하는 잇점이 있다.As described above, in the present invention, the current density is distributed along the P-type contact layer and the second impurity region when the over-shoot is applied to the P-type contact layer, thereby suppressing the occurrence of PNPN latch-up due to P + triggering, and the N-type When under-shoot is applied to the contact layer, the current density is distributed along the N-type contact layer and the first impurity region, thereby suppressing NPNP latchup generation due to N + triggering.

Claims (1)

반도체기판 상에 소자 격리영역을 정의하는 트렌치를 형성하는 공정과,Forming a trench defining a device isolation region on the semiconductor substrate; 상기 트렌치의 일측에 제 1도전형인 제 1불순물영역을 형성하는 공정과,Forming a first impurity region of a first conductivity type on one side of the trench; 상기 트렌치의 타측에 제 2도전형인 제 2불순물영역을 형성하는 공정과,Forming a second impurity region of a second conductivity type on the other side of the trench; 상기 트렌치를 채우도록 갭필층을 형성하는 공정과,Forming a gapfill layer to fill the trench; 상기 제 1불순물영역을 포함하는 부위에 제 1도전형인 제 1웰을 형성하는 공정과,Forming a first well having a first conductivity type in a portion including the first impurity region; 상기 제 2불순물영역을 포함하는 부위에 제 2도전형인 제 2웰을 형성하는 공정과,Forming a second well having a second conductivity type in a portion including the second impurity region; 상기 제 1웰 하부에 제 1도전형인 제 3불순물영역을 형성하는 공정과,Forming a third impurity region having a first conductivity type under the first well; 상기 제 2웰 하부에 제 2도전형인 제 4불순물영역을 형성하는 공정을 구비한 반도체장치의 제조방법.And forming a fourth impurity region of a second conductivity type in a lower portion of said second well.
KR1019970078773A 1997-12-30 1997-12-30 Method of fabricating semiconductor device KR100247704B1 (en)

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