JP2006147768A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can stably reduce a shadow region where ions cannot be implanted during an oblique ion implantation step and has an appropriate structure for microfabrication, and to provide its manufacturing method. <P>SOLUTION: The manufacturing method includes a step to form an insulated separation layer 13 so as to divide a p-type well area 12 into first and second areas; a step to form both a first gate electrode 16 which is formed in the first area 12a apart from the insulated separation layer 13, and a second gate electrode 17 which bridges the insulated separation layer 13 and a second area 12b facing the first gate electrode 16 at the same time; a step to implant p-type impurity ions to the first area 12a from a direction declined by a specified angle from the vertical direction while the one end of the second gate electrode 17 is used as a mask, and furthermore to implant n-type impurity ions from the vertical direction so as to form source/drain areas 19 and 20; and a step to form a well contact layer 21 in the second area 12b by using the other end of the second gate electrode 17 as a mask. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly provides a semiconductor device having a structure suitable for miniaturization and a manufacturing method thereof.

  As semiconductor devices are highly integrated, miniaturization of MOS transistors and optimization of circuit pattern layout are required in order to suppress an increase in chip size.

  With the miniaturization of MOS transistors, short channel effects such as punch-through are more likely to occur when the channel length is shortened. Impurity ions are introduced into a shallow region under the gate electrode, thereby generating short channel effects such as punch-through. Suppressed.

  Conventionally, in an oblique ion implantation process used to introduce impurity ions into a shallow region under a gate electrode, a photoresist pattern opposite to the gate electrode pattern and spaced apart from the gate electrode pattern is formed on the semiconductor substrate. Is used as a block layer that blocks implantation of impurity ions implanted from a direction inclined by a predetermined angle from the vertical direction of the substrate.

  However, since the impurity ions are blocked by the photoresist pattern and a shadow region where no impurity ions are implanted is formed, there is a problem that improvement in the integration degree of the semiconductor device is hindered.

  On the other hand, a method is known in which an area where ions cannot be implanted due to a shadow of the block layer in the oblique ion implantation process is reduced, and the integration degree of the semiconductor device is improved (see, for example, Patent Document 1).

  In the method of manufacturing a semiconductor device disclosed in Patent Document 1, a step of forming a gate electrode pattern on a semiconductor substrate, a step of forming a photoresist on the semiconductor substrate and on the electrode pattern, and the surface of the photoresist is an electrode pattern. The step of thinning the photoresist so as to be the same height as the surface of the substrate, the step of patterning the photoresist, and the semiconductor substrate on which the electrode pattern and the photoresist are formed are predetermined from the direction perpendicular to the surface of the semiconductor substrate. And a step of implanting impurity ions from a tilted direction.

  That is, after a photoresist thicker than the gate electrode is formed, the photoresist is polished using a CMP (Chemical Mechanical Polishing) method or the like so that the surface height of the photoresist is the same as the surface of the gate electrode pattern. As a result, the shadow region due to the oblique ion implantation is reduced and the integration degree of the semiconductor device is improved as compared with the thick photoresist.

However, when the photoresist is thinned by polishing, since the photoresist is softer than the gate electrode, it tends to be thinner than the gate electrode.
If the photoresist becomes too thin, there is a problem that the implanted ions penetrate the photoresist and cannot prevent the intrusion of ions.

Also, since the patterning of the gate electrode and the patterning of the photoresist are performed in separate processes, the gap between the gate electrode pattern and the photoresist pattern is shifted depending on the alignment accuracy of the exposure apparatus, and the oblique ion implantation is performed. There is a problem that the length of the shadow region varies.
JP 2003-45819 A (page 4, FIG. 3)

  The present invention provides a semiconductor device having a structure suitable for miniaturization, and a method for manufacturing the same, by stably reducing shadow regions that cannot be ion-implanted in an oblique ion implantation process.

  In order to achieve the above object, in the method for manufacturing a semiconductor device of one embodiment of the present invention, the well region is partitioned into first and second regions on the surface of the first conductivity type well region on the surface of the semiconductor substrate. A step of forming an insulating isolation layer; a first gate electrode provided in the first region apart from the insulating isolation layer; straddling the insulating isolation layer and the second region; and the first gate. A step of simultaneously forming a second gate electrode opposite to the electrode, and a first region having an opening exposing the first region including the first gate electrode and the second gate electrode portion on the first gate electrode side. A step of forming a photoresist pattern on the surface of the semiconductor substrate, and using the first and second gate electrodes as a mask, the first conductivity type impurity ions are introduced from a direction inclined by a predetermined angle from the vertical direction of the semiconductor substrate. Implanting into the first region, and further implanting second conductivity type impurity ions into the first region from the vertical direction of the semiconductor substrate to form source / drain regions, and removing the first photoresist pattern. Forming a second photoresist pattern on the surface of the semiconductor substrate, the second photoresist pattern having an opening exposing the second region including a part of the second gate electrode in the second region; and Forming a contact means to the second region as a mask.

  In the semiconductor device of one embodiment of the present invention, a semiconductor substrate, a first conductivity type well region formed on the surface of the semiconductor substrate, a well region formed on the surface of the well region, and the well region defined by the first and first well regions. An insulating isolation layer partitioned into two regions; a first gate electrode formed in the first region spaced apart from the insulating isolation layer; straddling the insulating isolation layer and the second region; and A second gate electrode formed opposite to the gate electrode; a first conductivity type impurity region formed in the first region adjacent to the first gate electrode; and the first conductivity type impurity region. And a second conductivity type source / drain region formed in the first region between the first and second insulating layers, and a first conductivity type formed in the second region adjacent to the second gate electrode. Having self-aligning contact means, It is a symptom.

  According to the method for manufacturing a semiconductor device of the present invention, a block layer having sufficient ion blocking ability and high pattern accuracy can be obtained.

  As a result, one block layer can stably reduce a shadow region where ions are not implanted using one end of the block layer as a mask in the oblique ion implantation process, and self-alignment contact can be performed using the other end of the block layer as a mask. By forming, the insulating space around the contact plug can be shortened.

  Therefore, a semiconductor device with a small chip size and a high degree of integration can be provided by miniaturization.

  Embodiments of the present invention will be described below with reference to the drawings.

  1A and 1B are diagrams showing a main part of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view thereof, and FIG. 1B is cut along a line AA in FIG. FIG. 2 to FIG. 7 are views showing the manufacturing process of the semiconductor device, and are sectional views sequentially showing the process of manufacturing the MOS transistor of the semiconductor device.

  In this embodiment, by miniaturizing the MOS transistor, impurity ions are introduced into a shallow region under the gate electrode in order to suppress the occurrence of a short channel effect such as punch-through accompanying the shortening of the channel, and the electric field at the pn junction interface is reduced. A semiconductor having a double drain structure in which source / drain regions are formed of two types of impurity regions, a low concentration region and a high concentration region, and a MOS transistor having a self-aligned contact structure to the well region in order to relax and improve breakdown voltage It is an example of an apparatus.

  In this specification, “source / drain region” means “source region or drain region”.

  As shown in FIG. 1, a semiconductor device 10 of this embodiment includes a p-type well region 12 formed on a semiconductor substrate 11, for example, an n-type silicon substrate, and a p-type well region 12 as a first region 12a, a second region 12a, Insulating isolation layers (Shallow Trench Isolation: STI) 13 and 14 divided into 12b, the first gate electrode 16 formed in the first region 12a apart from the insulating isolation layer 13, the insulating isolation layer 13 and the second well layer A second gate electrode 17 formed over the first gate electrode 16 and opposite to the first gate electrode 16; and a p-type impurity region 18 formed in the first region 12a adjacent to the first gate electrode 16; And n-type source / drain regions 19 and 20 formed in the first region 12a between the impurity region 18 and the insulating isolation layer 13, and a well contact layer 21 formed in the second region 12b. Yes.

  Further, the contact plugs 22 and 23 are electrically connected to the well contact layer 21 and the source region 19, respectively, and an interlayer insulating film 25 for preventing a short circuit between the contact plugs 22 and 23. The well contact plug 22 Forms a self-aligned contact adjacent to the second gate electrode 17 on the p-type well region 12.

  The first and second gate electrodes 16 and 17 are formed with offset spacers 26 and 27 for protecting the upper surface and side surfaces, respectively, and the source / drain regions 19 and 20 are for relaxing the electric field at the pn junction interface. A double drain structure 30 having a shallow high concentration layer and a deep low concentration layer is formed.

Next, a method for manufacturing the semiconductor device 10 will be described. First, as shown in FIG. 2, a protective film 50 in which, for example, a silicon oxide film, a silicon nitride film, and a TEOS film are stacked is formed on the surface of the semiconductor substrate 11 on which the p-type well region 12 is formed, and photolithography technology is applied. Then, the trench opening is patterned, and the protective film 50 is etched into a predetermined shape by anisotropic etching, for example, RIE to expose a part of the upper surface of the semiconductor substrate 11.
Next, the semiconductor substrate 11 is etched by anisotropic etching using the TEOS film as a mask to form, for example, a trench having a depth of about 0.3 μm.
Next, after thermally oxidizing the inner wall of the trench, for example, a silicon oxide film is formed by a CVD method and the trench is embedded to insulate the p-type well region 12 into the first and second regions 12a and 12b. Separation layers 13 and 14 are formed.

Next, as shown in FIG. 3, a silicon oxide film is formed to a thickness of about 8 nm on the entire surface by using, for example, a thermal oxidation method. This silicon oxide film becomes the gate insulating film 51. Next, a polysilicon film is formed to a thickness of about 100 nm on the entire surface by CVD.
Then, a tungsten silicide film is formed to a thickness of about 55 nm on the upper surface of the polysilicon film by using, for example, a sputtering method. Further, for example, a CVD method is used to form a silicon nitride film on the upper surface of the tungsten silicide film to a thickness of about 150 nm.
Further, using a resist (not shown) patterned in a predetermined shape on the upper surface of the silicon nitride film as a mask, the silicon nitride film, the tungsten silicide film, and the polysilicon film using anisotropic etching, for example, RIE (Reactive Ion Etching) method Etch.

  The silicon nitride film, the tungsten silicide film, and the polysilicon film become the first and second gate electrodes 16 and 17, and are separated from the first gate electrode 16 provided in the first region 12a so as to be separated from the insulating separation layer 13. A second gate electrode 17 straddling the layer 13 and the second region 12b and facing the first gate electrode 16 is simultaneously formed.

Next, as shown in FIG. 4, a photoresist film is formed on the surface of the semiconductor substrate 11 on which the first and second gate electrodes 16 and 17 are formed, and a part of the second gate electrode 17 is formed by photolithography. The first photoresist pattern 52 is formed by patterning the openings of the source / drain regions 19 and 20 so as to be exposed.
Next, boron (B) ions are applied to the first region from a direction inclined by a predetermined angle θ from a direction perpendicular to the near-conductor substrate 11 using the partially exposed second gate electrode 17 and the first photoresist pattern 52 as a mask. 12a is ion-implanted at an acceleration voltage of 20 KeV and a dose of about 1E13 atoms / cm 2 to form a p-type impurity region 18.

  Here, the distance L1 between the first gate electrode 16 and the second gate electrode 17 is the length L2 of the source region 19 and the length L3 of the shadow region where B ions incident obliquely by the second gate electrode 17 are not implanted. It is set equal to the sum.

  The length L2 of the source region 19 may be appropriately determined based on the required specifications of the MOS transistor. For example, the length L3 of the shadow region is 330 nm, for example, the oblique incident angle θ is 20 °, and the second gate electrode 17 When the height H1 is 300 nm, L3 = H1 × tan (θ) is 110 nm.

  Next, as shown in FIG. 5, using the exposed second gate electrode 17 and the first photoresist pattern 52 as a mask, arsenic (As) ions are applied to the first region 12a in an acceleration voltage of 10 KeV from a direction perpendicular to the semiconductor substrate 11. Ions are implanted at a dose of about 1E15 atoms / cm 2 to form a low concentration layer 53 having a double drain structure.

Next, as shown in FIG. 6, after the first photoresist pattern 52 is once removed, a silicon nitride film is formed on the surface of the semiconductor substrate 11 on which the first and second gate electrodes 16 and 17 are formed, and RIE is performed. The offset spacers 26 and 27 are formed on the upper and side surfaces of the first and second gate electrodes 16 and 17, respectively, by selective processing by the method.
Next, a photoresist film is formed on the surface of the semiconductor substrate 11 on which the first and second gate electrodes 16 and 17 are formed, and the source / source is so exposed that a part of the second gate electrode 17 is exposed by photolithography. The openings of the drain regions 19 and 20 are patterned to form a first photoresist pattern 54 again.
Next, As ions are implanted into the first region 12a at an acceleration voltage of 20 KeV and a dose of about 1E15 atoms / cm 2 from the direction perpendicular to the semiconductor substrate 11 using the exposed second gate electrode 17 and first photoresist pattern 54 as a mask. A high concentration layer 55 having a double drain structure is formed.

Next, as shown in FIG. 7, a photoresist film is formed on the surface of the semiconductor substrate 11 on which the first and second gate electrodes 16 and 17 are formed, and a part of the second gate electrode 17 is formed by photolithography. Then, the opening of the well contact layer 21 is patterned so that the second photoresist pattern 56 is formed.
Next, B ions are applied to the second region 12b at an acceleration voltage of 10 KeV and a dose of about 1E15 atoms / cm 2 from the direction perpendicular to the semiconductor substrate 11 using the second gate electrode 17 and the second photoresist pattern 56 that are partially exposed as a mask. The well contact layer 21 is formed by ion implantation.

  Here, the distance L4 between the insulating isolation layer 13 and the well contact 21 is set to a distance that can ensure electrical insulation of the self-aligned contact plug with respect to the second gate electrode 17, for example, about 110 nm.

Next, an interlayer insulating film 25, for example, a silicon oxide film is formed on the surface of the semiconductor substrate 11 on which the first and second gate electrodes 16 and 17 are formed by the CVD method, and the second gate is formed by the photolithography technique and the RIE method. A contact hole (not shown) of the well contact layer 21 is formed so that a part of the electrode 17 is exposed.
Next, polysilicon or tungsten doped with impurities is buried in the contact hole by a CVD method to form a self-aligned contact plug 22 for the second gate electrode 17.

  Next, the contact plug 23 in the source region 19 and the contact plug (not shown) in the drain region 20 are formed in the same manner, thereby completing the semiconductor device 10 shown in FIG.

  8A and 8B are diagrams showing the effect of miniaturization by the second gate electrode 17 in comparison with the conventional example. FIG. 8A shows the case of this embodiment and FIG. 8B shows the case of the conventional example.

  As shown in FIG. 8A, the second gate electrode 17 straddling the insulating separation layer 13 and the second region 12b and facing the first gate electrode is formed simultaneously with the first gate electrode 16. As shown in FIG. 6, when the resist opening end deviates from the boundary between the MOS transistor part A and the well contact part B and reaches the well contact activation region C due to process variations, the second gate electrode 17 becomes a block layer. It is possible to prevent erroneous implantation of As ions for forming source / drain regions in the well contact activation region C.

  In addition, since a self-aligned contact with the second gate wiring 17 is used for the contact plug 22 to the well contact layer 21, a necessary space between the second gate wiring 17 and the contact plug 22 can be reduced.

  Therefore, the distance L5 from the source region 19 to the well contact plug 22 is the length L3 (110 nm) of the shadow region, the distance L4 (110 nm) between the insulating separation layer 13 and the second gate electrode 17, and the alignment of the exposure apparatus. Considering an error, for example, 170 nm, about 340 nm is sufficient.

On the other hand, as shown in FIG. 8B, when the block layer formed on the insulating isolation layer 63 that electrically isolates the MOS transistor portion E and the well contact portion F is a conventional photoresist, the photoresist Is about 1000 nm, and the length L6 of the shadow region by oblique ion implantation is about 360 nm.
In consideration of the alignment error of the exposure apparatus, for example, 170 nm, the length L7 of the insulating separation layer 63 is equal to the length L6 of the shadow area and the position of the exposure apparatus in order to prevent the defect that the oblique ion implantation is not performed in the source region 19. The sum of the alignment errors needs to be about 530 nm.

  In addition, in the As ion implantation process for forming the source / drain regions, insulation isolation is performed in order to prevent As ions from being erroneously implanted into a part of the well contact activation region C due to the displacement of the block layer. Since the overlap length of the layer 63 and the block layer needs to allow for an alignment error of the exposure apparatus, an appropriate length L7 of the insulating separation layer 63 is about 530 nm.

  Therefore, the distance L8 from the source region 19 to the well contact plug 62 is about 640 nm which is the sum of the length L7 (530 nm) of the insulating separation layer 63 and the distance L4 (110 nm) between the insulating separation layer 63 and the well contact plug 62. is necessary.

  Accordingly, by using the second gate electrode 17 as a block layer, the distance from the source region 19 to the well contact plug 22 can be shortened from the conventional L8 (640 nm) to L5 (340 nm).

  As described above, according to the method of manufacturing a semiconductor device according to the embodiment of the present invention, the first gate electrode 16 and the second gate electrode 17 that becomes a block layer in the ion implantation process are formed simultaneously. A block layer having an excellent ion blocking ability and high pattern accuracy can be obtained.

As a result, one block layer can stably reduce a shadow region where ions are not implanted using one end of the block layer as a mask in the oblique ion implantation process, and self-alignment contact can be performed using the other end of the block layer as a mask. By forming, the insulating space around the contact plug can be shortened.
Therefore, a semiconductor device with a small chip size and a high degree of integration can be obtained by miniaturization.

  Here, the case where the source region 19 is formed in the first region 12a between the impurity region 18 and the insulating separation layer 13 has been described, but the case where the drain region 20 is formed can be similarly performed.

FIG. 1A is a plan view of a semiconductor device according to an embodiment of the present invention, FIG. 1B is a plan view thereof, and FIG. 1B is cut along a line AA in FIG. It is sectional drawing. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the Example of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the Example of this invention. The figure for demonstrating the effect of the 2nd gate electrode which concerns on the Example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor substrate 12 P-type well area | region 12a 1st area | region 12b 2nd area | region 13, 14, 63 Insulation isolation layer (STI)
16 First gate electrode 17 Second gate electrode 18 P-type impurity layer 19 Source region 20 Drain region 21, 61 Well contact layer 22, 23, 62 Contact plug 25 Interlayer insulating film 26, 27 Offset spacer 30 Double drain structure 50 Protection Film 51 Gate insulating films 52 and 54 First photoresist pattern 53 Low concentration layer 55 High concentration layer 56 Second photoresist pattern

Claims (4)

Forming a first gate electrode and a second gate electrode that are spaced apart from each other and opposite each other on the surface of the semiconductor substrate;
And implanting impurity ions from a direction inclined at a predetermined angle from the vertical direction of the semiconductor substrate using the second gate electrode as a mask to form an impurity region in the semiconductor substrate under the first gate electrode. A method of manufacturing a semiconductor device. Forming an insulating isolation layer on the surface of the first conductivity type well region on the surface of the semiconductor substrate so as to partition the well region into first and second regions;
A first gate electrode provided in the first region apart from the insulating isolation layer, and a second gate electrode straddling the insulating isolation layer and the second region and facing the first gate electrode And simultaneously forming
Forming a first photoresist pattern on the surface of the semiconductor substrate having an opening exposing the first region including the first gate electrode and the second gate electrode portion on the first gate electrode side;
Using the first and second gate electrodes as masks, impurity ions of the first conductivity type are implanted into the first region from a direction inclined by a predetermined angle from the vertical direction of the semiconductor substrate, and further from the vertical direction of the semiconductor substrate. Implanting two conductivity type impurity ions into the first region to form source / drain regions;
Removing the first photoresist pattern;
Forming a second photoresist pattern on the surface of the semiconductor substrate having an opening exposing the second region including a part of the second gate electrode in the second region;
Forming a contact means with respect to the second region using the second gate electrode as a mask.   The distance between the first gate electrode and the second gate electrode is such that when the first conductivity type impurity ions are implanted from the direction inclined by a predetermined angle from the length of the source / drain region and the vertical direction, 3. The method of manufacturing a semiconductor device according to claim 2, wherein the method is equal to a sum of a length of a shadow region blocked by the gate electrode and not ion-implanted. A semiconductor substrate;
A first conductivity type well region formed on the surface of the semiconductor substrate;
An insulating isolation layer formed on the surface of the well region and partitioning the well region into first and second regions;
A first gate electrode formed in the first region apart from the insulating separation layer;
A second gate electrode formed across the insulating isolation layer and the second region and facing the first gate electrode;
A first conductivity type impurity region formed in the first region adjacent to the first gate electrode;
A second conductivity type source / drain region formed in the first region between the first conductivity type impurity region and the insulating isolation layer;
A semiconductor device comprising: a first conductivity type self-alignment contact means formed adjacent to the second gate electrode in the second region.

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