JP2007335756A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method which can manufacture stably even when the miniaturization of element patterns advances without producing breakdown voltage deterioration, in the semiconductor device where a high breakdown voltage transistor and a low voltage drive transistor are formed in the same semiconductor substrate. <P>SOLUTION: On a semiconductor substrate 1, a conductive film 5 and an insulating film 6 are sequentially formed through gate oxide films 3, 4. The insulating film 6 and the conductive film 5 are sequentially etched as a resist pattern 7 as a mask, a patterned insulating film 8 and the laminate of a gate electrode 9 of the high breakdown voltage transistor are formed. An impurity is injected as inversely conductive to the semiconductor substrate 1 with the laminate as a mask. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a high voltage transistor and a low voltage driving transistor and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, semiconductor devices equipped with high voltage transistors that are driven with a voltage of several tens of volts to several tens of volts have been widely used. An example of this type of semiconductor device is a liquid crystal panel driving LSI (Large Scale Integrated Circuit). In order to realize high image quality of the liquid crystal panel, the liquid crystal panel driving LSI is required to have a high output voltage. A high breakdown voltage transistor having a breakdown voltage of 20 V or more is used as a transistor constituting a circuit that outputs the voltage. The liquid crystal panel driving LSI includes an output circuit and a logic circuit that controls the operation of the output circuit. It is essential that the logic circuit has low power consumption. For this reason, low voltage driving transistors that are driven at a voltage of 3.3 V or lower are used in the logic circuit.

  The liquid crystal panel driving LSI has a long shape in which about 400 output terminals are arranged in the longitudinal direction, and is arranged at the edge of the liquid crystal panel. The edge of the liquid crystal panel preferably has a minimum area, and it is required to further shorten the length in the short direction of the liquid crystal panel driving LSI. At the same time, with the increase in the number of pixels of the liquid crystal panel in recent years, further increase in the number of outputs is required for the LSI for driving the liquid crystal panel. On the other hand, the upper limit length of the liquid crystal panel driving LSI that can be formed as one chip is limited by the exposure range (for example, 20 mm or less) of the stepper used for exposure for pattern formation in the manufacturing process. For this reason, in the liquid crystal panel driving LSI, it is necessary to further reduce the occupied area on the chip of the high breakdown voltage transistor in order to realize the reduction in the length in the lateral direction and the increase in the number of outputs.

  As a structure of a semiconductor device in which a high breakdown voltage transistor and a low voltage driving transistor as described above are mounted on the same substrate and a manufacturing method thereof, for example, one described in Patent Document 1 is known. Hereinafter, a conventional method for manufacturing a semiconductor device will be described. 6 to 8 are process cross-sectional views illustrating a manufacturing process of a conventional semiconductor device. 6 to 8, the left side of the drawing is the high breakdown voltage transistor formation region 31, and the right side of the drawing is the low voltage drive transistor formation region 32.

  As shown in FIG. 6A, first, a gate oxide film 103 of a high breakdown voltage transistor is formed to a thickness of 20 nm to 50 nm on a P-type silicon substrate 101 having an element isolation oxide film 102 formed on the surface. Is done. Next, a polysilicon film 105 having a thickness of about 300 nm to 500 nm is formed on the gate oxide film 103. On the polysilicon film 105, as shown in FIG. 6B, a resist pattern 107 that covers the gate electrode formation region of the high voltage transistor is formed by lithography. Using the resist pattern 107 as a mask, the polysilicon film 105 is etched to form the gate electrode 109 of the high voltage transistor as shown in FIG.

Next, as shown in FIG. 6D, after a resist pattern 106 covering the low voltage driving transistor region is formed, phosphorus ions are implanted to form a low concentration impurity region 110 of the high breakdown voltage transistor. . The ion implantation is performed with continuous rotation or multi-step rotation in a state where the silicon substrate 101 is arranged at a predetermined tilt angle with respect to a plane perpendicular to the ion incident direction (hereinafter referred to as oblique incidence implantation). The implantation conditions are an acceleration energy of 70 keV to 150 keV and a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² .

  As shown in FIG. 6E, after the resist pattern 106 is removed, a heat treatment at 950 ° C. or higher is performed. By this processing, the low concentration impurity region 110 is diffused in the silicon substrate 101 as shown in FIG. For example, when heat treatment is performed at 1050 ° C. for 60 minutes, the low-concentration impurity region 110 is diffused in the lateral direction and enters about 0.3 μm to 0.4 μm below the gate electrode 109.

  When the heat treatment is completed, as shown in FIG. 7B, after the resist pattern 108 covering the high breakdown voltage transistor formation region 31 is formed, the threshold voltage Vt of the low voltage drive transistor is applied to the low voltage drive transistor formation region 32. Channel injection for adjustment is performed. When the channel implantation is completed, the gate oxide film 103 formed in the low voltage driving transistor formation region 32 is removed (FIG. 7C).

  After the resist pattern 108 is removed, a gate oxide film 104 is formed in the low voltage drive transistor formation region 32 by thermal oxidation or the like, as shown in FIG. At this time, an oxide film is also formed on the surface of the gate electrode 109 of the high voltage transistor.

  When the formation of the gate oxide film 104 is completed, a polysilicon film 117 having a thickness of about 150 nm to 350 nm is formed on the entire surface of the silicon substrate 101 as shown in FIG. Further, a resist pattern 113 is formed on the polysilicon film 117 so as to cover the gate electrode formation region of the low voltage driving transistor. Etching is performed using the resist pattern 113 as a mask, and as shown in FIG. 8A, the gate electrode 114 of the low voltage driving transistor is formed. Note that the resist pattern 113 is removed after the etching process.

When the resist pattern 113 is removed, a resist pattern 115 that covers the high breakdown voltage transistor formation region 31 is formed. Using the resist pattern 115 as a mask, phosphorus ions are ion-implanted into the low-voltage driving transistor formation region 32 to form a low-concentration impurity region 116 (FIG. 8B). The ion implantation is performed under the conditions of an oblique energy implantation under the conditions of an acceleration energy of 70 keV to 150 keV and an implantation dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² , similar to the ion implantation for the high breakdown voltage transistor described above. Is done.

When the formation of the low concentration diffusion region 116 of the low voltage driving transistor is completed, the resist pattern 115 is removed, and an oxide film 111 is deposited on the silicon substrate 101 as shown in FIG. The oxide film 111 is formed by a low pressure CVD (Chemical Vapor Deposition) method using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. Thereafter, anisotropic dry etching is performed on the oxide film 111. As shown in FIG. 8D, sidewall spacers 112a and 112b each having a width of 100 nm to 200 nm are formed on the side surfaces of the gate electrode 109 and the gate electrode 114, respectively. Formed. Then, arsenic ions are ion-implanted using the gate electrodes 109 and 114 and the side wall spacers 112a and 112b as masks, thereby forming a high concentration impurity region 119 functioning as a source region or a drain region (FIG. 8E).
JP 2001-308197 A

  In order to ensure the breakdown voltage of the high breakdown voltage transistor, the low concentration impurity region of the high breakdown voltage transistor needs to be formed at a relatively deep position in the silicon substrate. In the technique described in Patent Document 1, the impurity region is thermally diffused by heat treatment at a relatively high temperature to form the low-concentration impurity region 116 of the high breakdown voltage transistor (FIGS. 6E and 7A). . However, in recent semiconductor devices having a fine element pattern, various material films constituting the element are thinned in order to enable processing of the fine element pattern. In the semiconductor device, heat treatment at a low temperature is indispensable in order to realize a shallow junction corresponding to the miniaturization of the element pattern. Therefore, it is difficult to apply the technique of Patent Document 1 in which the low-concentration impurity region is diffused deeply by high-temperature heat treatment.

  On the other hand, as a method of forming a deep impurity region without using thermal diffusion, there is a method of performing ion implantation with high acceleration energy. However, when the thickness of the gate electrode 109 of the high breakdown voltage transistor is reduced in accordance with the miniaturization of the element pattern, impurity ions penetrate through the gate electrode 109 which is a mask during ion implantation. This makes it impossible to form a transistor. Such penetration of impurity ions can be suppressed by setting the thickness of the gate electrode 109 to 300 nm or more, but it becomes difficult to process the gate electrode 109 into a fine pattern, and the element size of the high voltage transistor is reduced. I can't. In addition, in the technique described in Patent Document 1 described above, when the thickness of the gate electrode 109 is increased, the step of forming the gate electrode 114 of the low-voltage driving transistor (FIGS. 7E and 8A). ), The polysilicon film 111 is not completely etched and tends to remain on the side surfaces of the gate electrode 109. The polysilicon film 111 remaining on the side surface of the gate electrode 109 causes a problem that the electrical characteristics and long-term reliability of the completed semiconductor device are deteriorated. Further, in order to prevent the polysilicon film 111 from remaining, it may be possible to perform over-etching. However, there arises a problem that the processing accuracy of the gate electrode 114 formed simultaneously by the etching is lowered.

  In the conventional method for manufacturing a semiconductor device, the sidewall spacers of the high breakdown voltage transistor and the low voltage driving transistor are formed simultaneously. That is, the distance between the high concentration impurity region functioning as the source region or the drain region and the gate electrode is substantially the same in each transistor. Therefore, there are few degrees of freedom in setting and adjusting the electrical characteristics (characteristics such as current drive capability and breakdown voltage) of each transistor, and it is very difficult to optimize the electrical characteristics of the high breakdown voltage transistor and the low voltage drive transistor. Met.

  Further, in the above conventional semiconductor device manufacturing method, the gate electrode 109 of the high breakdown voltage transistor and the gate electrode 114 of the low voltage driving transistor are formed by processing the polysilicon films 105 and 111 deposited separately, respectively. Yes. This complicates the manufacturing process and increases the manufacturing cost.

  The present invention has been proposed in view of the above-described conventional circumstances, and provides a high voltage transistor and a low voltage driving transistor that can be stably manufactured even when the element pattern is miniaturized. An object of the present invention is to provide a provided semiconductor device and a manufacturing method thereof.

  In order to achieve the above object, the present invention employs the following technical means. First, the present invention is premised on a method for manufacturing a semiconductor device including a high breakdown voltage transistor and a low voltage driving transistor on a surface portion of a first conductivity type semiconductor layer. And the manufacturing method of the 1st semiconductor device concerning the present invention manufactures a semiconductor device as follows. First, a first gate insulating film is formed in a high breakdown voltage transistor formation region on a semiconductor layer. Further, a second gate insulating film having a film thickness different from that of the first gate insulating film is formed in the low voltage driving transistor formation region. A conductive film is formed on the entire surface of the semiconductor layer on which the first and second gate insulating films are formed, and the first insulating film is formed on the conductive film. A first mask pattern is formed on the first insulating film to cover the gate electrode formation region and the low-voltage drive transistor formation region of the high breakdown voltage transistor. Using the first mask pattern as an etching mask, the first insulating film and the conductive film are etched. As a result, a stacked body of the gate electrode of the high voltage transistor having a conductive film pattern and the pattern of the first insulating film covering the gate electrode is formed on the first gate insulating film. Subsequently, a first conductivity type first low concentration impurity region is formed in the semiconductor layer of the high breakdown voltage transistor formation region using the stacked body as a mask. After the second insulating film is formed on the entire surface of the semiconductor layer, anisotropic etching is performed on the second insulating film and the first insulating film, so that the gate electrode of the high breakdown voltage transistor and the low voltage driving transistor are formed. The conductive film in the formation region is exposed. At this time, the first sidewall spacer made of the second insulating film is formed on the side surface of the gate electrode of the high voltage transistor. Next, a second mask pattern is formed to cover the exposed gate electrode formation region of the low voltage driving transistor and the high breakdown voltage transistor formation region of the conductive film. By etching the conductive film using the second mask pattern as an etching mask, the gate electrode of the low-voltage driving transistor is formed on the second gate insulating film. Further, the second conductivity type second low-concentration impurity region is formed in the semiconductor layer of the low-voltage drive transistor formation region using the gate electrode of the low-voltage drive transistor as a mask. Thereafter, a third insulating film is formed on the entire surface of the semiconductor layer, and anisotropic etching is performed on the third insulating film. Thereby, the second sidewall spacer is formed on the side surface of the gate electrode of the high voltage transistor and the side surface of the gate electrode of the low voltage driving transistor. Then, using the first sidewall spacer, the second sidewall spacer, the gate electrode of the high breakdown voltage transistor, and the gate electrode of the low voltage drive transistor as a mask, the semiconductor layer in the high breakdown voltage transistor formation region and the low voltage drive transistor formation region A second conductivity type high concentration impurity region is formed in the semiconductor layer.

  The second method for manufacturing a semiconductor device according to the present invention manufactures the semiconductor device as follows. That is, first, the first gate insulating film is formed in the high breakdown voltage transistor formation region on the semiconductor layer. In addition, a second gate insulating film having a thickness different from that of the first gate insulating film is formed in the low voltage driving transistor formation region on the semiconductor layer. A conductive film is formed on the entire surface of the semiconductor layer on which the first and second gate insulating films are formed, and the first insulating film is formed on the conductive film. A first mask pattern is formed on the first insulating film to cover the gate electrode formation region of the high breakdown voltage transistor and the low voltage drive transistor formation region. Using the first mask pattern as an etching mask, the first insulating film and the conductive film are etched. As a result, a stacked body of the gate electrode of the high voltage transistor made of the conductive film pattern and the pattern of the first insulating film covering the gate electrode is formed on the first gate insulating film. Subsequently, a first conductivity type first low concentration impurity region is formed in the semiconductor layer of the high breakdown voltage transistor formation region using the stacked body as a mask. After the second insulating film is formed on the entire surface of the semiconductor layer, anisotropic etching is performed on the second insulating film, and the first insulating film on the gate electrode of the high breakdown voltage transistor and the low voltage driving are performed. The first insulating film in the transistor formation region is exposed. At this time, the first sidewall spacer made of the second insulating film is formed on the side surface of the gate electrode of the high voltage transistor. Next, the first insulating film, the first gate insulating film, and the semiconductor layer are etched using the gate electrode of the high breakdown voltage transistor and the first sidewall spacer as an etching mask, so that the gate electrode of the high breakdown voltage transistor and the low breakdown voltage are reduced. The conductive film in the voltage driving transistor formation region is exposed. At this time, a groove is formed in the semiconductor layer not covered with the gate electrode of the high breakdown voltage transistor and the first sidewall spacer. Thereafter, a second mask pattern is formed to cover the gate electrode formation region of the low-voltage driving transistor and the high breakdown voltage transistor formation region of the exposed conductive film. By etching the conductive film using the second mask pattern as an etching mask, the gate electrode of the low-voltage driving transistor is formed on the second gate insulating film. Further, the second conductivity type second low-concentration impurity region is formed in the semiconductor layer of the low-voltage drive transistor formation region using the gate electrode of the low-voltage drive transistor as a mask. Thereafter, a third insulating film is formed on the entire surface of the semiconductor layer, and anisotropic etching is performed on the third insulating film. Thereby, the second sidewall spacer is formed on the side surface of the gate electrode of the high voltage transistor and the side surface of the gate electrode of the low voltage driving transistor. Then, using the first sidewall spacer, the second sidewall spacer, the gate electrode of the high breakdown voltage transistor, and the gate electrode of the low voltage drive transistor as a mask, the semiconductor layer in the high breakdown voltage transistor formation region and the low voltage drive transistor formation region A second conductivity type high concentration impurity region is formed in the semiconductor layer.

  On the other hand, from another viewpoint, the present invention can provide a semiconductor device that achieves the above object. First, a first semiconductor device according to the present invention includes a high voltage transistor and a low voltage driving transistor on a surface portion of a semiconductor layer. In the semiconductor device according to the present invention, the high breakdown voltage transistor includes a gate electrode formed on the semiconductor layer via the first gate insulating film. A first sidewall spacer is formed on the side surface of the gate electrode. A second sidewall spacer is formed on the side surface of the first sidewall spacer. In addition, low concentration impurity regions are formed in the semiconductor layer located on both sides of the gate electrode of the high breakdown voltage transistor. Further, high-concentration impurity regions are formed in the semiconductor layer located on both sides of the gate electrode of the high breakdown voltage transistor in a self-aligned manner with respect to the second sidewall spacer. On the other hand, the low-voltage driving transistor includes a gate electrode formed on the semiconductor layer via a second gate insulating film. Sidewall spacers are formed on the side surfaces of the gate electrode. Low concentration impurity regions are formed in the semiconductor layer located on both sides of the gate electrode of the low voltage driving transistor. Further, high-concentration impurity regions are formed in the semiconductor layer located on both sides of the gate electrode of the low-voltage drive transistor in a self-aligned manner with respect to the sidewall spacer of the low-voltage drive transistor.

  The second semiconductor device according to the present invention has the following configuration. In other words, the high breakdown voltage transistor includes a gate electrode formed on the semiconductor layer via the first gate insulating film. A first sidewall spacer is formed on the side surface of the gate electrode. In addition, a groove is formed in which the semiconductor layer located on both sides of the first sidewall spacer is dug down. A second sidewall spacer is formed across the side surface of the first sidewall spacer and the side surface of the groove. Furthermore, a low concentration impurity region is continuously formed over the semiconductor layer located on both sides of the gate electrode of the high breakdown voltage transistor, the side of the trench on the gate electrode side, and the bottom of the trench. In addition, a high concentration impurity region is formed in the semiconductor layer located at the bottom of the trench in a self-aligned manner with respect to the second sidewall spacer. On the other hand, the low-voltage driving transistor includes a gate electrode formed on the semiconductor layer via a second gate oxide film. Sidewall spacers are formed on the side surfaces of the gate electrode. Low concentration impurity regions are formed in the semiconductor layer located on both sides of the gate electrode of the low voltage driving transistor. Further, high-concentration impurity regions are formed in the semiconductor layer located on both sides of the gate electrode of the low-voltage drive transistor in a self-aligned manner with respect to the sidewall spacer of the low-voltage drive transistor.

  According to the present invention, when forming the low-concentration impurity region of the high breakdown voltage transistor, the gate electrode is covered with the insulating film having a significant thickness, and the substantial thickness of the gate electrode at the time of impurity ion implantation is reduced. It becomes larger than the conventional one. Therefore, impurity ions can be implanted at a high acceleration even in a manufacturing process of a fine semiconductor device, and a low-concentration impurity region having a desired depth can be easily formed even under a low-temperature heat treatment.

  In the present invention, the gate electrode of the high breakdown voltage transistor and the gate electrode of the low voltage driving transistor are formed from the same conductive film. In this case, the heat treatment after the implantation of ions into the high breakdown voltage transistor formation region causes outward diffusion of impurities such as phosphorus from the conductive film in the low voltage drive transistor formation region, and an unexpected oxide film on the surface of the conductive film. There is a concern about the deterioration of electrical characteristics due to the formation of. However, according to the present invention, since the insulating film covering the conductive film is deposited, it is possible to suppress the cause of the deterioration of the electrical characteristics. This suppression effect can be enhanced by using a silicon nitride film as the insulating film covering the conductive film. In addition, the number of steps can be reduced as compared with the case where each transistor is formed by processing different conductive films, and an effect that a semiconductor device can be manufactured at low cost can be obtained.

  Further, in the present invention, when the gate electrode of the low voltage driving transistor is formed, there is no film to be etched in the high breakdown voltage transistor forming region. Therefore, there is no possibility that the conductive film remains on the side surface of the gate electrode of the high voltage transistor, which has been a big problem in the conventional technology. For this reason, it is possible to easily form a low voltage driving transistor having a fine gate size without impairing the processing accuracy.

  As a result, it is possible to manufacture a semiconductor device having a high-performance high-breakdown-voltage transistor and a low-voltage driving transistor without deteriorating electrical characteristics in a fine manufacturing process.

  In addition, according to the present invention, the gate electrode of the high breakdown voltage transistor includes the sidewall spacer having a two-layer structure in which the first sidewall spacer and the second sidewall spacer are sequentially stacked on the side surface. . Further, the gate electrode of the low voltage driving transistor includes a third sidewall spacer formed simultaneously with the second sidewall spacer of the high breakdown voltage transistor. For this reason, the design freedom of the high voltage transistor and the low voltage driving transistor is increased as compared with the conventional one, and the electric characteristics of each transistor can be easily optimized.

  Further, according to the configuration of the present invention in which the high breakdown voltage transistor includes the groove portion, in addition to the above-described effect, an effect that a higher breakdown voltage can be realized can be obtained. In addition, since the area occupied by the high voltage transistor for realizing a desired breakdown voltage can be reduced, the cost and function of the semiconductor device can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, the present invention is embodied as a semiconductor device including an N-channel high breakdown voltage transistor and an N-channel low voltage driving transistor. In the case of the P-channel type, the following description can be similarly applied by reversing the conductivity type of the impurity region in the element.

(First embodiment)
The structure of the semiconductor device according to the first embodiment of the present invention will be described below together with the manufacturing method thereof with reference to the drawings. 1 to 3 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the present embodiment. 1 to 3, the left side in the drawing is a high breakdown voltage transistor formation region 31, and the right side in the drawing is a low voltage drive transistor formation region 32.

  In this embodiment, first, as shown in FIG. 1A, an element isolation insulating film 2 made of STI (Shallow Trench Isolation) or a field oxide film is formed on a semiconductor substrate 1 made of a P-type silicon substrate. Is done. In the surface portion of the semiconductor substrate 1, the high breakdown voltage transistor formation region 31 and the low voltage drive transistor formation region 32 are electrically isolated by the element isolation insulating film 2. A gate insulating film 3 (first insulating film) for a high breakdown voltage transistor is formed on the entire surface of the semiconductor substrate 1 on which the element isolation insulating film 2 is formed by a thermal oxidation method or the like. Next, as shown in FIG. 1B, a resist pattern 21 covering the high breakdown voltage transistor formation region 31 is formed. The gate insulating film 3 in the low voltage drive transistor formation region 32 is removed by etching using the resist pattern 21 as an etching mask. After the resist pattern 21 is removed by an organic solvent or the like, as shown in FIG. 1C, the low voltage driving having a film thickness of about 3 nm to 10 nm is formed in the low voltage driving transistor formation region 32 by a thermal oxidation method or the like. A gate insulating film 4 (second insulating film) for the transistor is formed. At this time, the thickness of the gate insulating film 3 increases as the gate insulating film 4 grows. In addition, the gate insulating film 3 is deposited by the process shown in FIG. 1A with a film thickness of about 20 nm to 50 nm. As described above, the gate insulating film 3 made of a relatively thick silicon oxide film is formed in the high breakdown voltage transistor forming region 31, and the relatively thin film thickness is formed in the low voltage driving transistor forming region 32. A gate insulating film 4 made of a silicon oxide film is formed.

  On the semiconductor substrate 1 on which the gate insulating film 3 and the gate insulating film 4 are formed, as shown in FIG. 1D, a conductive film 5 made of a conductive polysilicon film having a thickness of about 150 nm to 350 nm is formed. It is formed by a low pressure CVD method or the like. A silicon nitride film 6 (first insulating film) having a thickness of about 150 nm to 350 nm is formed on the conductive film 5 by a low pressure CVD method or the like.

Next, as shown in FIG. 1E, a resist pattern 7 (first mask pattern) covering the gate electrode formation region of the high breakdown voltage transistor and the low voltage drive transistor formation region 32 is formed on the silicon nitride film 6. It is formed by a known lithography technique. The silicon nitride film 6 and the conductive film 5 are etched using the resist pattern 7 as an etching mask. By this etching, as shown in FIG. 2A, a stacked body including the gate electrode 9 of the high breakdown voltage transistor and the silicon nitride film pattern 8 covering the gate electrode 9 is formed. The etching process can be performed, for example, by dry etching using SF ₆ (sulfur hexafluoride) gas or CF ₄ (carbon tetrafluoride) gas as a process gas. 2A shows a state in which the resist pattern 7 is removed by ashing or the like after the etching process.

After the resist pattern 7 is removed, as shown in FIG. 2B, N-type impurities such as phosphorus ions are introduced into the high breakdown voltage transistor formation region 31 by ion implantation or the like using the stacked body as a mask. The ion implantation is performed while the semiconductor substrate 1 is arranged at a predetermined tilt angle with respect to a plane perpendicular to the ion incident direction and is rotated continuously or multi-step (hereinafter referred to as oblique incidence implantation). The implantation conditions are, for example, an acceleration energy of about 70 keV to 150 keV and a dose amount of about 1 × 10 ¹² cm ⁻² to 1 × 10 ¹⁴ cm ⁻² . As a result, a first low-concentration impurity region 10 (hereinafter referred to as a high breakdown voltage LDD (Lightly Doped Drain) region 10) is formed in the semiconductor substrate 1 located on both sides of the gate electrode 9 (stacked body). In the present embodiment, a silicon nitride film pattern 8 is formed on the gate electrode 9. For this reason, even if ion implantation is performed using relatively high acceleration energy, impurity ions are prevented from penetrating the gate electrode 9 and entering the semiconductor substrate 1. Thereafter, the high voltage LDD region 10 is diffused at a high temperature of 900 ° C. or higher. As described above, in this embodiment, since ion implantation with high acceleration energy is possible, a high breakdown voltage is obtained to a depth that does not cause a practical problem by heat treatment at a relatively low temperature (or high temperature for a short time). The LDD region 10 can be formed.

  When the formation of the high breakdown voltage LDD region 10 is completed, as shown in FIG. 2C, a silicon oxide film 11 (second insulating film) is deposited on the entire surface of the semiconductor substrate 1 by a low pressure CVD method using TEOS as a raw material. The Then, the silicon oxide film 11, the silicon nitride film 6, and the silicon nitride film pattern 8 are etched by anisotropic dry etching using argon gas or the like as a process gas. By this etching, as shown in FIG. 2D, a side wall spacer 12 (first side wall spacer) having a width of about 100 nm to 200 nm is formed on the side surface of the gate electrode 9. When the etching is completed, the conductive film 5 is exposed in the low voltage driving transistor formation region 32. In the high breakdown voltage transistor formation region 31, the gate electrode 9 and the semiconductor substrate 1 located on both sides of the gate electrode 9 are exposed.

Subsequently, as shown in FIG. 2E, a resist pattern 13 (second mask pattern) covering the gate formation region of the low-voltage drive transistor and the high breakdown voltage transistor formation region 31 is formed by a known lithography technique. . The conductive film 5 is etched using the resist pattern 13 as an etching mask. By this etching, as shown in FIG. 3A, the gate electrode 14 of the low voltage driving transistor is formed. For example, the etching process can be performed by dry etching using SF ₆ gas, CF ₄ gas, Cl ₂ (chlorine) gas, or the like as a process gas. FIG. 3A shows a state in which the resist pattern 13 is removed by ashing or the like after the etching process.

  As described above, in the present embodiment, in the etching for forming the gate electrode 14, the conductive film 5 that is an etching target film does not exist in the high breakdown voltage transistor formation region 31. For this reason, the etching residue of the conductive film 5 does not occur on the side surface of the gate electrode 9. Therefore, it is not necessary to perform overetching or the like in order to avoid the conductive film 5 remaining, and the fine gate electrode 14 can be processed with high accuracy. In this embodiment, the gate electrode of the high voltage transistor and the gate electrode of the low voltage driving transistor are formed of the same conductive film. Conventionally, when the gate electrode is formed of the same conductive film, if the low-concentration impurity region 10 of the high breakdown voltage transistor as described above is subjected to thermal diffusion treatment, the electrical characteristics of the low voltage drive transistor may be deteriorated. there were. This deterioration in electrical characteristics is caused by the outward diffusion of phosphorus contained in the conductive film (polysilicon film) or the formation of an unexpected oxide film on the surface of the conductive film (polysilicon film) in the low-voltage drive transistor formation region 32. Due to being. However, in this embodiment, since the silicon nitride film 6 is deposited on the conductive film 5 made of a polysilicon film, such deterioration of the electrical characteristics is suppressed.

After the resist pattern 13 is removed, as shown in FIG. 3B, a resist pattern 15 that covers the high breakdown voltage transistor formation region 31 is formed by lithography. Then, using the resist pattern 15 and the gate electrode 14 as a mask, N-type impurities such as phosphorus ions are introduced into the low-voltage drive transistor formation region 31 by an ion implantation method or the like. As a result, second low concentration impurity regions 16 (hereinafter referred to as low voltage LDD regions 16) are formed in the semiconductor substrate 1 located on both sides of the gate electrode. The ion implantation is performed by oblique incidence implantation in the same manner as the ion implantation for the high breakdown voltage transistor described above. The ion implantation can be performed, for example, under conditions of an acceleration energy of about 10 keV to 30 keV and an implantation dose of about 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² .

  When the formation of the low voltage LDD region 16 is completed, the resist pattern 15 on the high breakdown voltage transistor forming region 31 is removed as shown in FIG. Thereafter, a silicon oxide film 17 (third insulating film) is deposited on the entire surface of the semiconductor substrate 1 by a low pressure CVD method using TEOS as a raw material. Then, the silicon oxide film 17 is etched by anisotropic dry etching using argon gas or the like as a process gas. By this etching, as shown in FIG. 3D, a side wall spacer 18a (second side wall spacer) having a width of about 50 nm to 100 nm is formed on the side surface of the side wall spacer 12 of the gate electrode 9. At the same time, a sidewall spacer 18b (second sidewall spacer) having a width of about 50 nm to 100 nm is formed on the side surface of the gate electrode 14.

Under this circumstance, as shown in FIG. 3E, N-type impurities such as arsenic ions are reduced in the high breakdown voltage transistor formation region 31 and the low voltage transistor formation region 31 using the gate electrodes 9 and 14 and the sidewall spacers 12, 18a and 18b as masks. It is introduced into the breakdown voltage driving transistor formation region 32. The ion implantation is performed in a state where the semiconductor substrate 1 is disposed at a tilt angle of 0 degree. The implantation conditions are, for example, an acceleration energy of about 20 keV to 50 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² or more. As a result, high-concentration impurity regions 19 (third impurity regions) functioning as source / drain regions are formed in the semiconductor substrate 1 located on both sides of the gate electrode 9 in a self-aligned manner with respect to the sidewall spacers 18a. Similarly, high-concentration impurity regions 19 functioning as source / drain regions are formed in the semiconductor substrate 1 located on both sides of the gate electrode 14 in a self-aligned manner with respect to the sidewall spacers 18b.

  Thereafter, a source electrode and a drain electrode made of metal constituting an ohmic contact are formed in the high-concentration impurity region 19, and a high breakdown voltage transistor and a low voltage driving transistor are completed. Note that the subsequent steps for forming an interlayer insulating film, a wiring layer, and the like on the semiconductor substrate are the same as those in a known method for manufacturing a semiconductor device, and thus description thereof is omitted here.

  As described above, in the method of manufacturing the semiconductor device according to the present embodiment, the insulating film (silicon nitride film 8) having a significant film thickness is formed on the gate electrode 9 when ion implantation for forming the high breakdown voltage LDD region 10 is performed. Is formed. For this reason, the substantial film thickness of the gate electrode at the time of the ion implantation is greatly increased to 300 nm to 700 nm. Therefore, ion implantation of impurities can be performed with relatively high acceleration energy, and a low concentration impurity region having a desired diffusion depth can be easily formed even by heat treatment at a relatively low temperature. In addition, although the gate electrodes of the high breakdown voltage transistor and the low voltage driving transistor are formed from the same conductive film, the electrical characteristics are not deteriorated. Furthermore, the gate electrode 14 of the low voltage driving transistor having a fine gate dimension can be formed with high accuracy. Therefore, a high breakdown voltage transistor and a low voltage drive transistor having a fine element pattern can be stably manufactured on the same semiconductor substrate.

  In the semiconductor device of this embodiment, sidewall spacers having different widths are formed in the high breakdown voltage transistor and the low voltage drive transistor. That is, the distance between the gate electrode and the source / drain region (high concentration impurity region) differs between the high voltage transistor and the low voltage driving transistor. For example, in a low voltage driving transistor, optimization of electrical characteristics including current driving capability can be easily performed by setting the width of the side wall spacer 18b independently. At this time, in the high breakdown voltage transistor, a high breakdown voltage can be realized by increasing the width of the sidewall spacer 12. Therefore, the high voltage transistor and the low voltage driving transistor can be optimized independently according to required electrical characteristics.

  In addition, since the high breakdown voltage transistor and the low voltage driving transistor are formed by processing the same conductive film 5, the cost is lower than when the gate electrode is formed by processing the separately deposited conductive film. A semiconductor device can be manufactured.

In the case described above, the impurity concentration of the high breakdown voltage LDD region 10 is about 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the low voltage LDD region 16 is 5 × 10 ¹⁸ cm ⁻³ to 5 × 10 ¹⁹ cm ^-3 or so, the impurity concentration of the high concentration impurity region 19 is suitably set to about ^{5 × 10 19 cm -3 ~5 ×} 10 20 cm -3.

  In the above description, the case where the first insulating film deposited on the conductive film 5 is the single-layer silicon nitride film 6 has been described. However, the first insulating film may be a multilayer film. For example, a silicon oxide film having a thickness of about 10 nm to 20 nm can be deposited between the conductive film 5 and the silicon nitride film 6. In this case, the silicon oxide film functions as a stopper film in the step of forming the sidewall spacer 12 (FIG. 2D). That is, by providing an insulating film that can ensure an etching selectivity with respect to the silicon nitride film 6 that is a film to be etched in the etching process, the reduction in the film thickness of the conductive film 5 can be minimized.

  Further, in the ion implantation step for forming the low voltage LDD region 16 (FIG. 3B), the ion implantation may be performed without forming the resist pattern 15 in the high breakdown voltage transistor forming region 31. In this case, the high breakdown voltage LDD region is composed of a first impurity region formed in a self-aligned manner with respect to the gate electrode 9 and a second impurity region formed in a self-aligned manner with respect to the sidewall spacer 12. Composed. Here, the concentration of the second impurity region is preferably higher than the concentration of the first impurity region. In this case, since the impurity concentration of the high breakdown voltage LDD region changes stepwise, the electric field concentration generated between the high concentration impurity region and the high breakdown voltage LDD region during operation of the high breakdown voltage transistor can be reduced. Therefore, the high breakdown voltage transistor can be further increased in voltage without increasing the number of steps.

(Second Embodiment)
Subsequently, the structure of the semiconductor device according to the second embodiment of the present invention will be described together with the manufacturing process with reference to the drawings. 4 and 5 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the present embodiment. Similar to FIGS. 1 to 3, in FIGS. 4 and 5, the left side in the drawing is the high breakdown voltage transistor formation region 31, and the right side in the drawing is the low voltage drive transistor formation region 32.

  In this embodiment, in the first embodiment, the same steps as those described with reference to FIGS. 1A to 1E, FIGS. 2A and 2B are performed, and FIG. As shown in a), a high breakdown voltage LDD region 10 (first low concentration impurity region) is formed in the high breakdown voltage transistor formation region 31. Therefore, the gate electrode 9 of the high breakdown voltage transistor is formed in the high breakdown voltage transistor region 31 via the gate insulating film 3, and the silicon nitride film pattern 8 is formed on the gate electrode 9. Further, the conductive film 5 and the silicon nitride film 6 are formed on the gate insulating film 4 in the low voltage driving transistor formation region 32.

  After the high breakdown voltage LDD region 10 is formed, as shown in FIG. 4B, a silicon oxide film 11 (second insulating film) is deposited on the entire surface of the semiconductor substrate 1 by a low pressure CVD method using TEOS as a raw material. The Then, the silicon oxide film 11 is etched by anisotropic dry etching using argon gas or the like as a process gas. By this etching, as shown in FIG. 4C, sidewall spacers 12 (first sidewall spacers) having a width of about 100 nm to 200 nm are formed on the side surfaces of the stacked body of the gate electrode 9 and the silicon nitride film pattern 8. It is formed. In the present embodiment, the silicon nitride film 6 is exposed in the low voltage driving transistor formation region 32 when the anisotropic etching is completed. In the high breakdown voltage transistor formation region 31, the semiconductor substrate 1 located on both sides of the silicon nitride film pattern 8 and the gate electrode 9 is exposed.

Subsequently, as shown in FIG. 4D, the silicon nitride film 6 and the silicon nitride film pattern 8 are removed by dry etching using SF ₆ gas or CF ₄ gas as a process gas. By this etching, the semiconductor substrate 1 exposed in the high breakdown voltage transistor region 31 (region not covered by the gate electrode 9 and the sidewall spacer 12) is also etched, and the groove portion 20 is formed in the semiconductor substrate located on both sides of the sidewall spacer 12. It is formed. The depth of the trench 20 is preferably shallower than the bottom surface of the element isolation insulating film 2 so that the high breakdown voltage transistor and other adjacent elements are electrically isolated. Needless to say, the high breakdown voltage LDD region 10 is formed to a depth that is not completely removed by the formation of the groove 20.

Subsequently, as shown in FIG. 4E, a resist pattern 13 (second mask pattern) covering the gate formation region of the low-voltage drive transistor and the high breakdown voltage transistor formation region 31 is formed by a known lithography technique. . Using the resist pattern 13 as an etching mask, the conductive film 5 is etched by dry etching using SF ₆ gas, CF ₄ gas, Cl ₂ gas or the like as a process gas. By this etching, as shown in FIG. 5A, the gate electrode 14 of the low voltage driving transistor is formed. FIG. 5A shows a state where the resist pattern 13 is removed by ashing or the like after the etching process.

  After the resist pattern 13 is removed, as shown in FIG. 5B, a resist pattern 15 that covers the high breakdown voltage transistor forming region 31 is formed by lithography. Then, using the resist pattern 15 and the gate electrode 14 as a mask, N-type impurities such as phosphorus ions are introduced into the low-voltage drive transistor formation region 32 by an ion implantation method or the like. As a result, a low voltage LDD region 16 (second low concentration impurity region) is formed in the semiconductor substrate 1 located on both sides of the gate electrode 14. The ion implantation can be performed under the implantation conditions exemplified in the first embodiment.

  After the resist pattern 15 on the high breakdown voltage transistor forming region 31 is removed, a silicon oxide film 17 (third insulating film) is deposited on the entire surface of the semiconductor substrate 1 by low pressure CVD using TEOS as a raw material (FIG. 5). (C)). Then, the silicon oxide film 17 is etched by anisotropic dry etching using argon gas or the like as a process gas. By this etching, as shown in FIG. 5D, side wall spacers 18a (second side wall spacers) having a width of about 50 nm to 100 nm are formed on the side surfaces of the side wall spacers 12 and the side surfaces of the groove portions 20 of the gate electrode 9. It is formed. At the same time, a sidewall spacer 18b (second sidewall spacer) having a width of about 50 nm to 100 nm is formed on the side surface of the gate electrode 14. Further, by this etching, the protruding portion of the side wall spacer 12 protruding above the upper surface of the gate electrode 9 formed when the silicon nitride film 6 is removed by etching (FIG. 4D) is also removed by etching.

  Under this situation, as shown in FIG. 5E, N-type impurities such as arsenic ions are reduced in the high breakdown voltage transistor formation region 31 and the low voltage transistor formation region 31 using the gate electrodes 9 and 14 and the sidewall spacers 12, 18 a and 18 b as masks. It is introduced into the breakdown voltage driving transistor formation region 32. The ion implantation can be performed under the implantation conditions exemplified in the first embodiment. As a result, a high concentration impurity region 19 functioning as a source / drain region is formed on the bottom surface of the trench 20 in a self-aligned manner with respect to the sidewall spacer 18a. Similarly, high-concentration impurity regions 19 functioning as source / drain regions are formed in the semiconductor substrate 1 located on both sides of the gate electrode 14 in a self-aligned manner with respect to the sidewall spacers 18b.

  Thereafter, a source electrode and a drain electrode made of metal constituting an ohmic contact are formed in the high-concentration impurity region 19, and a high breakdown voltage transistor and a low voltage driving transistor are completed. Note that the subsequent steps for forming an interlayer insulating film, a wiring layer, and the like on the semiconductor substrate are the same as those in a known method for manufacturing a semiconductor device, and thus description thereof is omitted here.

In this example, the impurity concentration of the high voltage LDD region 10 is about 5 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ , and the impurity concentration of the low voltage LDD region 16 is 5 × 10 ¹⁸ cm ^{−3 to} 5 × 5. × 10 ¹⁹ cm ^-3 or so, the impurity concentration of the high concentration impurity region 19 is suitably set to about ^{5 × 10 19 cm -3 ~5 ×} 10 20 cm -3.

  As described above, in the present embodiment, the high breakdown voltage transistor includes the groove 20 formed by digging down the semiconductor substrate 1 on both sides of the first sidewall spacer 12. In addition, a second sidewall spacer 18a is formed across the side surface of the first sidewall spacer 12 and the side surface of the groove portion 20, and the bottom surface of the groove portion 20 is high in a self-aligned manner with respect to the second sidewall spacer 18a. A concentration impurity region 19 is formed. For this reason, compared with the first embodiment, the substantial width of the sidewall spacer of the high breakdown voltage transistor is increased by the depth of the groove portion 20, so that a high breakdown voltage transistor having a higher breakdown voltage can be formed. Further, when forming a high breakdown voltage transistor having a breakdown voltage comparable to that of the first embodiment, the high breakdown voltage transistor can be formed smaller. Therefore, a semiconductor device having a function equivalent to that of the conventional one can be manufactured at a lower cost. In addition, a semiconductor device having a chip size equivalent to that of the conventional device can achieve high functionality such as multi-output. Needless to say, this embodiment has the effect described in the first embodiment.

  Also in the present embodiment, the first insulating film formed on the conductive film 5 is a multilayer film made of different insulating films that can ensure the etching selectivity, so that the conductivity in the etching process for forming the groove 20 is achieved. The film thickness reduction of the film 5 can be minimized. Further, by performing ion implantation without forming the resist pattern 15 in the step of forming the low voltage LDD region 16, the high breakdown voltage transistor can be further increased in voltage without increasing the number of steps.

  In addition, the above-mentioned embodiment shows a specific example and does not limit the technical scope of the present invention. The present invention can be variously modified and applied without departing from the technical idea of the present invention. For example, in the above description, each transistor is formed on a P-type semiconductor substrate, but each transistor may be formed on a P-type well formed on an N-type semiconductor substrate. In addition, it is not essential to form the gate insulating films having different film thicknesses in the high breakdown voltage transistor formation region and the low voltage driving transistor formation region by the above-described method, and can be formed by any method. Further, the materials of the conductive film and the insulating film are not limited to the above-described materials, and any material that can realize the above-described process can be used. In addition, it is needless to say that the semiconductor device formation process exemplified in the above embodiment can be replaced by a known equivalent process.

  The present invention is useful for improving performance and reducing manufacturing cost in a semiconductor device mounted with a high breakdown voltage transistor, represented by an LSI for driving a liquid crystal panel and the like, and a manufacturing method thereof.

Process sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention Process sectional drawing which shows the manufacturing method of the semiconductor device in the 1st Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention Sectional drawing which shows the manufacturing method of the semiconductor device in the 2nd Embodiment of this invention Process sectional view showing a conventional method of manufacturing a semiconductor device Process sectional view showing a conventional method of manufacturing a semiconductor device Process sectional view showing a conventional method of manufacturing a semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation insulating film 3 Gate insulating film (1st gate insulating film) of a high voltage transistor
4 Low voltage drive transistor gate insulating film (second gate insulating film)
5 Conductive film 6 Silicon nitride film (first insulating film)
7, 13, 15 Resist pattern 9 High breakdown voltage transistor gate electrode 10 High breakdown voltage LDD region (first low concentration impurity region)
11 Silicon oxide film (second insulating film)
12 Side wall spacer (first side wall spacer)
14 Low voltage drive transistor gate electrode 16 Low voltage LDD region (second low concentration impurity region)
17 Silicon oxide film (third insulating film)
18a Side wall spacer (second side wall spacer)
18b Side wall spacer 19 Source / drain region (high concentration impurity region)
20 Groove

Claims (14)

In a method for manufacturing a semiconductor device comprising a high breakdown voltage transistor and a low voltage drive transistor on a surface portion of a first conductivity type semiconductor layer,
Forming a first gate insulating film in a high breakdown voltage transistor formation region on the semiconductor layer;
Forming a second gate insulating film having a thickness different from that of the first gate insulating film in a low voltage driving transistor forming region on the semiconductor layer;
Forming a conductive film on the entire surface of the semiconductor layer on which the first and second gate insulating films are formed;
Forming a first insulating film on the conductive film;
Forming a first mask pattern covering the gate electrode formation region of the high breakdown voltage transistor and the low voltage drive transistor formation region on the first insulating film;
The first insulating film and the conductive film are etched using the first mask pattern as an etching mask, and the gate electrode of the high voltage transistor made of the conductive film pattern is formed on the first gate insulating film. Forming a laminate with a pattern of a first insulating film covering the gate electrode;
Forming a second conductivity type first low-concentration impurity region in the semiconductor layer of the high breakdown voltage transistor formation region using the stacked body as a mask;
Forming a second insulating film on the entire surface of the semiconductor layer;
Anisotropic etching is performed on the second insulating film and the first insulating film to form a first sidewall spacer made of the second insulating film on a side surface of the gate electrode of the high breakdown voltage transistor. And exposing the conductive film in the gate electrode of the high breakdown voltage transistor and the low voltage driving transistor formation region,
Forming a second mask pattern that covers the exposed gate electrode formation region of the low-voltage drive transistor of the conductive film and the high-breakdown-voltage transistor formation region;
Etching the conductive film using the second mask pattern as an etching mask to form a gate electrode of a low-voltage driving transistor on the second gate insulating film;
Forming a second conductivity type second low-concentration impurity region in the semiconductor layer of the low-voltage drive transistor formation region using the gate electrode of the low-voltage drive transistor as a mask;
Forming a third insulating film on the entire surface of the semiconductor layer;
Performing anisotropic etching on the third insulating film to form second side wall spacers on the side surfaces of the gate electrode of the high voltage transistor and the gate electrode of the low voltage driving transistor;
Using the first sidewall spacer, the second sidewall spacer, the gate electrode of the high breakdown voltage transistor, and the gate electrode of the low voltage drive transistor as a mask, the semiconductor layer in the high breakdown voltage transistor formation region and the low voltage drive transistor formation region Forming a second conductivity type high concentration impurity region in the semiconductor layer;
A method for manufacturing a semiconductor device, comprising:   The method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a multilayer film including films made of different materials.   2. The semiconductor device according to claim 1, further comprising a step of thermally diffusing the first low-concentration impurity region after forming the first low-concentration impurity region and before forming the second insulating film. Manufacturing method.   After forming the first sidewall spacer and before forming the third insulating film, the semiconductor in the high breakdown voltage transistor formation region using the gate electrode of the high breakdown voltage transistor and the first sidewall spacer as a mask. The method of manufacturing a semiconductor device according to claim 1, further comprising forming a second conductivity type impurity region in the layer. In a method for manufacturing a semiconductor device comprising a high breakdown voltage transistor and a low voltage drive transistor on a surface portion of a first conductivity type semiconductor layer,
Forming a first gate insulating film in a high breakdown voltage transistor formation region on the semiconductor layer;
Forming a second gate insulating film having a thickness different from that of the first gate insulating film in a low voltage driving transistor forming region on the semiconductor layer;
Forming a conductive film on the entire surface of the semiconductor layer on which the first and second gate insulating films are formed;
Forming a first insulating film on the conductive film;
Forming a first mask pattern covering the gate electrode formation region of the high breakdown voltage transistor and the low voltage drive transistor formation region on the first insulating film;
The first insulating film and the conductive film are etched using the first mask pattern as an etching mask, and the gate electrode of the high voltage transistor made of the conductive film pattern is formed on the first gate insulating film. Forming a laminate with a pattern of a first insulating film covering the gate electrode;
Forming a second conductivity type first low-concentration impurity region in the semiconductor layer of the high breakdown voltage transistor formation region using the stacked body as a mask;
Forming a second insulating film on the entire surface of the semiconductor layer;
The second insulating film is anisotropically etched to form a first sidewall spacer made of the second insulating film on the side surface of the gate electrode of the high breakdown voltage transistor, and the gate of the high breakdown voltage transistor Exposing the first insulating film on the electrode and the first insulating film in the low-voltage driving transistor formation region;
The first insulating film, the first gate insulating film, and the semiconductor layer are etched using the gate electrode of the high breakdown voltage transistor and the first sidewall spacer as an etching mask, and the gate electrode and the first sidewall of the high breakdown voltage transistor are etched. Forming a groove in the semiconductor layer not covered with the spacer, and exposing the conductive film in the gate electrode of the high breakdown voltage transistor and the low voltage driving transistor formation region;
Forming a second mask pattern covering the exposed gate electrode formation region of the low-voltage driving transistor and the high-breakdown-voltage transistor formation region of the conductive film;
Etching the conductive film using the second mask pattern as an etching mask to form a gate electrode of a low-voltage driving transistor on the second gate insulating film;
Forming a second conductivity type second low-concentration impurity region in the semiconductor layer of the low-voltage drive transistor formation region using the gate electrode of the low-voltage drive transistor as a mask;
Forming a third insulating film on the entire surface of the semiconductor layer;
Performing anisotropic etching on the third insulating film to form second side wall spacers on the side surfaces of the gate electrode of the high voltage transistor and the gate electrode of the low voltage driving transistor;
Using the first sidewall spacer, the second sidewall spacer, the gate electrode of the high breakdown voltage transistor, and the gate electrode of the low voltage drive transistor as a mask, the semiconductor layer in the high breakdown voltage transistor formation region and the low voltage drive transistor formation region Forming a second conductivity type high concentration impurity region in the semiconductor layer;
A method for manufacturing a semiconductor device, comprising:   6. The method of manufacturing a semiconductor device according to claim 5, wherein the first insulating film is a multilayer film including films made of different materials.   6. The semiconductor device according to claim 5, further comprising a step of thermally diffusing the first low-concentration impurity region after forming the first low-concentration impurity region and before forming the second insulating film. Manufacturing method.   After the trench is formed and before the third insulating film is formed, the second conductivity type is formed on the semiconductor layer in the high breakdown voltage transistor formation region using the gate electrode of the high breakdown voltage transistor and the first sidewall spacer as a mask. 6. The method of manufacturing a semiconductor device according to claim 5, further comprising a step of forming an impurity region.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the bottom surface of the groove is formed at a position shallower than the bottom surface of the element isolation insulating film that electrically isolates each transistor. In a semiconductor device comprising a high breakdown voltage transistor and a low voltage drive transistor on the surface of the semiconductor layer,
The high voltage transistor is
A gate electrode formed on the semiconductor layer via a first gate insulating film;
A first sidewall spacer formed on a side surface of the gate electrode;
A second sidewall spacer formed on a side surface of the first sidewall spacer;
A low concentration impurity region formed in a semiconductor layer located on both sides of the gate electrode;
A high concentration impurity region formed in a semiconductor layer on both sides of the gate electrode in a self-aligned manner with respect to the second sidewall spacer;
With
The low-voltage drive transistor is
A gate electrode formed on the semiconductor layer via a second gate insulating film;
A sidewall spacer formed on a side surface of the gate electrode of the low-voltage drive transistor;
A low concentration impurity region formed in a semiconductor layer located on both sides of the gate electrode of the low voltage driving transistor;
A high-concentration impurity region formed in a semiconductor layer located on both sides of the gate electrode of the low-voltage drive transistor in a self-aligned manner with respect to a sidewall spacer of the low-voltage drive transistor;
A semiconductor device comprising: The low concentration impurity region of the high breakdown voltage transistor is
A first impurity region formed in a self-aligned manner with respect to the gate electrode of the high breakdown voltage transistor;
A second impurity region having a higher concentration than the first impurity region, formed in a self-aligned manner with respect to the first sidewall spacer;
A semiconductor device according to claim 10. In a semiconductor device comprising a high breakdown voltage transistor and a low voltage drive transistor on the surface of the semiconductor layer,
The high voltage transistor is
A gate electrode formed on the semiconductor layer via a first gate insulating film;
A first sidewall spacer formed on a side surface of the gate electrode;
A groove part in which a semiconductor layer located on both sides of the first sidewall spacer is dug;
A second sidewall spacer formed across the side surface of the first sidewall spacer and the side surface of the groove;
A semiconductor layer located on both sides of the gate electrode, a side portion on the gate electrode side of the groove, and a low concentration impurity region continuously formed over the bottom of the groove;
A high concentration impurity region formed in a self-aligned manner with respect to the second sidewall spacer in the semiconductor layer located at the bottom of the groove;
With
The low-voltage drive transistor is
A gate electrode formed on the semiconductor layer via a second gate oxide film;
A sidewall spacer formed on a side surface of the gate electrode of the low-voltage drive transistor;
A low concentration impurity region formed in a semiconductor layer located on both sides of the gate electrode of the low voltage driving transistor;
A high-concentration impurity region formed in a semiconductor layer located on both sides of the gate electrode of the low-voltage drive transistor in a self-aligned manner with respect to a sidewall spacer of the low-voltage drive transistor;
A semiconductor device comprising: The low concentration impurity region of the high breakdown voltage transistor is
A first impurity region formed in a self-aligned manner with respect to the gate electrode of the high breakdown voltage transistor;
A second impurity region having a higher concentration than the first impurity region, formed in a self-aligned manner with respect to the first sidewall spacer;
A semiconductor device according to claim 12. 13. The semiconductor device according to claim 12, wherein a bottom surface of the groove is formed at a position shallower than a bottom surface of an element isolation insulating film that electrically isolates each transistor.

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