JP2007201337A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems that a PSG film and a BSG film are needed as thermal diffusion sources and processes are complicated when thermally diffusing the oppositely conductive impurities of a low concentration from an insulating film containing the oppositely conductive impurities, by not using ion implantation but using thermal treatment for forming a low concentration source/drain diffusion layer relating to a CMOS semiconductor device. <P>SOLUTION: In the semiconductor device and its manufacturing method by executing thermal treatment with only a PSG film or a BSG film as the thermal diffusion source, a shallow low concentration source/drain diffusion region can be easily formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a CMOS type semiconductor device having an LDD (Lightly Doped Drain) structure and a method for manufacturing the same.

  With the trend toward higher integration of semiconductor devices, source / drain punch-through due to the short channel effect becomes a problem in MOSFETs. In order to solve this problem, LDD structures have been developed so far. The LDD structure is formed by adding a region with a low impurity concentration in the vicinity of the channel side end of the source / drain. Since the electric field at the end of the source and the drain is relaxed and the breakdown voltage increases, punch-through due to the short channel effect described above can be prevented.

  In order to form this LDD structure, a gate electrode is formed on a one-conductivity-type semiconductor substrate via a gate oxide film, and then a reverse-conductivity type low-concentration impurity is implanted with low acceleration energy. Next, after forming a sidewall insulating film on the sidewall of the gate electrode, a reverse conductivity type high concentration impurity is implanted with high acceleration energy. As a result, a low concentration source / drain diffusion layer is formed in a shallow region below the sidewall insulating film, and a high concentration source / drain diffusion layer is formed in a deep region adjacent to the end of the sidewall insulating film.

  Thus, the low concentration source / drain diffusion layer is formed shallow by reducing the ion acceleration energy during ion implantation. However, it is difficult for the method using ion implantation to be formed shallow enough to satisfy the design rules of recent ultra-high integration elements. That is, the current common high-current ion implanter is possible with acceleration energy of 10 keV or less, but problems such as excavation of the semiconductor substrate occur due to the sputtering effect.

Therefore, various processes have been developed for forming low concentration source / drain diffusion layers by thermally diffusing low concentration reverse conductivity type impurities from an insulating film containing reverse conductivity type impurities by heat treatment without using ion implantation. As related technical literatures, for example, the following patent literatures can be cited.
JP-A-7-130998 JP-A-10-270569

  However, in the above reference, the process of forming a CMOS (Complementary MOS) FET in which an n-channel MOSFET and a p-channel MOSFET are formed on the same substrate is complicated, and PSG and BSG are formed in LDD formation as shown below. Two types of films must be generated and controlled, and P-channel and N-channel LDD variations occur, making it difficult to obtain a stable process.

  That is, in Reference 1, first, as shown in FIG. 7A, p-type impurities or n-type impurities are selectively applied to predetermined regions of the n-type MOSFET region 12 and the p-type MOSFET region 13 on the surface of the semiconductor substrate 11. Ion implantation is performed to form a p-well region 14 and an n-well region 15, respectively. Next, an element isolation insulating film 16 is formed at the boundary between the p-well region 14 and the n-well region 15. Subsequently, a gate oxide film 17 is formed on the surface of the p-well region 14 and the n-well region 15 which will be element forming regions by thermal oxidation. Thereafter, after depositing a polycrystalline silicon film (not shown) on the entire surface, a lithography technique and anisotropic etching are performed, and the gate oxide film 17 and the polysilicon film are patterned to form the gate electrode 18 in the n-type and p-type. Formed in the type MOSFET region. Next, as shown in FIG. 7B, a BSG film 121 is deposited on the entire surface. Next, as shown in FIG. 7C, after forming a resist film 131 covering the n-well region 15 and having an opening on at least the p-well region 14, the resist film 131 is used as a mask. The BSG film 121 is isotropically etched. Next, as shown in FIG. 7D, after removing the resist film 131, a PSG film 141 is deposited on the entire surface. Thereafter, by performing heat treatment, impurities are diffused from the BSG film 121 and the PSG film 141, and p-type low-concentration impurity diffusion regions are respectively formed in shallow regions of the n-well region 15 and the p-well region 14 surface. 142, an n-type low concentration impurity diffusion region 143 is formed. Next, as shown in FIG. 8A, the PSG film 141 is anisotropically etched until the upper surfaces of the gate electrode 18 and the BSG film 121 are exposed, and the PSG sidewall is formed on the sidewall of the gate electrode 18. A film 151 is formed. Thereafter, high concentration phosphorus (P) or arsenic (As) is ion-implanted using the BSG film 121, the gate electrode 18 and the PSG sidewall film 151 as a mask, and an n-type high concentration is implanted into the surface of the p well region 14. A source / drain diffusion layer 152 and an n-type low concentration source / drain diffusion layer 153 are formed. Next, as shown in FIG. 8B, after forming a resist film 161 covering the p well region 14 and the exposed upper surface of the element isolation insulating film 16, the BSG film is formed using the resist film 161 as a mask. 121 is anisotropically etched to form a BSG sidewall film 162 on the sidewall of the gate electrode 18. Thereafter, high-concentration boron or boron fluoride is ion-implanted using the resist film 161, the element isolation insulating film 16, the gate electrode 18 and the BSG sidewall film 162 as a mask, and p is formed on the surface of the n-well region 15. A high concentration source / drain diffusion layer 163 and a low concentration source / drain diffusion layer 164 are formed.

  In Reference 2, first, as shown in FIG. 9A, a BSG film 171 is deposited on the entire surface. Next, as shown in FIG. 9B, a resist film 181 is formed on the BSG film 171 in the p-type MOSFET region 13. Next, as shown in FIG. 9C, anisotropic etching is performed using the resist film 181 as a mask to selectively remove the BSG film 171 in the n-type MOSFET region 13. Next, as shown in FIG. 10A, after the resist film 181 is removed, a PSG film 191 is formed on the entire surface. Next, as shown in FIG. 10B, after forming an insulating film (not shown) on the entire surface, anisotropic etching is performed using the PSG film 191 as a stopper to form a side wall insulating film on the side wall of the gate electrode 18. 201 is formed. Next, as shown in FIG. 10C, after forming a resist film (not shown) in the p-type MOSFET region 13, high concentration phosphorus (P) or arsenic (As) is formed using the resist film as a mask. Ions are implanted to form an n-type high concentration source / drain diffusion layer 211 on the main surface of the semiconductor substrate 11 in the n-type MOSFET region 12. Subsequently, after removing the resist film, a resist film (not shown) is formed in the n-type MOSFET region 12, and high concentration boron (B) or boron fluoride (BF) is formed using the resist film as a mask. Ion implantation is performed to form a p-type high concentration source / drain diffusion layer 212 on the main surface of the semiconductor substrate 11 in the p-type MOSFET region 13. Next, as shown in FIG. 11, the semiconductor substrate 11 in the n-type MOSFET region 12 and the p-type MOSFET region 13 is diffused by performing heat treatment to diffuse impurities from the PSG film 191 and the BSG film 171. An n-type low-concentration source / drain diffusion layer 221 and a p-type low-concentration source / drain diffusion layer 222 are formed in shallow regions of the surface, respectively.

  As described above, in the above reference, it is necessary to form the BSG film and the PSG film, so that the process becomes complicated. Further, since the n-type impurity and the p-type impurity have different diffusion distances in the heat treatment, the depth at which the low-concentration source / drain diffusion layer is formed differs between the n-type MOSFET region and the p-type MOSFET region.

  The present invention has been made in view of such a problem, and an object of the present invention is to easily perform heat treatment using only a PSG film or a BSG film as a thermal diffusion source in a CMOS semiconductor device having an LDD structure. An object of the present invention is to provide a semiconductor device capable of forming a shallow low-concentration source / drain diffusion region and a method for manufacturing the same.

  In view of the above, a semiconductor device according to the present invention is a semiconductor device including a first conductivity type MOSFET region and a second conductivity type MOSFET region, and is formed on a semiconductor substrate and a gate oxide film on the semiconductor substrate. And a first conductivity type sidewall film formed on a sidewall of the gate electrode, and a first conductivity type low film formed below the first conductivity type sidewall film in the first conductivity type MOSFET region. In the first conductivity type high concentration source / drain diffusion layer formed adjacent to the end of the concentration source / drain diffusion layer and the first conductivity type sidewall film, and in the second conductivity type MOSFET region, the first conductivity type A second conductivity type low concentration source / drain diffusion layer formed under the sidewall film and a second conductivity type high concentration source / drain diffusion layer formed adjacent to an end of the first conductivity type sidewall film; Preparation I am characterized in.

  Further, the gate electrode is formed such that the upper surface portion has a longer gate length than the bottom surface portion.

  The semiconductor device further comprises a second conductivity type well region formed in the first conductivity type MOSFET region, and a first conductivity type well region formed in the second conductivity type MOSFET region.

  The semiconductor substrate may be a first conductivity type semiconductor substrate, and may include a second conductivity type well region formed in the first conductivity type MOSFET region.

  The first conductivity type sidewall film is formed of a PSG film or a BSG film.

  A method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device comprising a first conductivity type MOSFET region and a second conductivity type MOSFET region, wherein the first conductivity type MOSFET region and the second conductivity type are provided. A step of selectively forming a gate oxide film and a gate electrode in the MOSFET region, a step of forming a first resist film having an opening in the second conductivity MOSFET region, the first resist film, Using the gate electrode as a mask, a second conductivity type impurity is ion-implanted to form a second conductivity type high concentration impurity diffusion region, and after removing the first resist film, a first conductivity type film is formed on the entire surface. Forming a first conductive type sidewall film on the side walls of the gate insulating film and the gate electrode, performing a heat treatment, and etching the first conductive type film. Forming a first conductivity type low concentration source / drain diffusion layer in the SFET region, and a second conductivity type low concentration source / drain diffusion layer and a second conductivity type high concentration source / drain diffusion layer in the second MOSFET region; Forming a second resist film having an opening in the first conductivity type MOSFET region; and using the second resist film, the gate electrode, and the first conductivity type sidewall film as a mask. And a step of ion-implanting impurities to form a first conductivity type source / drain diffusion layer.

  A method of manufacturing a semiconductor device including a first conductivity type MOSFET region and a second conductivity type MOSFET region, the step of forming an insulating film having an opening on a semiconductor substrate, and the first conductivity type film over the entire surface Depositing the first conductivity type film to etch back the first conductivity type film to form a first conductivity type sidewall film on the side wall of the opening; applying heat treatment; and forming a gate oxide film and the first MOSFET region A step of forming a first conductivity type low concentration source / drain diffusion layer, a first conductivity type high concentration impurity diffusion region of the second MOSFET region, a step of depositing a gate material on the entire surface, and etching back the gate material. Then, a step of burying the gate material between the first conductivity type sidewall films to form a gate electrode, and a first electrode having an opening in the second conductivity type MOSFET region after the insulating film is removed. A step of applying a resist film, and ion implantation of a second conductivity type impurity obliquely using the first resist film, the first conductivity type side wall film, and the gate electrode as a mask. A step of forming a drain diffusion layer and a second conductivity type high-concentration source / drain diffusion layer; and after removing the first resist film, a second resist film having an opening in the first conductivity type MOSFET region is formed A first conductive type impurity is ion-implanted using the second resist film, the first conductive type side wall film, and the gate electrode as a mask to form a first conductive type high concentration source / drain diffusion layer. And a step of performing.

  Further, the method includes a step of forming a second conductivity type well region in the first conductivity type MOSFET region, and a step of forming a first conductivity type well region in the second conductivity type MOSFET region.

  The semiconductor substrate is a first conductivity type semiconductor substrate, and includes a step of forming a second conductivity type well region in the first conductivity type MOSFET region.

  The first conductivity type side wall insulating film is formed of a PSG film or a BSG film.

  In the CMOS type semiconductor device according to the present invention, the low concentration source / drain diffusion region can be formed using only one of the PSG film and the BSG film as a thermal diffusion source. Therefore, the concentration and depth of the low concentration source / drain diffusion region can be easily designed by controlling the impurity concentration and heat treatment time in the PSG film or BSG film.

  Further, since the width of the lower portion of the gate electrode can be formed below the fine limit of the exposure apparatus, the channel length can be miniaturized at the same time.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
Hereinafter, the case of a 0.35 μm process will be specifically described as an example.
First, as shown in FIG. 1A, p-type impurities or n-type impurities are selectively ion-implanted into predetermined regions of the n-type MOSFET region 12 and the p-type MOSFET region 13 on the surface of the semiconductor substrate 11, A p well region 14 and an n well region 15 are formed. It should be noted that even when only one of the p-well region 14 and the n-well region 15 is formed according to the conductivity type of the semiconductor substrate, the same can be implemented. Next, the element isolation insulating film 16 is formed at the boundary between the p-well region 14 and the n-well region 15 using, for example, a LOCOS (Local Oxidation of Silicon) method. Subsequently, a gate oxide film 17 is formed on the surface of the p-well region 14 and the n-well region 15 which will be element forming regions by thermal oxidation. Thereafter, after depositing a polycrystalline silicon film on the entire surface, the gate oxide film and the polysilicon film are patterned by lithography and anisotropic etching to form the gate electrode 18 in the n-type and p-type MOSFET regions. .

Next, as shown in FIG. 1B, a resist film 21 that covers the p-well region 14 and has an opening on at least the n-well region 15 is formed. Thereafter, boron (B) or boron difluoride (BF ₂ ) is ion-implanted using the resist film 21 and the gate electrode 18 as a mask. For example, boron difluoride is ion-implanted under the conditions of an acceleration energy of 35 keV and an ion implantation amount of 2.0 × 10 ¹⁵ atoms / cm ² , thereby forming a p-type on the surface of the n-well region 15 of the p-type MOSFET region 12. A high concentration impurity diffusion region 22 is formed.

  Next, as shown in FIG. 2A, after removing the resist film 21 and depositing a PSG film (not shown) on the entire surface, the PSG film is etched back on the entire surface using the gate electrode 18 as a stopper. A PSG sidewall film 31 is formed on the sidewall of the gate electrode 18.

  Next, as shown in FIG. 2B, heat treatment is performed at a temperature of about 950 ° C. for 25 seconds by, for example, RTA (Rapid Thermal Annealing). By this heat treatment, n-type low-concentration impurities such as phosphorus (P) contained in the PSG sidewall film 31 diffuse into the p-well region 14 and the n-well region 15. As a result, in the n-type MOSFET region 12, an n-type low concentration source / drain diffusion layer 41 having a depth of about 250 mm is formed below the PSG sidewall film 31 in the p-well region 14. In the p-type MOSFET region 13, the n-type low concentration impurity diffused from the PSG sidewall film and the p-type high concentration impurity diffusion region 22 are formed below the PSG sidewall film 31 in the n well region 15. By mixing, a p-type low concentration source / drain diffusion layer 42 having a depth of about 150 mm is formed. In addition, the p-type high-concentration source / drain diffusion layer 43 is formed by thermally diffusing the p-type high-concentration impurity diffusion region 22 except for the portion under the PSG sidewall film 31 in the p-type MOSFET region 13. The concentration distribution of the n-type low-concentration source / drain diffusion layer 41 and the p-type low-concentration source / drain diffusion layer 42 depends on the ion implantation conditions when forming the p-well region 14 and the n-well region 15. It can also be controlled.

Next, as shown in FIG. 2C, a resist film 51 that covers the n-well region 15 and has an opening on at least the p-well region 14 is formed. Thereafter, phosphorus (P) or arsenic (As) is ion-implanted into the n-type MOSFET region 12 using the resist film 51 as a mask. For example, the n-type high-concentration source / drain diffusion layer 52 is formed by ion implantation of arsenic ions under the conditions of an acceleration energy of 100 keV and an ion implantation amount of 5.0 × 10 ¹⁵ atoms / cm ² .

Next, by removing the resist film 51 as shown in FIG. 3, the semiconductor device according to the first embodiment is obtained.
(Second Embodiment)
Hereinafter, the case of a 0.13 μm process will be specifically described as an example.

  First, as shown in FIG. 4A, p-type impurities and n-type impurities are selectively ion-implanted into predetermined regions of the n-type MOSFET region 12 and the p-type MOSFET region 13 on the surface of the semiconductor substrate 11, and p Well region 14 and n-well region 15 are formed. Next, the element isolation insulating film 16 is formed at the boundary between the p-well region 14 and the n-well region 15 by using, for example, the LOCOS method (STI may be used). Further, after an insulating film such as LP-SiN is deposited on the entire surface to a thickness of 200 nm, the insulating film is patterned by performing lithography and anisotropic etching to form the insulating film on the p-well region 14 and the n-well region 15. An insulating film 62 having an opening 61 is formed thereon. At this time, the width of the opening 61 is set to the resolution limit of the exposure apparatus. For example, when i-line is used as the light source type, the width of the opening is 0.35 μm.

  Next, as shown in FIG. 4B, after a PSG film is deposited to a thickness of 0.11 μm on the entire surface, the PSG film is etched back to thereby form a PSG sidewall film made of the PSG film on the sidewall of the insulating film 62. 71 is formed. At this time, the width of the PSG sidewall film 71 is 0.11 μm, which is equal to the deposited film thickness of the PSG film. Accordingly, the width between the PSG sidewall films 71 is reduced to 0.13 μm by reducing the thickness of the PSG film by 0.22 μm.

  Next, as shown in FIG. 4C, a gate oxide film 81 made of a silicon dioxide film is formed to a thickness of 20 nm on the surface of the semiconductor substrate 11 between the PSG sidewall films 71 by thermal oxidation. At the same time, n-type low-concentration impurities such as phosphorus (P) contained in the PSG sidewall film 71 are diffused into the p-well region 14 and the n-well region 15. As a result, an n-type low concentration source / drain diffusion layer 82 having a depth of about 90 mm is formed below the PSG sidewall film 71 on the surface of the p well region 14. Further, an n-type high concentration impurity diffusion region 83 having a depth of about 90 mm is formed below the PSG sidewall film 71 on the surface of the n well region 15. Here, the PSG sidewall film 71 is thick on the sidewall of the insulating film 62 and thin on the opposite side. Further, the supply amount of impurities as a thermal diffusion source in each part of the PSG sidewall film 71 is proportional to the film thickness of the PSG sidewall film 71 in each part. Therefore, the n-type low-concentration source / drain diffusion layer 82 and the n-type high-concentration impurity diffusion region 83 are shallow and lightly separated from the gate oxide film 81 in the portion adjacent to the end of the gate oxide film 81. Accordingly, it is formed with an inclined portion so as to be deep and high in concentration. The concentration distribution of the n-type low-concentration source / drain diffusion layer 82 and the n-type high-concentration impurity diffusion region 83 is controlled by ion implantation conditions when forming the p-well region 14 and the n-well region 15. You can also.

  Next, as shown in FIG. 5A, after forming 0.2 μm of a polysilicon film (not shown) as a gate material on the entire surface, the polysilicon film is etched back until the PSG sidewall film 71 is exposed. Then, a gate electrode 91 in which the polysilicon film is buried in the groove between the PSG sidewall films 71 is formed. In this case, the height of the gate electrode 91 is equal to the film thickness of the insulating film 62. Note that the gate electrode 91 can be formed even by using CMP.

Next, as shown in FIG. 5B, the insulating film 62 is removed by etching with, for example, HOT phosphoric acid using the PSG sidewall film 71 and the gate electrode 91 as a mask. Thereafter, a resist film 101 that covers the p-well region 14 and has an opening on at least the n-well region 15 is formed. Thereafter, boron (B) or boron fluoride (BF) is ion-implanted using the resist film 101, the PSG sidewall film 71 and the gate electrode 91 as a mask. For example, boron is ion-implanted at an incident angle of about 45 degrees with respect to the surface of the semiconductor substrate 11 under conditions of an acceleration energy of 7 keV and an ion implantation amount of 5.0 × 10 ¹⁵ atoms / cm ² . In this case, ions implanted from the thick part of the PSG sidewall film 71 are implanted shallowly into the n-well region 15. Further, ions implanted from the thinnest portion of the PSG sidewall film 71 are implanted deeply into the n-well region 15. Accordingly, the implanted p-type high concentration impurity diffusion region and the n-type high concentration impurity diffusion region 83 have similar concentration distribution shapes. As a result, the implanted p-type high-concentration impurity and the n-type high-concentration impurity diffusion region 83 are mixed under the PSG sidewall film 71 in the p-type MOSFET region 13, so that a p of about 35 mm in depth is obtained. A type low concentration source / drain diffusion layer 102 is formed. At the same time, a p-type high concentration source / drain diffusion layer 103 is formed adjacent to the p-type low concentration source / drain diffusion region 102 on the surface of the n-well region 15.

Next, as shown in FIG. 5C, a resist film 111 that covers the n-well region 15 and has an opening on at least the p-well region 14 is formed. Thereafter, using the resist film 111, the gate electrode 91 and the PSG sidewall film 71 as a mask, for example, arsenic ions are ion-implanted under the conditions of an acceleration energy of 45 keV and an ion implantation amount of 5.0 × 10 ¹⁵ atoms / cm ^2. As a result, an n-type high-concentration source / drain diffusion layer 112 is formed adjacent to the n-type low-concentration source / drain diffusion layer 82 on the surface of the p-well region 14.

  Next, as shown in FIG. 6, by removing the resist film 111, the semiconductor device according to the second embodiment is obtained.

  In addition, although PSG is used in the above embodiment, even if it uses BSG, it can implement similarly.

It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. 1 is a cross-sectional view showing a semiconductor device according to a first embodiment of the present invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. It is sectional drawing which shows the manufacturing method of the conventional semiconductor device.

Explanation of symbols

11 Semiconductor substrate 12 n-type MOSFET region 13 p-type MOSFET region 14 p-well region 15 n-well region 16 element isolation insulating film 17 gate oxide film 18 gate electrode 21 resist film 22 p-type high-concentration impurity diffusion region 31 PSG sidewall film 41 n Type low concentration source / drain diffusion layer 42 p type low concentration source / drain diffusion layer 43 p type high concentration source / drain diffusion layer 51 resist film 52 n type high concentration source / drain diffusion layer 61 opening 62 insulating film 71 PSG sidewall Film 81 gate oxide film 82 n-type low concentration source / drain diffusion layer 83 n-type high concentration impurity diffusion region 91 gate electrode 101 resist film 102 p-type low concentration source / drain diffusion layer 103 p-type high concentration source / drain diffusion layer 111 Resist film 112 n-type high concentration source / drain diffusion layer 121 BSG 131 Resist film 141 PSG film 142 p-type low-concentration impurity diffusion region 143 n-type low-concentration impurity diffusion region 151 PSG sidewall film 152 n-type high-concentration source / drain diffusion layer 153 n-type low-concentration source / drain diffusion layer 161 Resist film 162 BSG sidewall film 163 p-type high concentration source / drain diffusion layer 164 p-type low concentration source / drain diffusion layer 171 BSG film 181 resist film 191 PSG film 201 sidewall insulating film 211 n-type high concentration source / drain diffusion layer 212 p-type high Concentration source / drain diffusion layer 221 n-type low concentration source / drain diffusion layer 222 p-type low concentration source / drain diffusion layer

Claims (10)

A semiconductor device comprising a first conductivity type MOSFET region and a second conductivity type MOSFET region,
A semiconductor substrate;
A gate electrode formed on the semiconductor substrate via a gate oxide film;
A first conductivity type sidewall film formed on the sidewall of the gate electrode;
In the first conductivity type MOSFET region, the first conductivity type low concentration source / drain diffusion layer formed below the first conductivity type sidewall film and the end of the first conductivity type sidewall film are formed adjacent to each other. A first conductivity type high concentration source / drain diffusion layer;
In the second conductivity type MOSFET region, the second conductivity type low-concentration source / drain diffusion layer formed under the first conductivity type sidewall film and the end of the first conductivity type sidewall film are formed adjacent to each other. A semiconductor device comprising: a second conductivity type high concentration source / drain diffusion layer.   2. The semiconductor device according to claim 1, wherein the gate electrode is formed such that the upper surface portion has a longer gate length than the bottom surface portion. A second conductivity type semiconductor layer formed in the first conductivity type MOSFET region;
The semiconductor device according to claim 1, further comprising: a first conductivity type semiconductor layer formed in the second conductivity type MOSFET region.   4. The semiconductor device according to claim 3, wherein at least one of the first conductivity type semiconductor layer and the second conductivity type semiconductor layer is a well region.   3. The semiconductor device according to claim 1, wherein the first conductivity type side wall film is formed of a PSG film or a BSG film. A method for manufacturing a semiconductor device comprising a first conductivity type MOSFET region and a second conductivity type MOSFET region,
Selectively forming a gate oxide film and a gate electrode in the first conductivity type MOSFET region and the second conductivity type MOSFET region;
Forming a first resist film having an opening in the second conductivity type MOSFET region;
Using the first resist film and the gate electrode as a mask, ion-implanting a second conductivity type impurity to form a second conductivity type high concentration impurity diffusion region;
Forming a first conductivity type film over the entire surface after removing the first resist film;
Etching back the first conductivity type film to form a first conductivity type sidewall film on the side walls of the gate insulating film and the gate electrode;
A first conductivity type low concentration source / drain diffusion layer in the first MOSFET region, a second conductivity type low concentration source / drain diffusion layer and a second conductivity type high concentration source / drain diffusion layer in the second MOSFET region are subjected to heat treatment. Forming a step;
Forming a second resist film having an opening in the first conductivity type MOSFET region;
Forming a first conductivity type high concentration source / drain diffusion layer by ion-implanting a first conductivity type impurity using the second resist film, the gate electrode, and the first conductivity type sidewall film as a mask; A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device comprising a first conductivity type MOSFET region and a second conductivity type MOSFET region,
Forming an insulating film having an opening on a semiconductor substrate;
Depositing a first conductivity type film on the entire surface;
Etching back the first conductivity type film to form a first conductivity type sidewall film on the sidewall of the opening;
Performing heat treatment to form a gate oxide film, a first conductivity type low concentration source / drain diffusion layer in the first MOSFET region, and a first conductivity type high concentration impurity diffusion region in the second MOSFET region;
Depositing gate material on the entire surface;
Etching back the gate material to embed the gate material between the first conductivity type sidewall films to form a gate electrode;
Applying a first resist film having an opening in the second conductivity type MOSFET region after removing the insulating film;
Using the first resist film, the first conductivity type side wall film, and the gate electrode as a mask, second conductivity type impurities are ion-implanted obliquely to form a second conductivity type low concentration source / drain diffusion layer and a second conductivity type. Forming a high concentration source / drain diffusion layer;
Applying a second resist film having an opening in the first conductive MOSFET region after removing the first resist film;
Forming a first conductivity type high-concentration source / drain diffusion layer by ion-implanting a first conductivity type impurity using the second resist film, the first conductivity type sidewall film and the gate electrode as a mask; A method for manufacturing a semiconductor device, comprising: Forming a second conductivity type well region in the first conductivity type MOSFET region;
The method of manufacturing a semiconductor device according to claim 6, further comprising: forming a first conductivity type well region in the second conductivity type MOSFET region. The semiconductor substrate is a first conductivity type semiconductor substrate,
The method of manufacturing a semiconductor device according to claim 6, further comprising a step of forming a second conductivity type well region in either the first conductivity type MOSFET region or the second conductivity type MOSFET region. Method.   8. The semiconductor device according to claim 6, wherein the first conductivity type side wall insulating film is formed of a PSG film or a BSG film.