JP3221014B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a pull-up element for preventing floating.

[0002]

2. Description of the Related Art A conventional pull-up element will be described with reference to the drawings.

FIG. 5A shows an N-type M as a pull-up element.
FIG. 3 is a circuit diagram using an OSFET.

[0004] _Vcc is a power supply terminal, B is a wiring to be pulled up, Vd is a power supply line for pulling up, N1 is an N-type MOSFET whose gate input is a power supply voltage _Vcc and is always on. Next, the basic operation will be described. FIG.
(B) is a waveform diagram in which about 5 V of the operating voltage of the integrated circuit is always applied to Vd and _Vcc (straight line α). When the pull-up function is required, assuming that the potential of the wiring B at time t = 0 is 0 V, the potential of B is, as shown by the curve β, its capacitance and N
T = t determined by the capability of the type MOSFET NI
2 is charged to approximately 4.3 V (the threshold voltage VT of the N-type MOSFET is about 0.7 V). However, when the pull-up function is not required, no current flows through the MOSFET N1 when the wiring B is at the “H” level (about 5 V), but when the wiring B is at the “L” level (about 0 V), the current does not flow.
A steady current of the order of 10 to 100 μA flows between the power supply line Vd and the wiring B according to the capability of the SFET N1.

Next, the structure of the pull-up element will be described with reference to a plan view and a sectional view.

FIG. 4A is a plan view showing a pull-up element of a conventional semiconductor device, and FIG. 4B is a sectional view taken along line XX of FIG.
It is a line sectional view.

A P well 14 is formed on the surface of an N-type silicon substrate 15, and an element formation region 7 is defined on the surface of the P well 14 by a field oxide film (not shown). A thickness of about 20 n selectively formed on the surface of the element formation region 7
A gate electrode 9 made of a polysilicon film is formed via an m gate oxide film 16. Reference numerals 7a and 7b denote N-type diffusion layers formed by ion implantation using the gate electrode 9 and the field oxide film as masks. The wiring B is made of an ion-implanted polycrystalline silicon film and is in contact with the N-type diffusion layer 7b. Reference numerals 12 and 13 denote interlayer insulating films, the power supply line Vd is made of an aluminum film, and the diffusion layer 7a is formed through the contact hole 10.
Is in contact with Incidentally, reference numeral 11 denotes an insulating film. As described above, the power supply line Vd
When inserted between the wiring and the wiring B, an area of about 16 μm × μm is required.

[0008]

Since the pull-up element of the conventional semiconductor device is constituted by a MOSFET, it requires not only a large area in a plane and a large volume in three dimensions, but also a circuit as shown in FIG. Is used for a redundant circuit, for example, but in such a circuit, the following problem occurs. The pull-up element P1 has a role of preventing the line L1 from floating when the fuse F1 is cut to use the redundant function. L1 is an input signal of the inverter I2. When L1 is floating, the output of I2 is unstable and a through current is generated. However, when it is not necessary to cut F1, L1 does not float and P1 is not originally required. Conversely, at this time, if the output of the inverter I1 is at a low level, P1
Unnecessary steady-state current is generated via.

[0009]

According to the present invention, one electrode is connected to a constant voltage power supply, the other electrode is connected to a circuit selection line in a selection circuit, and the one electrode and the other electrode are connected. in a semiconductor device having a pull-up device sandwiching an insulating film between the circuit select lines seen contains a fuse,
When the fuse is cut, the insulating film is
Voltage exceeding the certain voltage between one electrode and the other electrode.
Is destroyed by applying a predetermined voltage
The other electrode is short-circuited to the power supply .

[0010]

FIG. 1A is a plan view showing a pull-up element of a semiconductor device according to a first embodiment of the present invention, and FIG.
It is a XX sectional view taken on the line of (a).

Field oxide film 5 of N-type silicon substrate 6
A wiring A made of a polycrystalline silicon film made conductive by doping impurities is formed. An appropriate insulating film (here, two layers of 3 and 4 are shown, but a single layer covering the surface of the wiring A may be provided) is formed on the wiring A by an opening 1 of about 1 μm × 1 μm.
Is formed, and a silicon oxide film O having a thickness of about 9 nm is formed by a CVD method.
X, and a power line V made of an aluminum film is formed thereon.
Then, an insulating film 2 is formed. The insulating film 2 is a power line V
The surface of d may be coated. That is, the pull-up device is a kind of capacity sheet data, voltage exceeding the insulating film OX breakdown voltage (approximately 9V), by applying for example 10V, it is also regarded as a switch S, which becomes conductive. The required area of the switch S is only about 2.5 μm × μm, which may be smaller than the conventional example.

FIG. 2A is a circuit diagram of this embodiment, and FIG.
(B) is a waveform diagram for explaining a basic operation.

Normally, a voltage of about 5 V is applied to the power supply line Vd. In this state, since the switch is off, the potential of the wiring A is 0 V (region T1). When a pull-up is required, a pulse of about 10 V is applied at t = t1, as shown by the curved surface α. Then, when the switch S is turned on, the potential of the wiring A rises to about 10 V as shown by the curve β (region T2). When the pull-up function is not required, that is, in a state before the switch S is turned on, the steady current between the power supply line Vd and the wiring A can be ignored.

FIG. 3 is a sectional view showing a second embodiment.

In this embodiment, the opening 1 of the insulating film is buried with the conductive polycrystalline silicon film 1a and the silicon oxide film OX is formed thereon, so that the thickness of the silicon oxide film OX can be made uniform. It has the advantage of good reproducibility and reliability.

[0016]

As described above, the semiconductor device of the present invention has a pull-up element in which a power supply line and a wiring are connected via an insulating film which causes dielectric breakdown when a predetermined high voltage is applied to both ends. Need only occupy the area of one contact. Therefore, there is an effect of contributing to improvement of the degree of integration of the semiconductor device having the pull-up element. When pull-up is not required, it is DC-insulated,
There is also an effect that a steady current that has conventionally been a problem when the fuse is not cut can be cut off.

[Brief description of the drawings]

FIG. 1 is a plan view (FIG. 1) showing a first embodiment of the present invention;
(A)) and sectional drawing (FIG.1 (b)).

FIG. 2 is a circuit diagram (FIG. 2A) of the first embodiment and a waveform diagram (FIG. 2B) used for explaining the basic operation.

FIG. 3 is a sectional view showing a second embodiment.

FIG. 4 is a plan view (FIG. 4A) and a cross-sectional view (FIG. 4B) showing a conventional example.

FIG. 5 is a circuit diagram (FIG. 5 (a)) of a conventional example and a waveform diagram (5 (b)) used for explaining a basic operation.

FIG. 6 is a circuit diagram showing a usage example of a pull-up element.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Opening 1a Polysilicon film 2,3,4 Insulating film 5 Field oxide film 6 N-type silicon substrate 7 Element formation region 7a, 7b N-type diffusion layer 8 Contact hole 9 Gate electrode 10 Contact hole 11,12,13 Insulating film A , B Wiring that may be pulled up OX Silicon oxide film Vd Power supply line

Continuation of the front page (51) Int.Cl. ⁷ identification code FI H03K 19/0175 H03K 19/00 101K (58) Investigation field (Int.Cl. ⁷ , DB name) H01L 29/86 G11C 11/417 H01L 21 / 822 H01L 27/04 H01L 29/94 H03K 19/0175

Claims (2)

(57) [Claims] 1. One electrode is connected to a power supply of a constant voltage, the other electrode is connected to a circuit selection line in a selection circuit, and an insulating film is interposed between the one electrode and the other electrode. in a semiconductor device having a pull-up element, the circuit selection line viewed contains a fuse, the insulating film, the full
When the fuse is cut, the one electrode and the other
Apply a predetermined voltage exceeding the above-mentioned certain voltage between the electrodes
And the other electrode is connected to the power source.
A semiconductor device having a film thickness to be short-circuited . 2. The semiconductor device according to claim 1, wherein the insulating film of the pull-up element is a silicon oxide film.