JPS6237549B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and particularly to a technique for preventing gate breakdown in an insulated gate type (hereinafter referred to as MOS type) semiconductor device.

In general, breakdown of the gate insulating film of a MOS type semiconductor device is common in MOS transistors that are directly connected to lead terminals of an enclosure, especially MOS transistors that constitute the input system of a circuit. This is because in the input system of the circuit, static electricity from the outside is received by a very small capacitance of one or two transistors, so an abnormally large voltage is applied to the gate. The gate insulating film of a MOS transistor is normally formed of a thin silicon oxide film of about 1000 Å, and its breakdown voltage is about 70V, so the gate insulating film is easily destroyed by excessive voltage. This phenomenon has been a big problem for a long time, and many proposals have been made in the past regarding gate protection to prevent destruction. Examples of well-known prior art include a method of inserting a PN diode into the input terminal, a method of using a MOS transistor with its gate grounded, and a method of using a MOS transistor with a thick gate insulating film. However, when the desired functions of a gate protection device are examined in detail and the conditions to be provided are considered, many of these prior art techniques have insufficient functions.

In general, the basic idea of preventing gate destruction is as follows:
In the process of charging charges flowing into the chip from the external leads, the charges are dispersed within the chip before the voltage rises to the gate breakdown voltage. Therefore, a sufficiently effective gate protection device must satisfy the following conditions.

(1) The threshold voltage for discharging charged charges must be sufficiently lower than the gate breakdown voltage, and the lower the voltage, the better.

(2) However, in order to avoid interfering with normal operation, the threshold voltage for discharging the charged charge must be sufficiently higher than the operating voltage applied to its terminals under normal usage conditions.

(3) After the voltage exceeds the threshold voltage due to charging, discharging must occur as quickly as possible.

(4) The protective device itself must not be destroyed.

Conventionally devised protective devices are insufficiently effective against either of these conditions.

For example, FIG. 1 is an equivalent circuit diagram of a conventional technique using a PN diode with a diffusion layer as a protection device. In the case of an N-channel, a wiring 2 introduced from a bonding pad 1 is guided to the gate of an internal transistor 6 via a diode 5 composed of an N-type impurity diffusion layer 3 and a P-type substrate 4. In this structure, by setting the reverse breakdown voltage of the P-N diode to be lower than the gate breakdown voltage of the transistor 6, the P-N junction breaks down before the gate of the transistor is destroyed by high voltage, and the charge is transferred to the diffusion layer 3. and discharges it to the substrate 4. But with this method,
Generally, the withstand voltage of the P-N junction is as high as 40 to 50V, so there is only a small margin for the gate breakdown voltage of 70V, and the condition (1) above is not met. In other words, if the charging is instantaneous and the breakdown of the P-N junction cannot be followed, the voltage will instantaneously rise above the junction breakdown voltage and there will be no protection function, but in this example In this case, the margin against such excessive voltage is extremely small.

FIG. 2 shows an equivalent circuit diagram of a structure using a MOS transistor as a protection device as another example of the prior art. In this case, a protective MOS transistor is added so that the diffusion layer 3 of the input signal line serves as a drain. The gate 7 and source 8 of the protection MOS transistor are normally connected to ground potential. With this structure, the breakdown voltage of the drain 3 becomes lower than that of a simple PN junction due to the electric field effect generated by the gate insulating film 9 and the gate electrode 7. for example,
By setting the thickness of the gate insulating film 9 to 1000 Å and the comparative resistance of the substrate to 4π cm, the breakdown voltage of the diffusion layer 3 is set to 30 V.
It can be done to a certain extent. Therefore, there is more margin for the gate breakdown voltage of the transistor 6 to be protected than in the example shown in FIG. 1, and a more favorable effect can be obtained. However, usually MOS as a gate protection device
Since the transistor is made with the same structure as the MOS transistor used inside, there is a drawback that the gate insulator 9 of the protection transistor itself is destroyed.

FIG. 3 shows yet another example in which a MOS transistor having a thick gate insulator 9 is used as a protection transistor instead of a MOS transistor having the same structure as the internal element. In this case, the gate electrode 7
is used by connecting it to the potential of the input signal line 2. In this example, the charged charges are discharged as on-current of a MOS transistor with a thick gate. Therefore, the discharge threshold voltage is the threshold voltage of the protection MOS transistor.

This structure works well as a protector. In other words, it is an empirical fact that gate breakdown generally occurs with a higher probability when a semiconductor device is handled before it is mounted than after it is mounted. is in a floating state. In N-channel devices that are normally used with a substrate biased, the threshold voltage of the transistor is low in the absence of substrate bias, and even if a thick insulator is used as the gate insulator 9, the substrate bias remains unchanged. It is easy to set the threshold voltage to about 10V. Therefore, the advantages of this structure over others are that the discharge threshold voltage is sufficiently low, and because the gate insulator of the protection device is thick, there is no problem of the gate of the protection device being destroyed as shown in Figure 2. It is. Under normal usage conditions with substrate bias,
The threshold voltage of this transistor is 80V or higher and has no effect on normal operation.

In this way, this structure satisfies the conditions (1) to (3) above and is considered to be the most effective at present. However, the drawback of this structure is that the principle of discharging the charge as the on-current of the transistor is Despite this, the conductance of the transistor is small because the gate insulating film is thick, so the discharge speed is slow and cannot follow instantaneous pulses. If this drawback is attempted to be avoided by reducing the film thickness, the threshold voltage will drop, making it impossible to maintain the threshold voltage sufficiently high under normal usage conditions.

SUMMARY OF THE INVENTION An object of the present invention is to provide a protection device that maintains a high threshold voltage under normal use and has high conductivity when performing its protection function.

A semiconductor device according to the present invention is characterized in that a MOS transistor having a region with a relatively high threshold voltage and a region with a relatively large current capacity in the same channel is used as a protection circuit.

An embodiment of the present invention will be described in detail below with reference to FIGS. 4A to 4C.

An input signal from the outside is introduced into the diffusion layer 3 via the metal wiring 2 connected to the bonding pad 1.
It is led to the gate of transistor 6 of the input circuit.
The protection device is a MOS transistor in which a part of the diffusion layer 3, which is an input signal line, is used as the drain, the first gate electrode 10 and the second gate electrode 11 are used as the gate electrodes, and the added diffusion layer 8 is used as the source. The gate insulator 12 under the first gate 10 is constructed relatively thin and constitutes a channel region 13 with a large current capacity. 2nd gate 11
The gate insulator 14 underneath is thick and forms a channel region 15 with a relatively high threshold voltage.
The first electrode 10 and the second electrode 11 are electrically connected to each other through a contact hole 16, and the wiring 2
is connected to the input terminal by Diffusion layer 8 is connected to ground potential as a source. As an example, if this structure is constructed using the currently common silicon gate technology, the first gate 10 can be constructed of polycrystalline silicon and the second gate 11 can be constructed of aluminum. In addition, a relatively thin insulator 13 is
The thickness of the thick insulator 14 can be set to about 4000 Å, and the thickness of the thick insulator 14 to about 8000 Å. By adopting such a structure, all the conditions required for a protective device can be satisfied. In other words, it is easy to set the threshold voltage of the second gate 11 to about 10 V in a state where no substrate bias is applied before mounting where gate breakdown is likely to occur, and it can be set sufficiently small compared to the gate breakdown voltage of 60 to 70 V. The conditions in section can be satisfied. For normal operation, a substrate bias is applied and the threshold voltage of the second gate 6 is raised and used, so it is easy to make the threshold voltage sufficiently high compared to the operating voltage, (2)
The conditions in section 2 can also be satisfied. In the present invention, the threshold voltage for starting discharge is determined in the area of 4 channels 15, and the channel 13 portion is
Since the capacitor is made thin and the current capacity is set large, once the gate voltage exceeds the threshold voltage, the charge is quickly discharged and the condition (2) is satisfied.

Furthermore, in the present invention, the gates 10 and 1 are
When the potential of 1 increases, the gate insulators 12 and 1
4 is made thicker than the gate insulator of a normal MOS transistor, the gate withstand voltage of the protection device itself can be made sufficiently high, and the condition (4) is also satisfied.

FIGS. 5 and 6 show another embodiment of the present invention for reducing the area occupied by the protection device. Needless to say, this goal can be achieved. It is also clear that the present invention can be applied to both N-channel and P-channel semiconductor devices.

[Brief explanation of the drawing]

1 to 3 are diagrams each showing an equivalent circuit of a semiconductor device according to the prior art, and FIGS. 4A to 4C are a plan view, a sectional view, and an equivalent circuit, respectively, showing a semiconductor device according to an embodiment of the present invention. Figure, 5th
FIG. 6 is a sectional view showing another embodiment of the present invention. Codes in the diagram: 1... Bonding pad, 2, 3
...diffusion layer, 5...P-N junction, 6...MOS transistor, 10...first gate, 11...second
Gate.

Claims (1)

[Claims] 1 A transistor that prevents gate breakdown of an insulated gate transistor connected to an input terminal, with one end connected to the input terminal and the other end connected to a reference potential, with a thick gate oxide film and a thin gate on the channel. a first gate electrode on the thin gate oxide film; a second gate electrode on the thick gate oxide film and the first gate electrode; A semiconductor device comprising: a protection transistor connected to the first gate electrode and also connected to the input terminal.