JPH0744256B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a MOS type capacitance element.

[Conventional technology]

Conventionally, as shown in FIG. 5, a semiconductor integrated circuit of this type has an n-type well 2 provided on the main surface of a p-type silicon substrate 1.
And p ⁻ provided in the channel formation region on the surface of the n-type well 2.
Type region 3, gate insulating film 4 provided on the surface including n-type well 2, and gate electrode 5 provided on gate insulating film 4.
And ap ⁺ type diffusion region 6 provided on the surface of the n type well 2 in alignment with the gate electrode 5, and an n ⁺ type diffusion region provided on the surface of the n type well 2 adjacent to the p ⁺ type diffusion region 6. 7 and gate electrode 5
To one of the p ⁺ -type diffusion region 6 and the wiring 9 connected to the gate electrode 5 through the opening, and the interlayer insulating film 8 provided on the surface including the contact opening formed in the interlayer insulating film 8. The wiring 10 and the wiring 10 connected to each other are provided, and the wiring 11 connected to both the p ⁺ type diffusion region 6 and the n ⁺ type diffusion region 7 on the other side, respectively.
11 is connected to form a MOS type capacitive element.

As shown in FIG. 6, the CV characteristic of the capacitance portion constituted by the gate electrode 5 and the p ⁻ type region facing each other with the gate insulating film 4 interposed therebetween is shown in FIG. The capacitance C at that time is the capacitance formed only by the gate insulating film.
Although it becomes C _OX , a depletion layer is formed on the surface of the p ⁻ type region 3 near OV, and the capacitance C is It will be smaller. The n-type inversion layer is formed as the voltage of the gate electrode is gradually increased. However, since the n ⁺ -type diffusion region 7 is not in contact with the channel region, the n-type inversion layer and p-type
The depletion layer between the mold regions 3 contributes to the CV characteristics and stays at a constant value as shown in FIG.

Further, since the n ⁺ type diffusion region 7 shown in FIG. 5 is not in contact with the channel region, an extra resistance component or capacitance component is involved in the MOS capacitance shown in the conventional example.

FIG. 7 is a cross-sectional view of a plane perpendicular to the channel length direction of the capacitor portion of FIG.

As shown in the figure, when a positive voltage is applied to the n-type well 2 and the n-type inversion layer 12 is formed on the surface of the channel region, the n-type inversion layer 12 partitions the element region. The parallel connection is made to the connection with the n ⁺ type diffusion region 7 through the channel stopper 14 provided on the lower surface of the field insulating film 13, and mainly the resistance component of the channel stopper 14 and the n type well 2 and the n type inversion. Between layer 12 and p ^- type region 3 and P ^- type region 3
As a result, the capacitance component between the n-type well 2 and the n-type well 2 is involved, and an extra element is added in addition to the pure MOS capacitance.

[Problems to be Solved by the Invention]

In the conventional semiconductor integrated circuit described above, since the n ⁺ type diffusion region 7 is not in contact with the channel region, the CV characteristic of the MOS capacitor changes stepwise due to the potential difference between the two poles,
There is a drawback that a resistance component is interposed between the n ⁺ type diffusion regions 7 and not only a pure MOS capacitance but also a circuit defect occurs.

[Means for Solving the Problems]

The semiconductor integrated circuit according to the present invention includes a well of opposite conductivity type provided on one main surface of a semiconductor substrate of one conductivity type, a gate insulating film formed on a surface including the well, and a gate insulating film on the well. The first electrode of the first conductivity type diffusion region having a low impurity concentration formed in the channel region on the surface of the well immediately below the gate electrode, and the first electrode of the first conductivity type diffusion region. A high impurity concentration second conductivity type diffusion region formed by connection, a high impurity concentration reverse conductivity type diffusion region formed in contact with the other side surface of the first conductivity type diffusion region, and An interlayer insulating film formed on the surface including the gate electrode, and a wiring electrically connecting the second one conductivity type diffusion region and the opposite conductivity type diffusion region through a contact hole formed in the interlayer insulating film. MOS type capacitor configured with Having.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention.

As shown in FIG. 1, an n-type well 2 is selectively provided on the main surface of a p-type silicon substrate 1, and a p-type impurity is selectively ion-implanted into a channel forming region on the surface of the n-type well 2 to form a p-type impurity. ^{-Provide the} mold region 3. Next, a gate insulating film 4 is provided on the surface including the n-type well 2, a polycrystalline silicon layer is deposited on the gate insulating film 4, and this is selectively etched to form a gate electrode 5. Next, an impurity is ion-implanted into the n-type well 2 so as to be aligned with the gate electrode 5 to form a P ⁺ -type diffusion region 6. Similarly, an impurity is ion-implanted so as to be aligned with the gate electrode 5 and the p ⁻ -type region 3 is formed. An n ⁺ type diffusion region 7 adjacent to is formed selectively. Next, an interlayer insulating film 8 is deposited on the surface including the gate electrode 5 to form an opening for contact. Next, a wiring 9 connected to the gate electrode 5 through the opening, a wiring 10 connected to the p ⁺ type diffusion region 6 and a wiring 11 connected to the n ⁺ type diffusion region 7 are provided, respectively, and the wiring 10 and the wiring 10 are provided. Connect 11 and MO
Form an S-type capacitor.

FIG. 2 is a CV characteristic diagram of the first embodiment of the present invention.

As shown in FIG. 2, the capacitance C when a negative voltage is applied to the gate electrode 5 with respect to the n-type well 2 becomes the capacitance C _OX obtained only by the gate insulating film, and the channel surface extends from near OV to the positive voltage side. A depletion layer is formed in the However, when the voltage is further increased, an n-type inversion layer is formed, and the capacitance value returns to C _OX again because the n ⁺ -type diffusion region 7 is adjacent to the channel region. Therefore, as can be seen by comparing with the C-V characteristic of the conventional MOS capacitor of FIG. 6, the C-V characteristic of this embodiment has less voltage dependence.
Further, since the n ⁺ type region 4 is formed adjacent to the channel, it is in contact with the n type inversion layer that can be formed when the voltage is increased, so that the resistance component of the well region different from the conventional MOS capacitor element can be excluded.

FIG. 3 is an equivalent circuit diagram showing the second embodiment of the present invention.

Regarding the connection of the MOS type capacitance element shown in FIG. 1, the first MOS
The second MOS type capacitance element 22 has a reverse polarity to the capacitance type capacitance element 21 and is connected in parallel. MOS type capacitor 21,
22 is composed of substantially the same shape and material.

FIG. 4 is a CV characteristic diagram of the second embodiment of the present invention.

As shown in the figure, the C-V characteristic of the first MOS capacitor 23
The C-V characteristic of the second MOS type capacitance element is symmetrical about the OV point, and the C-V characteristic of the synthesized capacitance element is
25 is the sum of the characteristics of the first and second MOS capacitance elements 21 and 22, and as you can see from this characteristic, the size of the dent near OV is
Although it is the same as the case of individual capacitors, the capacitance value of the flat part is doubled due to the characteristics of the combined capacitive element,
MOS whose voltage fluctuation ratio is reduced and voltage dependency is small
A type capacitive element is obtained.

〔The invention's effect〕

As described above, according to the present invention, by providing both the p ⁺ and n ⁺ regions adjacent to the channel region of the MOS-type capacitance element, the voltage dependency of the capacitance value can be significantly reduced compared to the conventional case, and the extra resistance can be reduced. Since the components can be eliminated, there is an effect that it can be used in a high-precision circuit.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a first embodiment of the present invention, FIG. 2 is a CV characteristic diagram of the first embodiment of the present invention,
FIG. 3 is an equivalent circuit diagram showing the second embodiment of the present invention, and FIG.
FIG. 5 is a CV characteristic diagram of the second embodiment of the present invention, FIG. 5 is a sectional view of a semiconductor chip showing an example of a conventional semiconductor integrated circuit, and FIG. 6 is a CV characteristic of a conventional semiconductor integrated circuit. FIG. 7 and FIG. 7 are cross-sectional views of a plane perpendicular to the channel length direction of the capacitor portion of FIG. 1 ...... p-type silicon substrate, 2 ...... n-type well, 3 ...... p ^-
Mold region, 4 ... Gate insulating film, 5 ... Gate electrode, 6 ...
… P ⁺ type diffusion region, 7 …… n ⁺ type diffusion region, 8 …… Interlayer insulating film, 9,10,11 …… wiring, 12 …… n type inversion layer, 13 …… Field insulating film, 14 …… Channel stopper, 21,22 …… MOS
-Type capacitive element, 23 ... C-V characteristic of first MOS-type capacitive element, 24 ... C-V characteristic of second MOS-type capacitive element, 25 ...
C-V characteristics of the synthesized capacitive element.

Claims (1)

[Claims] 1. A well of opposite conductivity type provided on one main surface of a semiconductor substrate of one conductivity type, a gate insulating film formed on a surface including the well, and a gate insulating film formed on the well. A gate electrode, a first impurity diffusion region of a low impurity concentration formed in a channel region on the surface of the well directly below the gate electrode, and one side surface of the diffusion region of the first conductivity. The formed high impurity concentration second conductivity type diffusion region, the high impurity concentration reverse conductivity type diffusion region formed in contact with the other side surface of the first conductivity type diffusion region, and the gate electrode An interlayer insulating film formed on the surface including the insulating layer, and a wiring electrically connecting the second one conductivity type diffusion region and the opposite conductivity type diffusion region through a contact hole formed in the interlayer insulating film. Must have a MOS type capacitive element configured The semiconductor integrated circuit according to claim.