JP4512570B2 - Liquid crystal display device and manufacturing method thereof - Google Patents

Description

  The present invention generally relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a MOS (metal-oxide-semiconductor) capacity and a method for manufacturing the same. The present invention further relates to such a MOS capacitor, a semiconductor device having such a MOS capacitor, and a method of manufacturing the same.

  Conventionally, liquid crystal display devices have been widely used as portable information processing devices such as so-called notebook personal computers as small information display devices with low power consumption.

  On the other hand, the use of the liquid crystal display device is not limited to such a portable information processing device. Today, even a so-called desktop information processing device replaces a conventional CRT display device. Furthermore, the liquid crystal display device is also promising as a so-called high-definition (HDTV) display device, and its application to a projection type HDTV display device has been particularly studied.

  In the case of these high-performance large-area liquid crystal display devices, using the conventional simple matrix driving method cannot satisfy the required specifications in terms of response speed, contrast ratio, and color purity. Therefore, an active matrix driving method is used in which each pixel is driven by a corresponding thin film transistor (TFT). In an active matrix liquid crystal display device, an amorphous silicon liquid crystal display device using amorphous silicon in an active region of a TFT has been used conventionally. However, amorphous silicon has a low electron mobility, and the high performance liquid crystal display device is the same. The required specifications cannot be satisfied. Therefore, it is necessary to use a polysilicon TFT as the TFT in these high-performance liquid crystal display devices.

  In general, in an active matrix liquid crystal display device, a capacitor is used corresponding to each TFT in order to hold a driving voltage applied to a liquid crystal layer. Such a capacitor may be formed by a pair of metal electrodes and a dielectric film interposed between the pair of metal electrodes as in a normal capacitor, but the capacitor cooperating with the miniaturized polysilicon TFT is formed by a so-called MOS structure. Is advantageous.

  FIG. 1 shows a schematic configuration of a conventional active matrix drive type liquid crystal display device.

  Referring to FIG. 1, the liquid crystal display device includes a TFT glass substrate 1A carrying a number of TFTs and a transparent pixel electrode cooperating therewith, and a counter glass substrate 1B formed on the TFT substrate 1A. A liquid crystal layer 1 is sealed between 1A and 1B by a seal member 1C. In the illustrated liquid crystal display device, the transparent pixel electrode is selectively driven through the corresponding TFT, whereby the orientation of the liquid crystal molecules is selectively selected in the liquid crystal layer corresponding to the selected pixel electrode. Change. Further, on the outside of the glass substrates 1A and 1B, although not shown, polarizing plates are arranged in a crossed Nicols state. Although not shown, a molecular alignment film is formed inside the glass substrates 1A and 1B so as to be in contact with the liquid crystal layer 1 to regulate the alignment direction of the liquid crystal molecules.

  FIG. 2 shows an enlarged part of the TFT glass substrate 1A.

  Referring to FIG. 2, on the glass substrate 1A, a large number of pad electrodes 13A supplied with a scanning signal and a large number of scanning electrodes 13 extending therefrom, and a large number of pad electrodes 12A supplied with a video signal and the following are formed. A number of extending signal electrodes 12 are formed such that the extending direction of the scanning electrode 13 and the extending direction of the signal electrode 12 are substantially orthogonal to each other, and the intersection of the scanning electrode 13 and the signal electrode 12 The TFT 11 is formed. Further, on the substrate 1A, transparent pixel electrodes 14 are formed corresponding to the respective TFTs 11. Each TFT 11 is selected by a scanning signal on the corresponding scanning electrode 13, and on the corresponding signal electrode 12. The cooperating transparent pixel electrode 14 is driven by the video signal.

  FIG. 3 shows a liquid crystal cell driving circuit configuration for one pixel of the liquid crystal display device of FIG.

  Referring to FIG. 3, a plurality of liquid crystal cells 15 corresponding to a plurality of pixels are defined in the liquid crystal layer 1 of FIG. 1, and the TFT substrate corresponding to the glass substrate 1A of FIG. The TFTs 11 are formed in a matrix corresponding to the liquid crystal cells 15. On the TFT substrate 1A, signal lines 12 for supplying video signals to the TFTs 11 extend substantially in parallel to each other in the column direction, and gate control lines (scanning electrodes) 13 for controlling the TFTs 11 are mutually connected. It extends in the row direction substantially in parallel. In the illustrated example, the TFT 11 includes a pair of TFTs 11 </ b> A and 11 </ b> B connected in series, and drives the corresponding liquid crystal cell 15 via the pixel electrode 14. Further, a capacitor 16 is connected to the TFT 11 in parallel with the liquid crystal cell 15. The capacitor 16 forms a storage capacitance that holds a driving voltage applied to the liquid crystal cell 15. At this time, the capacitor 16 is connected between the pixel electrode 14 and the capacitor line 17.

  As described above, the storage capacitor 16 may have a structure in which a dielectric film is held between a pair of metal electrode patterns. However, in the liquid crystal display device of the active matrix driving method, it is formed in the form of a MOS capacitor. Is advantageous.

  FIG. 4 shows a circuit configuration of a liquid crystal display device having such a conventional MOS capacitor.

  Referring to FIG. 4, the liquid crystal cell covers a glass substrate 10A corresponding to the TFT substrate 1A, a polysilicon pattern 10B formed on the glass substrate 10A, and the polysilicon pattern 10B on the glass substrate 10A. The TFT 11 includes n + type diffusion regions 10a, 10b and 10c formed in the polysilicon pattern 10B, and the diffusion regions 10a and 10b on the oxide film 10C. A gate electrode 11a made of Al or polysilicon formed between the gate electrode 11a and a similar gate electrode 11b made of Al or polysilicon formed on the oxide film 10C and between the diffusion regions 10b and 10c. Become. However, the gate electrode 11a corresponds to the TFT 11A, and the gate electrode 11b corresponds to the TFT 11B. The oxide film 10C forms a gate insulating film under the gate electrodes 11a and 11b. The signal line 12 is connected to the diffusion region 10a, and the gate control line 13 is connected to the gate electrodes 11a and 11b.

  In the configuration of FIG. 4, the diffusion region 11c further extends rightward in the drawing to form an n + type diffusion region 10d. Further, on the oxide film 10C, an electrode 11c made of Al or polysilicon similar to the gate electrodes 11a and 11b is formed as a capacitor electrode corresponding to the diffusion region 10d. The electrode 11c and the diffusion region 10d constitute a capacitor electrode of the capacitor 16.

  In the liquid crystal display device having such a configuration, the TFTs 11A and 11B are turned on by the selection signal on the gate bus line 13, and the capacitor 16 is charged through the diffusion region 10d by the video signal on the signal line 12. . As a result, the potential of the pixel electrode 14 connected to the diffusion region 10c and the diffusion region 10d is held at a predetermined drive potential until the next selection signal comes in.

  On the other hand, in such a conventional liquid crystal display device, the diffusion regions 10a, 10b and 10c can be formed in a self-alignment manner using the gate electrodes 11a and 11b as a mask, but the diffusion region 10d cannot be formed in a self-alignment process. . That is, a mask is used separately to form the diffusion region 10d, and the ion implantation process needs to be performed separately from the diffusion regions 10a to 10c.

  However, when another mask process and another ion implantation process are used to form the diffusion region 10d in this way, the number of processes is greatly increased, and there is a defect such as a threshold fluctuation due to mask displacement. May increase the probability of. Further, in the configuration of FIG. 2, it is conceivable that the diffusion regions 10a to 10c are formed in the same mask process simultaneously with the diffusion region 10d instead of the self-alignment process. In such a process, the formation process of the oxide film 10C is considered. Is performed after the ion implantation step, the surface of the polysilicon pattern 10B is easily contaminated by an impurity element. In the case of manufacturing a semiconductor integrated circuit, such an impurity element is removed by cleaning. However, in the case of a liquid crystal display device using a glass substrate, thorough cleaning cannot be performed. When contamination occurs, the impurity element tends to remain on the polysilicon pattern 10B.

  On the other hand, FIG. 5 shows a configuration of another conventional liquid crystal display device that solves the above-described problems of the liquid crystal display device of FIG. However, in FIG. 5, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

  Referring to FIG. 5, in the illustrated liquid crystal display device, in addition to the n + type diffusion regions 10a to 10c constituting the TFTs 11A and 11B, a similar n + type diffusion region 10e is included in the polysilicon pattern 10B. The electrodes 11a and 11b and the capacitor electrode 11c are used as a mask to form a self-alignment process. Therefore, the problem of increasing the number of manufacturing processes and the problem of contamination of the polysilicon pattern 10B due to impurity elements are avoided. In the configuration of FIG. 3, a predetermined voltage is applied to the electrode 11c via the capacitance line 17, and the surface of the polysilicon pattern 10B is in the intrinsic or lightly doped region 10f between the diffusion regions 10c and 10e. Inducing the accumulation layer. The region 10f has the same impurity concentration as the channel region formed between the diffusion regions 10a and 10b or between the diffusion regions 10c and 10d in the polysilicon pattern 10B.

  The configuration of FIG. 5 can avoid the problems of the configuration of FIG. 4 as described above, but a separate power source is required to drive the capacitor line 17 in order to induce a surface accumulation layer in the region 10f. Therefore, the drive circuit in the liquid crystal display device becomes complicated, and the problem that the manufacturing cost increases is unavoidable. Further, as can be seen from the circuit diagram of FIG. 3, the capacitor line 17 to which such a high voltage is applied intersects the signal line 12 on the TFT substrate 10 </ b> A, but between the capacitor line 17 and the signal line 12. Since only a thin interlayer insulating film intervenes in the layer, there is a possibility that leakage current or dielectric breakdown may occur. The voltage applied to the capacitor line 17 is much higher than the voltage used in a normal semiconductor integrated circuit. In addition, since such a high voltage is continuously applied to the capacitor line 17, the gate oxide film 10C is more likely to deteriorate than the gate oxide film of a normal MOS transistor. For this reason, the capacitor 16 having the configuration of FIG. 5 has a problem in terms of reliability.

  Further, in the configuration of FIG. 5, as a high voltage is applied to the capacitor line 17, a domain is easily formed in the liquid crystal cell between the capacitor line and another wiring or TFT. Further, in order to avoid display disturbance due to the formation of such a domain, it is necessary to form a light shielding mask having a substantial width along the capacitance line. If such a light shielding mask having a wide width is formed, a liquid crystal display device is formed. The aperture ratio will be reduced.

  Accordingly, it is a general object of the present invention to provide a novel and useful MOS capacitor element, liquid crystal display device, semiconductor device, and manufacturing method thereof that solve the above-described problems.

  SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a new and useful MOS capacitor element that solves the above problems, a liquid crystal display device having such a MOS capacitor element, and a method for manufacturing the same.

  Another object of the present invention is to provide a MOS capacitor element that has a simple configuration and is easy to manufacture, a liquid crystal display device having such a MOS capacitor element, and a method for manufacturing the same.

The present invention is the above-mentioned problems, is sealed between a first glass substrate, a second glass substrate facing the first glass substrate, and the first glass substrate and the second glass substrate A liquid crystal layer, a signal electrode extending on the first glass substrate, a scanning electrode extending on the first glass substrate, and a common potential line extending on the first glass substrate; In a liquid crystal display device comprising: a thin film transistor formed at an intersection of the signal electrode line and the scan electrode; a pixel electrode electrically connected to the thin film transistor; and a storage capacitor connected in parallel to the pixel electrode. , the thin film transistor is formed in the semiconductor layer formed on the first glass substrate, the storage capacitance, and the semiconductor insulation formed on layer film, on the insulating film, the semiconductor layer To the flat pattern A capacitor electrode which is Marete formed, of the semiconductor layer, the exposed portion exposed from the capacitor electrode, a first diffusion region formed in one side of the capacitor electrode, the other of said capacitor electrode more becomes second diffusion regions formed in a side of said first diffusion region to the first conductivity type and said second diffusion region is doped to a second, opposite conductivity type, The first diffusion region and the second diffusion region are aligned with the edge of the capacitor electrode and are formed adjacent to each other at two locations, according to the liquid crystal display device, or
In the method of manufacturing a liquid crystal display device having a MOS type capacitive element, the MOS type capacitive element includes a step of forming a semiconductor layer on a glass substrate, a step of forming an insulating film on the semiconductor layer , and the insulating film. Forming a capacitor electrode included in a planar pattern of the semiconductor layer ; and using the capacitor electrode as a mask, an impurity element of a first conductivity type in the semiconductor layer on one side of the capacitor electrode And introducing a second, reverse conductivity type impurity element into the semiconductor layer on the other side of the capacitor electrode, using the capacitor electrode as a mask, and forming a first diffusion region . Forming the first diffusion region, and the first diffusion region and the second diffusion region are aligned with the edge of the capacitor electrode and adjacent to each other at two locations. Has been This problem is solved by the method for manufacturing a liquid crystal display device.
[Action]
FIG. 6A shows the principle of the MOS capacitor according to the present invention, and FIG. 6B shows an equivalent circuit diagram thereof. However, the same reference numerals are given to the portions corresponding to the portions described above in the drawing, and the description will be omitted.

  Referring to FIG. 6A, in the MOS type capacitive element, an n + type diffusion region 10h corresponding to one edge of the capacitor electrode 11c is formed in the semiconductor layer 10B corresponding to the polysilicon pattern 10B. A p + type diffusion region 10i is formed corresponding to the other edge of the gate electrode 11c.

  FIG. 6B shows an equivalent circuit diagram of the MOS capacitor of FIG.

  Referring to FIG. 6B, the MOS type capacitive element includes a capacitance Co corresponding to the capacitance of the oxide film 10C and connected to the gate electrode 11c, a diode Dn corresponding to the diffusion regions 10h and 10i, and Dp and junction capacitances Cjn and Cjp corresponding to the diffusion regions 10h and 10i are included.

  FIGS. 7A and 7B show capacitance-voltage characteristics (C-Vg characteristics) when a positive or negative DC bias ± Vg is applied to the MOS capacitive element 10 of FIGS. 6A and 6B. Indicates. However, FIG. 7A shows a configuration for such capacitance measurement, and the capacitance value of the MOS capacitor element is obtained by measuring the impedance Z between the output terminals OUT. FIG. 7B shows the obtained capacitance-voltage characteristics.

  First, referring to FIG. 7A, the capacitor electrode 11c is used as a first terminal in the MOS capacitor 10 of FIGS. 6A and 6B, and the n + type diffusion region 10h and the p + type diffusion region are used. 10i is connected in common to form a complementary MOS capacitive element 10 serving as a second terminal, and a small alternating current signal of 100 kHz or higher is applied to the complementary MOS capacitive element 10 from the alternating current signal source. Simultaneously with the supply, a positive or negative DC bias ± Vg was applied between the first and second terminals by the DC power supply 22 and the impedance Z was measured at the output terminal OUT to determine the value of the capacitance C. .

  FIG. 7B shows the capacitance of the MOS capacitor 10 obtained from such a test as a function of the DC bias voltage ± Vg. In FIG. 7B, the vertical axis represents the normalized capacitance value C / Co obtained by normalizing the obtained capacitance value C with the capacitance value Co of the oxide film 10C, and the horizontal axis represents the DC bias voltage ± Vg. Show.

  Referring to the C-Vg characteristic of FIG. 7B, the broken line does not take the complementary configuration shown in FIG. 7A in the MOS type capacitance element 10, but between the capacitor electrode 11c and the n + type diffusion region 10h. And the alternate long and short dash line shows the case where the capacitance between the capacitor electrode 11c and the p + type diffusion region 10i is obtained, but the capacitor indicated by the broken line The capacitance between the electrode 11c and the n + type diffusion region 10h is the n + type diffusion region 10h in the region immediately below the electrode 11c on the surface of the semiconductor layer 10B while a positive voltage + Vg is applied to the capacitor electrode 11c. In this case, when the negative voltage −Vg is applied to the capacitor electrode 11c, the electron storage layer is continuously formed. Such an electron storage layer is not formed, and the capacitance value becomes very small. Similarly, the capacitance between the capacitor electrode 11c and the p + type diffusion region 10i indicated by the alternate long and short dash line is the surface of the electrode 11c on the surface of the semiconductor layer 10B while a negative voltage −Vg is applied to the capacitor electrode 11c. Since a hole accumulation layer is formed continuously in the region immediately below the p + type diffusion region 10i, it has a value comparable to the capacitance value Co, whereas a positive voltage + Vg is applied to the capacitor electrode 11c. In some cases, such a hole accumulation layer is not formed, and the capacitance value becomes very small. If these complementary configurations are not employed, the C-Vg characteristic depends on the frequency as shown in FIG. 7B. In FIG. 7B, “low frequency CV characteristics” indicates C-Vg characteristics at low frequencies, while “high frequency CV characteristics” indicates C-Vg at high frequencies. It is a characteristic.

  On the other hand, when the complementary connection configuration shown in FIG. 7A is employed for the MOS capacitor 10, the C-Vg characteristic indicated by the solid line in FIG. 7B is obtained. That is, the MOS capacitive element 10 having such a complementary connection configuration exhibits a substantially constant capacitance value regardless of whether the applied DC bias voltage is positive or negative. Further, in the MOS capacitive element 10 having such a complementary connection configuration, the C-Vg characteristic is substantially independent of frequency. This is because no depletion layer is formed in the semiconductor layer 11B immediately below the capacitor electrode 11c, regardless of whether the polarity of the voltage applied to the capacitor electrode 11c is positive or negative. This means that the layer or the hole accumulation layer is formed continuously with the n + type diffusion region 11h or continuously with the p + type diffusion region. In such a carrier storage layer, carriers induced on the surface of the semiconductor layer 11B can follow the voltage applied to the capacitor electrode 11c at high speed.

  As described above, the MOS type capacitive element 10 having the configuration shown in FIGS. 6A and 6B connected in a complementary manner as shown in FIG. 7A has a positive voltage and a negative voltage. However, the capacitance value is almost constant.

  8A and 8B show the case where the DC bias power source 22 is omitted in the test apparatus of FIG. 7A and a symmetrical high frequency AC signal used for driving a liquid crystal display device is applied. The capacitance characteristic of the MOS type capacitive element 10 is shown. 8A shows the waveform of the high-frequency AC signal, and FIG. 8B shows the capacitance of the MOS capacitor 10 corresponding to the waveform of FIG. 8A.

  Referring to FIG. 8A, the drive signal used in the liquid crystal display device is a symmetric rectangular wave signal having an amplitude between the minimum level Vmin and the maximum level Vmax. As shown in FIG. 8B, it can be seen that the MOS capacitance element exhibits a substantially constant capacitance regardless of the polarity of the drive signal and the amplitude, as shown in FIG. 8B. However, in FIG. 8B, the vertical axis is the normalized capacitance C / Co normalized by the capacitance Co of the insulating film 10C, and the horizontal axis is applied to the capacitor electrode 11c by the signal of FIG. 8A. Voltage.

  As described above, the MOS type capacitive element according to the present invention shown in FIGS. 6 (A) and 6 (B) is complementary to the negative voltage as shown in FIG. 7 (A). In addition, both the low frequency signal and the high frequency signal exhibit substantially the same capacitance and operate as an effective capacitor. Further, the MOS type capacitive element of the present invention can be formed simultaneously with the manufacturing process of other MOS transistors without adding any process, and the manufacturing cost of an electronic device using such a MOS type capacitive element such as a liquid crystal display device. Can be reduced. Further, in the MOS type capacitive element of this embodiment, the n + type diffusion region 11h and the p + type diffusion region 11i are formed by performing ion implantation after covering the semiconductor layer 10B with the insulating film 10C. The problem of contamination by the impurity element of the semiconductor layer 10B as in the conventional example 4 does not occur. Accordingly, the problem that the threshold voltage and other operating characteristics of the transistor formed simultaneously with the MOS capacitor on the semiconductor layer 10B fluctuate due to contamination by the impurity element is solved. Further, when the MOS type capacitive element according to the present invention is used for driving a liquid crystal display device, the capacitor electrode only needs to be held at a common potential, so that the stress applied to the insulating film 10C or other interlayer insulating film is reduced. Thus, deterioration of display characteristics due to such stress is avoided.

  According to the features of the present invention described in claims 1 to 6, the manufacturing cost of the liquid crystal display device can be reduced by using the MOS type capacitive element according to the present invention for the liquid crystal display device. Such a liquid crystal display device can be manufactured with high reliability and high yield because stress applied to the gate insulating film, capacitor insulating film, or other interlayer insulating film is reduced.

  Further, according to the feature of the present invention described in claim 7, it becomes possible to manufacture the MOS type capacitive element according to the present invention, a liquid crystal display device using the same, or a semiconductor integrated circuit device using the same.

[First embodiment]
9A to 9E show the manufacturing process of the MOS capacitor 30 according to the first embodiment of the present invention.

  Referring to FIG. 9A, a semiconductor pattern 32 such as polysilicon or amorphous silicon is formed on a substrate 31, and SiO2 is formed so as to cover the semiconductor pattern 32 on the substrate 31 in the step of FIG. A dielectric film 33 made of or the like is formed. The substrate 31 may be a glass substrate of a liquid crystal display device or other insulating substrate. The substrate 31 may be a single crystal Si substrate. The semiconductor pattern 32 may be a single crystal Si pattern.

  Further, in the step of FIG. 9C, a conductive film such as Al or conductive polysilicon is deposited on the dielectric film 33, and a capacitor electrode 34 is formed by patterning the conductive film. Further, in the step of FIG. 9D, an n-type impurity element such as As + or P + is introduced by ion implantation into the semiconductor pattern 32 through the dielectric film 33 using the capacitor electrode 34 as a self-aligned mask, Subsequent heat treatment forms an n + type diffusion region 32A on one side of the capacitor electrode. During the n-type impurity element ion implantation process, the other side of the capacitor electrode 34 of the semiconductor pattern 32 is covered with a resist mask.

  Next, the resist mask is removed in the step of FIG. 9E, the one side of the capacitor electrode 34 of the semiconductor pattern 32 is covered with another resist mask, and the dielectric film 33 is interposed through the dielectric film 33. By introducing a p-type impurity element such as BF + into the semiconductor pattern 32 by ion implantation and subsequently performing heat treatment, a p + type diffusion region 32B is formed on the other side of the capacitor electrode.

  In the manufacturing process of the MOS type capacitive element 30 according to the present embodiment, since the ion implantation process is performed in the processes (D) and (E) after the semiconductor pattern 32 is covered with the dielectric film 33, the semiconductor The problem that the surface of the pattern 32 is contaminated with an impurity element is avoided. Further, the steps of FIGS. 9A to 9E are completely compatible with a step of forming a MOS transistor, particularly a manufacturing step of a top gate type TFT used in a liquid crystal display device. It is possible to form another MOS transistor on the semiconductor pattern 32 simultaneously with the formation of the MOS type capacitive element 30.

  For example, when a top gate type n-channel TFT is formed adjacent to the MOS type capacitive element 30, in the step of FIG. 9C, the capacitor electrode 34 is formed on the semiconductor pattern 32 at the same time or other similar ones. A gate electrode may be formed on the semiconductor pattern, and in the step of FIG. 9D, n + type source and drain regions may be formed on both sides of the gate electrode simultaneously with the formation of the diffusion region 32A. . When the TFT to be formed is a p-channel TFT, a p + -type source region and drain region are formed on both sides of the gate electrode simultaneously with the diffusion region 32B in the step of FIG. 9E.

  The MOS capacitor 30 formed in this way has the preferable capacitance characteristics described above with reference to FIG. 7B or FIG.

  FIG. 10A shows a MOS type capacitive element 30A according to a modification of the MOS capacitive element 30 of FIG.

  Referring to FIG. 10A, in the MOS capacitor element 30A, the n + type diffusion region 32A is formed apart from the capacitor electrode 34 in the semiconductor pattern 32, and an n− type LDD region 32a is formed therebetween. Is done. Similarly, the p + type diffusion region 32B is also formed apart from the capacitor electrode 34, and a p− type LDD region 32b is formed therebetween. The LDD region 32a or 32b can be formed by forming a sidewall insulating film on the capacitor electrode 34, for example. Alternatively, a separate mask process may be performed. By forming the LDD region 32a or 32b, the breakdown voltage of the MOS capacitor 30A can be increased.

  FIG. 10B shows a MOS type capacitive element 30B according to a modification of the MOS type capacitive element 30A of FIG.

  Referring to FIG. 10B, in the MOS capacitor 30B, only one of the LDD regions, for example, the LDD region 32b in the MOS capacitor 30A of FIG. 10A is omitted. Even in such a configuration, the breakdown voltage of the MOS capacitor can be increased.

  FIG. 10C shows a MOS type capacitive element 30C according to still another modification of the MOS capacitive element 30A shown in FIG.

  Referring to FIG. 10C, in the MOS capacitive element 30C, the n + -type diffusion region 32A is formed in the semiconductor pattern 32 so as to be separated from the capacitor electrode 34, and an offset region 32c is formed therebetween. Similarly, the p + type diffusion region 32B is also formed apart from the capacitor electrode 34, and an offset region 32d is formed therebetween. By forming the offset region 32c or 32d, the breakdown voltage of the MOS capacitor 30C can be increased.

  FIG. 11 is a plan view of the MOS capacitor 30 of FIG.

  Referring to FIG. 11, a capacitor electrode 34 covers the central portion of the semiconductor pattern 32, and a portion of the semiconductor pattern 32 exposed on one side of the capacitor electrode 34 is doped with an n + type diffusion region. 32A is formed, and the portion exposed on the other side is doped p + type to form a diffusion region 32B. Further, an ohmic contact 32A ′ is formed in the n + type diffusion region 32A, and an ohmic contact 32B ′ is formed in the p + type diffusion region 32B.

  FIG. 12A shows a plan view of a MOS capacitor 30D according to a modification of the MOS capacitor 30 of FIG.

  Referring to FIG. 12A, in the MOS type capacitive element 30D according to the present embodiment, the semiconductor pattern 32 is exposed only on one side of the capacitor electrode 34 and adjacent to the exposed portion, the n + A type diffusion region 32A and a p + type diffusion region 32B are formed. In this configuration, the ohmic contacts 32A ′ and 32B ′ are formed as single continuous ohmic contacts on the diffusion regions 32A and 32B, respectively, so that the n + type diffusion region 32A and the p + type diffusion region 32B are formed. The complementary connection configuration can be easily realized.

  FIG. 12B is a plan view of a MOS capacitor 30E according to a modification of the MOS capacitor 30D of FIG.

Referring to FIG. 12B, in this embodiment, the capacitor electrode 34 is included in a plan view in the semiconductor pattern 32, and one of the exposed portions of the semiconductor pattern 32 is doped n + type. As a result, the diffusion region 32A is formed, and the other is doped p + type to form the diffusion region 32B. Similarly to the embodiment of FIG. 12A, the ohmic contact 32A ′ of the diffusion region 32A and the ohmic contact 32B ′ of the diffusion region 32B are continuously formed to form a single ohmic contact. . Thereby, also in the present embodiment, a configuration in which the n + type diffusion region 32A and the p + type diffusion region 32B are complementarily connected can be easily realized.

[Second Embodiment]
13A to 13E show a manufacturing process of the MOS capacitor 40 according to the second embodiment of the present invention, which is compatible with the manufacturing process of a bottom gate TFT.

  Referring to FIG. 13A, a capacitor electrode pattern 42 made of conductive amorphous silicon or the like is formed on an insulating substrate 41 such as a glass substrate, and the capacitor is formed on the insulating substrate 41 in a step shown in FIG. A dielectric film 43 made of a SiO2 film or the like is deposited so as to cover the electrode pattern 42. Further, in the step of FIG. 13B, an amorphous silicon film 44 is deposited on the dielectric film 43.

  Further, in the step of FIG. 13C, the amorphous silicon film 44 is patterned to form a semiconductor pattern 44P. In the step of FIG. 13D, one side of the capacitor electrode pattern 42 in the semiconductor pattern 44P. An n + type diffusion region 44A is formed by ion-implanting As + or P + into this portion.

  Further, in the step of FIG. 13E, p + type diffusion region 44B is formed by ion-implanting BF + into the other side of the capacitor electrode pattern 42 in the semiconductor pattern 44P. 13D and 13E may be performed through the insulating film after the semiconductor pattern 44P is covered with the insulating film.

The MOS type capacitive element 40 according to this embodiment can be formed simultaneously with the bottom gate type TFT in an active matrix type liquid crystal display device or the like.

[Third embodiment]
14A and 14B show an example in which the MOS capacitor 30 described above is applied to the liquid crystal cell driving circuit of the active matrix liquid crystal display device shown in FIG. 3, according to the third embodiment of the present invention. A drive circuit 50 is shown. However, in FIGS. 14A and 14B, the same reference numerals are given to the portions described above, and the description thereof is omitted.

  Referring to FIG. 14A, the driving circuit 50 according to the present embodiment is formed on the semiconductor layer 10B made of polysilicon or the like and on the semiconductor layer 10B adjacent to the TFT 11a. The MOS capacitance element 30 is included. The TFT 11a includes n + type diffusion regions 10a and 10b formed in the semiconductor layer 10B in the same manner as described above with reference to FIG. 5, and the diffusion regions 10a and 10b are formed on the insulating film 10C. A gate electrode 11a is formed therebetween. The insulating film 10C forms a gate insulating film immediately below the gate electrode 11a.

  On the other hand, the MOS type capacitive element 30 has the configuration shown in FIG. 6A or 9E, and in the semiconductor layer 10B, the n + type diffusion region 10h in FIG. The diffusion region 32A of 9 (E) includes the diffusion region 10b, and further includes a p + -type diffusion region 10i corresponding to the diffusion region 32B of FIG. 9 (E). Further, a capacitor electrode 11c is formed on the insulating film 10C between the diffusion regions 10b and 10i.

  A control signal VG shown in FIG. 14B is supplied to the gate electrode 11a through the signal line 13. Referring to FIG. 14B, the control signal VG is normally at the level of -Vgl, and transitions to the level of + Vgl only when the TFT 11a is selected. The video signal VS shown in FIG. 14B is supplied to the diffusion region 10 a, and the video signal is sent to the diffusion region 10 b through the channel region of the TFT 11 a and is held in the MOS capacitor 30. The The video signal VS is a symmetric AC signal having a frame period T as shown in FIG. 14B, and the value alternately changes between + Vmin and -Vmin in the interval of the minimum signal level. In the interval, the value changes alternately between + Vmax and -Vmax. In the intermediate signal level section, the signal value changes alternately between positive and negative at an intermediate level between Vmax and Vmin. Further, the capacitor electrode 11c is held at a common potential level (Vcom) applied to the transparent counter electrode on the counter substrate 1B (see FIG. 1). The capacitor electrode 11c is connected to the capacitor line 17 of FIG. 3, but in the present embodiment, the common potential Vcom is supplied to the capacitor line.

  The video signal VS held in the MOS type capacitive element 30 is applied from the n + type diffusion region 10b to the liquid crystal cell 15 through the pixel electrode 14 (see FIG. 2).

  In this embodiment, the MOS capacitor 30 has the characteristics described above with reference to FIG. 7B or 8B, and stably holds the video signal VS having positive and negative polarities.

  As described above, the MOS capacitor 30 is completely compatible with the manufacturing process of the TFT 11a, and can be formed simultaneously with the formation of the TFT 11a.

In the active matrix drive liquid crystal display device, by using the MOS capacitor 30 according to the present invention in combination with the TFT 11a, the voltage applied to the liquid crystal cell 15 is stabilized, and high-quality and stable display becomes possible. In this embodiment, the voltage supplied to the capacitor line 17 may be the same voltage as the voltage supplied to the transparent counter electrode, so that it is not necessary to provide a separate drive power source to drive the capacitor line 17. .

[Fourth embodiment]
FIG. 15 shows a configuration of a liquid crystal panel 60 of a direct view type liquid crystal display device using the liquid crystal cell driving circuit 50 of FIGS. 14 (A) and 14 (B). However, the same reference numerals are given to the portions described above in the drawing, and the description will be omitted.

  Referring to FIG. 15, the liquid crystal panel 60 includes the TFT substrate 1A described in FIG. 1, a counter substrate 1B, and the liquid crystal layer 1 enclosed therebetween, and the TFT substrate 1A has the matrix shape. Corresponding to the arranged pixel electrodes 14 (see FIG. 2), the liquid crystal cell driving circuits 50 (not shown) in FIG. 14A are arranged in a matrix. Further, a gate side peripheral circuit 1G for selecting the gate control line 13 and a signal side peripheral for selecting the signal line 12 are arranged on the TFT substrate 1A so as to surround the array of the pixel electrode 14 and the liquid crystal cell driving circuit 50. A circuit 1V is formed.

On the other hand, on the counter substrate 1B, red, green and blue three-color filters corresponding to the respective pixels are formed in a matrix on the counter surface facing the substrate 1A so as to cover the three-color filters. A transparent counter electrode (not shown) is uniformly formed on the counter surface. The same common potential Vcom as that supplied to the capacitor electrode 11c of the MOS capacitor 30 is supplied to the transparent counter electrode at the counter electrode contacts 1Bc formed at the four corners of the substrate 1B.

[Fifth embodiment]
FIG. 16 shows a configuration of a liquid crystal panel 70 used in a projection type liquid crystal display device using the liquid crystal cell driving circuit 50 shown in FIGS. 14 (A) and 14 (B). However, the same reference numerals are given to the portions described above in the drawing, and the description will be omitted.

  Referring to FIG. 16, the liquid crystal panel 70 includes a TFT substrate 1A and a counter substrate 1B shown in FIG. 1 and a liquid crystal layer 1 sealed therebetween, and is arranged in the matrix on the TFT substrate 1A. Corresponding to the pixel electrodes 14 (see FIG. 2), the liquid crystal cell driving circuits 50 in FIG. 14A are arranged in a matrix. Further, a gate side peripheral circuit 1G for selecting the gate control line 13 and a signal side peripheral for selecting the signal line 12 are arranged on the TFT substrate 1A so as to surround the array of the pixel electrode 14 and the liquid crystal cell driving circuit 50. A circuit 1V is formed.

  On the other hand, on the counter substrate 1B, a transparent counter electrode (not shown) is uniformly formed on the counter surface facing the substrate 1A. Similarly to the liquid crystal panel 70 of FIG. 15, the same common potential Vcom as that supplied to the capacitor electrode 11 c of the MOS capacitor 30 is supplied to the transparent counter electrode at the counter electrode contact 1 Bc. Further, a light shielding pattern BM is formed on the counter substrate 1B so as to cover the circuit 1G or 1V on the TFT substrate 1A. Similar light shielding patterns are also provided in the individual liquid crystal cell driving circuits 50 arranged in a matrix, although not shown.

  FIG. 17 shows a configuration of a projection type liquid crystal display device 80 using the liquid crystal panel 70 of FIG.

  Referring to FIG. 17, the projection display device 80 includes a powerful light source 81 such as a metal halide lamp and a light beam 82 emitted from the light source 81 through an ultraviolet cut filter 81A formed as a part of the light source 81. A dichroic mirror 91 that transmits the blue light component and reflects the other light, and is disposed in the optical path of the light beam reflected by the dichroic mirror 91, and transmits the red light component. A dichroic mirror 92 that reflects and transmits other light, that is, a green light component, and a mirror 93 that is disposed in the optical path of the blue light beam that has passed through the dichroic mirror 91 and reflects it, and The blue light beam B that has passed through the dichroic mirror is reflected by the mirror 93 and then passes through the incident-side polarizing element 90B. Incident on the light valve 93B made of the liquid crystal panel 70.

  The blue light beam B that has passed through the liquid crystal panel 93B is further subjected to spatial modulation by the output-side polarizing element 94B disposed in a crossed Nicols state with respect to the incident-side polarizing element 90B.

  Similarly, the red light beam separated by the dichroic mirror 22 is allowed to pass through the incident-side polarizing device 90R, further passes through the liquid crystal panel 93R, and is subjected to spatial modulation by the output-side polarizing element 94R. The red light beam spatially modulated by the exit side polarization element 94R is combined with the blue light beam spatially modulated by the exit side polarization element 94B in the dichroic mirror 94 and is incident on another dichroic mirror 96.

Similarly, the green light beam separated by the dichroic mirror 92 is allowed to pass through the incident-side polarizing element 90G, further passes through the liquid crystal panel 93G, and then undergoes spatial modulation by the outgoing-side polarizing element 94G. The green light beam spatially modulated by the output side polarization element 94G is further incident on the other dichroic mirror 96 by a mirror 95, and is combined with the spatially modulated blue light beam and red light beam. The combined light beam is projected on the screen 98 by the projection optical system 97.

[Sixth embodiment]
FIG. 18 shows a configuration of a semiconductor integrated circuit 100 using the MOS type capacitive element 10 or 30 according to the present invention.

Referring to FIG. 18, a semiconductor integrated circuit 100 is formed on a p-type Si substrate 101, and a thermal oxide film 102 having a thickness of typically 10 to 0 nm is formed on the Si substrate 101. On the substrate 101, an element isolation structure is formed by a field oxide film 102A between a region 100A where an active element such as a MOS transistor is formed and a region 100B where a MOS capacitor element is formed. Further, n + type diffusion regions 101A and 101B are formed in the region 100A on the surface of the Si substrate 101, and n + type diffusion regions 101C and p + type diffusion regions 101D are formed in the region 100B. Further, a gate electrode 103A made of Al, polysilicon or WSi is formed on the thermal oxide film 102 between the diffusion regions 101A and 101B, and a capacitor electrode 103B is formed between the diffusion regions 101C and 101D. The gate electrode 103A is made of the same material. Further, in the region 100B, the diffusion regions 101C and 101D are connected in common, and as a result, a MOS type capacitive element having a complementary connection configuration similar to that described in the first embodiment is formed in the region 100B. The

[Seventh embodiment]
FIG. 19 shows a configuration of a transfer gate circuit 110 according to the seventh embodiment of the present invention, which is honored by using the complementary-connected MOS type capacitive element 100B of FIG.

Referring to FIG. 19, a signal input to the input terminal 111 is held in the form of a charge in the capacitor C1 corresponding to the complementary MOS type capacitive element 100B in FIG. 18, and the charge held in the capacitor C1. Is transferred to a similar capacitor C2 on the output side by a MOS transistor Tr that is turned on by a control signal supplied to the input terminal 113. Accordingly, an output signal appears at the output terminal 112 connected to the capacitor C2.

[Eighth embodiment]
FIG. 20 shows a configuration of a transfer gate circuit 115 according to the eighth embodiment of the present invention, which is a modification of the transfer gate circuit 110 of FIG. However, in FIG. 20, the same reference numerals are given to the parts described above, and the description thereof is omitted.

  Referring to FIG. 20, in this embodiment, the transistor Tr in the circuit of FIG. 19 is replaced with a configuration in which a p-channel MOS transistor Tr1 and an n-channel MOS transistor Tr2 are connected in parallel. At that time, the transistor Tr1 is controlled to be conductive by a first control signal supplied to the input terminal 113, and the transistor Tr2 is controlled to be conductive by a second control signal supplied to the input terminal 114.

Other features of the circuit 112 are the same as those of the circuit 110, and a description thereof will be omitted.
[Ninth embodiment]
FIG. 21 shows an example of the sampling circuit 120 according to the ninth embodiment of the present invention using the complementary-connected MOS type capacitive element 100B of FIG.

Referring to FIG. 21, an input signal input to input terminal 121 is complementary to MOS type capacitive element 100B of FIG. 18 through MOS transistor T1 that is turned on by a control signal supplied to control signal terminal 122. It is sent to the MOS capacitor element C3 and held in the form of electric charges. The charge held in the capacitive element C3 makes the MOS transistor T3 conductive, and makes the MOS transistor T2 connected in series to the transistor T3 conductive by the sampling signal supplied to the control signal terminal 123 of the transistor T2. Thus, the charge in the capacitive element C3 is supplied to the output terminal 124 through the transistor T2.

[Tenth embodiment]
FIG. 22 shows a configuration of a photoelectric conversion circuit 130 according to the tenth embodiment of the present invention using the complementary-connected MOS type capacitive element 100B of FIG.

  Referring to FIG. 22, the photoelectric conversion circuit 130 includes a photodiode D1 biased by a bias voltage supplied to a bias power supply terminal 131. When the photodiode D1 is turned on by an incoming light signal, the bias power supply terminal 131 is turned on. Is applied to the capacitor C4 via the MOS transistor T4 which is turned on by the control signal supplied to the control signal terminal 132, and charges the capacitor C4. The capacitor C4 has a configuration corresponding to the complementary MOS capacitor 100B shown in FIG.

In the circuit 130 of FIG. 22, the charge held in the capacitor C4 is read by the amplifier 133 in this way, and an output signal corresponding to the output terminal 134 is obtained. The circuit 130 includes a MOS transistor T5 that discharges the capacitor C4. The transistor T5 is turned on in response to a reset signal that enters the reset terminal 135.

[Eleventh embodiment]
FIG. 23 shows a configuration of a photoelectric conversion circuit 140 according to the eleventh embodiment of the present invention using the complementary-connected MOS type capacitive element 100B of FIG.

  Referring to FIG. 23, the photoelectric conversion circuit 140 is charged by a MOS transistor T6 that is turned on by a reset signal input to the reset terminal 141, and is a capacitor Ct corresponding to the complementary-connected MOS type capacitive element 100B of FIG. A photodiode D1 is connected in parallel with the capacitor Ct.

  When an optical signal enters the photodiode D1, the capacitor Ct is discharged, and accordingly, the MOS transistor T7 supplied with the power supply voltage is turned off in cooperation with the capacitor Ct. Between the transistor T7 and the ground potential, there are provided transistors T8 and T9 which are inserted in series with the transistor T7 and kept conductive by the bias circuit 142. Therefore, when the transistor T7 is turned off, the transistor T7 is turned off. And the potential of the connection node 143 between T8 decreases. Therefore, in this state, when the transistor T10 is turned on by the control signal input to the control input terminal 144, the capacitor CL connected to the output side of the transistor T10 and corresponding to the complementary MOS type capacitive element 100B of FIG. Discharging through the transistors T10, T8, and T7, the potential change of the capacitor CL accompanying this is detected by the amplifier 145 and supplied to the output terminal 146 as a low level output signal.

On the other hand, in the circuit 140 of FIG. 23, when an optical signal does not enter the photodiode D1, the capacitor Ct is in a charged state. Accordingly, the transistor T7 is turned on, and the capacitor T10 is turned on via the transistor T10. CL is charged. In this state, a high level output signal is output from the output terminal 146.

[Twelfth embodiment]
FIGS. 24A and 24B are a sectional view and a plan view showing the configuration of the driving circuit 150 for the liquid crystal cell according to the twelfth embodiment of the present invention.

  Referring to FIGS. 24A and 24B, in this embodiment, in the driving circuit 50 of FIG. 14A, the p + -type diffusion region 10i extends below the capacitor electrode 11c, and the n + -type diffusion region 10c. A p + -type diffusion region 10j that is continuous is formed.

  24A and 24B, the capacitance line 17 is held at the ground level, and the selection signal supplied to the control line 13 is the ground level and the power supply voltage VDD as shown in FIG. The voltage applied between the control line (scanning electrode) 13 and the capacitor line 17 becomes the VDD level at the maximum, and the stress applied to the insulating film or interlayer insulating film in the liquid crystal display device. Decrease.

  Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to such specific embodiments, and various modifications and changes can be made within the scope described in the claims.

It is a general-view figure which shows the conventional liquid crystal display device. It is a figure which expands and shows a part of liquid crystal display device of FIG. FIG. 2 is a circuit diagram showing a part of a liquid crystal cell driving circuit used in the liquid crystal display device of FIG. 1. It is sectional drawing which shows the structure of the conventional liquid crystal cell drive circuit. It is sectional drawing which shows the structure of another conventional liquid crystal cell drive circuit. (A), (B) is a figure (the 1) explaining the principle of this invention. (A), (B) is a figure (the 2) explaining the principle of this invention. (A), (B) is a figure (the 3) explaining the principle of this invention. (A)-(E) are figures which show the manufacturing process of the MOS type capacitive element by 1st Example of this invention. (A)-(C) are figures which show the various modifications of the MOS type capacitive element by 1st Example of this invention. 1 is a plan view showing a MOS type capacitive element according to a first embodiment of the present invention. (A), (B) is a figure which shows the various modifications of the MOS type capacitive element of FIG. FIGS. 8A to 8E are diagrams illustrating a process for manufacturing a MOS capacitor according to a second embodiment of the present invention. FIGS. (A), (B) are sectional views showing the configuration of a liquid crystal cell driving circuit of an active matrix driving liquid crystal display device according to a third embodiment of the present invention, and various signal waveforms applied to the liquid crystal cell driving circuit. FIG. It is a figure which shows the liquid crystal panel structure used with the direct view type liquid crystal display device by 4th Example of this invention. It is a figure which shows the structure of the liquid crystal panel used by the projection type liquid crystal display device by 5th Example of this invention. It is a figure which shows the structure of the projection type liquid crystal display device using the liquid crystal panel of FIG. It is a figure which shows the structure of the semiconductor integrated circuit by 6th Example of this invention. It is a circuit diagram which shows the structure of the transfer gate circuit by 7th Example of this invention using the semiconductor integrated circuit of FIG. FIG. 19 is a circuit diagram showing a configuration of a transfer gate circuit according to an eighth embodiment of the present invention using the semiconductor integrated circuit of FIG. 18. It is a circuit diagram which shows the structure of the sampling circuit by the 9th Example of this invention using the semiconductor integrated circuit of FIG. It is a circuit diagram which shows the structure of the photoelectric conversion circuit by 10th Example of this invention using the semiconductor integrated circuit of FIG. It is a circuit diagram which shows the structure of the photoelectric conversion circuit by 11th Example of this invention using the semiconductor integrated circuit of FIG. (A) and (B) are a sectional view and a plan view showing a configuration of a liquid crystal cell driving circuit of an active matrix driving liquid crystal display device according to a twelfth embodiment of the present invention.

Explanation of symbols

1 liquid crystal layer 1A, 10A TFT substrate 1B counter substrate 1Bc counter electrode contact 1C seal 1G gate side peripheral circuit 1V signal side peripheral circuit 10 MOS type capacitive element 10B semiconductor pattern 10C insulating films 10a, 10b, 10c, 10d, 10e, 10h n + Type diffusion region 10f lightly doped region 10i p + type diffusion region 11, 11A, 11B TFT
11a, 11b Gate electrode 11c Capacitor electrode 12 Signal electrode (signal line)
12A, 13A Electrode pad 13 Scan electrode (control line)
14 pixel electrode 15 liquid crystal cell 16 storage capacitor 17 capacitor line 21 AC power source 22 DC bias power source 30, 30A, 30B, 30C, 30D, 30E MOS type capacitive element 31, 41 substrate 32, 44 semiconductor pattern 32A, 44A n + type diffusion region 32A ′, 32B ′ ohmic contact 32a n− type LDD region 32B, 44B p + type diffusion region 32b p− type LDD region 32c, 32d offset region 33, 43 insulating film 34, 42 capacitor electrode 50, 150 liquid crystal cell driving circuit 60 direct view Type liquid crystal display panel 70 projection type liquid crystal display panel 80 projection type liquid crystal display device 81 light source 81A ultraviolet cut filter 82 light beams 91, 92, 94, 96 dichroic mirrors 93, 95 mirrors 90R, 90G, 90B incident side polarizing elements 93R, 93G , 93B LCD panel 94R, 94G, 94B Emission side polarization element 97 Projection optical system 98 Screen 100 Semiconductor integrated circuit device 101 Semiconductor substrate 101A, 101B, 101C n + type diffusion region 101D p + type diffusion region 102 Thermal oxide film 102A Field oxide film 103A Gate electrode 103B Capacitor electrode 110, 115 Transfer gate circuit 111, 121 Input terminal 112, 124, 134, 146 Output terminal 113, 114, 122, 123, 132, 144 Control input terminal 120 Sampling circuit 130, 140 Photoelectric conversion circuit 131 Bias input terminal 133 , 145 Amplifier 135, 141 Reset input terminal 142 Bias circuit

Claims (7)

A first glass substrate;
A second glass substrate facing the first glass substrate;
A liquid crystal layer sealed between the first glass substrate and the second glass substrate;
A signal electrode extending on the first glass substrate;
A scan electrode extending on the first glass substrate;
A common potential line extending on the first glass substrate;
A thin film transistor formed at the intersection of the signal electrode line and the scan electrode;
A pixel electrode electrically connected to the thin film transistor;
In a liquid crystal display device comprising a storage capacitor connected in parallel to the pixel electrode,
The thin film transistor is formed in a semiconductor layer formed on the first glass substrate,
The storage capacity is
An insulating film formed on the semiconductor layer;
A capacitor electrode formed on the insulating film so as to be included in a planar pattern of the semiconductor layer ;
Of the semiconductor layer, the exposed portion exposed from the capacitor electrode includes a first diffusion region formed on one side of the capacitor electrode and a second diffusion region formed on the other side of the capacitor electrode . Consisting of diffusion areas,
The first diffusion region is doped to a first conductivity type and the second diffusion region is doped to a second, reverse conductivity type ;
The liquid crystal display device, wherein the first diffusion region and the second diffusion region are formed in alignment with the edge of the capacitor electrode and adjacent to each other at two locations .   The thin film transistor includes a third diffusion region having the first conductivity type formed in the semiconductor layer and separated from the first diffusion region by a channel region, and the semiconductor on the insulating film. A gate electrode formed so as to cover the channel region in the layer, the first and second diffusion regions are connected to the pixel electrode in common, the capacitor electrode is connected to the common potential line, The liquid crystal display device according to claim 1, wherein the third diffusion region is connected to the signal line, and the gate electrode is connected to the scanning electrode.   The first diffusion region is formed substantially coincident with a first edge formed on one side of the capacitor electrode in the semiconductor layer, and the second diffusion region is formed on the semiconductor layer. 3. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is formed so as to substantially coincide with a second edge formed on the other side of the capacitor electrode.   The first diffusion region is outside the first edge formed on one side of the capacitor electrode in the semiconductor layer and between the region immediately below the capacitor electrode and the first conductivity type. The second diffusion region is formed on the outer side of the second edge formed on the other side of the capacitor electrode in the semiconductor layer and directly below the capacitor electrode. 3. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is formed via a second LDD region of the second conductivity type.   The first diffusion region is located outside the first edge formed on one side of the capacitor electrode in the semiconductor layer, with a first offset region between the region immediately below the capacitor electrode and the first diffusion region. The second diffusion region is formed outside the second edge formed on the other side of the capacitor electrode in the semiconductor layer and between the region immediately below the capacitor electrode. 3. The liquid crystal display device according to claim 1, wherein the liquid crystal display device is formed through an offset region. Wherein the first diffusion region and the second diffusion region, the liquid crystal display device according to claim 1 or 2, wherein the being made form adjacent to the edge of the capacitor electrode. In the method of manufacturing a liquid crystal display device having a MOS type capacitive element, the MOS type capacitive element is:
Forming a semiconductor layer on a glass substrate;
Forming an insulating film on the semiconductor layer ;
Forming a capacitor electrode included in a planar pattern of the semiconductor layer on the insulating film;
Using the capacitor electrode as a mask, introducing an impurity element of a first conductivity type into the semiconductor layer on one side of the capacitor electrode, and forming a first diffusion region ;
Using the capacitor electrode as a mask, introducing a second, reverse conductivity type impurity element into the semiconductor layer on the other side of the capacitor electrode, and forming a second diffusion region ;
The method of manufacturing a liquid crystal display device, wherein the first diffusion region and the second diffusion region are formed in alignment with an edge of the capacitor electrode and adjacent to each other at two locations. .

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