JPS63204655A - Mis transistor - Google Patents

Abstract

PURPOSE:To enable an MIS transistor to have increased drive current capacity without deteriorating its stability in operation, by providing the MIS transistor with a lattice-shaped gate electrode so as to divide an element forming region into island-type sub-regions having identical configurations. CONSTITUTION:An element forming region 2 demarkated by field insulation films 20 on one principal surface of an N-type semiconductor substrate 30 is divided into a plurality of sub-regions by gate electrode layers 3-1-3-8 having planar lattice configurations and gate insulation films 11-1-11-7 directly under the gate electrode layers. The sub-regions have source electrode layers 12-1-12-5 and drain electrode layers 10-1-10-4 and the source electrode layer 12-3 is connected to a substrate biasing region 6 provided by an N-type highly doped region formed in one of the sub-regions. The source electrode layers and drain electrode layers are arranged altenately one by one and such that they obliquely intersect gate electrode layers 3-1-3-8. In this manner, it is possible to provide a regular transistor structure having a large gate length per unit area over a large surface area and, thus, it is possible to satisfy both requirements of drive current capacity and stable operation.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to MIS transistors, and in particular to MOS transistors with a long gate length per unit area, used for output buffers, etc.
Regarding S transistor.

[Conventional technology]

Conventionally, there is a conventional example of the shape of this type of MoS transistor as shown in FIG. 4 for the purpose of making the gate length per unit area as long as possible. In this example, by shifting the contact positions of both the source and drain regions, the gate electrode layers 3-1 to 3-4 are made to meander to increase the gate length, and the distance between the source and drain region contacts in the vertical and horizontal directions is By shortening , the area of the source train region is reduced.

In addition, as another conventional example, as shown in FIG.
, and the drain region 4.

In the example shown in FIG. 5, although the vertical and horizontal distances between the source and drain contacts are larger than in the example shown in FIG. 4, the gate length can be made very long. - The area of the drain region can be reduced and the contacts can be arranged in multiple stages, resulting in a transistor with low parasitic capacitance and low contact resistance.

[Problem that the invention seeks to solve]

The conventional MOS transistor mentioned above is usually used in an output buffer section that requires high current drive, and the P-channel MO transistor and N-channel MOS transistor are
) - When constructing a CMO8 type O8 inverter using a transistor, the source electrode of the P channel M○S transistor is biased to a positive power supply potential, and the source electrode of the N channel MOS)
The source electrode of a transistor is biased to a negative power supply potential, and it is well known that when a high current flows under such conditions, the substrate potential changes, and as a result, latch-up phenomenon is likely to occur. There is. For this reason, in the conventional MOS transistor structure, a substrate potential bias region is provided around the transistor in order to suppress changes in the substrate potential. The drawback is that a transistor structure with a long gate length per area cannot be constructed over a very large area, and it is not possible to satisfy both drive current capability and stable operation.

[Means for solving problems]

The MIS) transistor of the present invention includes a gate electrode layer having a lattice-like planar shape and a gate insulating film immediately below the gate electrode layer, and an element-shaped region defined by a field insulating film on one principal surface of a first conductivity type semiconductor substrate. A plurality of source electrode layers and train electrode layers are divided into a plurality of partial regions, obliquely intersecting with the gate electrode layer, and arranged every other region, and at least one of the source electrode layers is in the portion. It is connected to a substrate bias region made of a high concentration first conductivity type impurity region provided in at least one of the regions.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor chip showing a first embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA' in FIG.

Note that drain electrode layers 10-1 to 10-4. The train lead electrode 10, the source electrode layers 12-1 to 12-5, and the source lead electrode 8i12 are located in the uppermost layer, but are shown by broken lines for convenience.

In this embodiment, gate electrode layers 3-1 to 3-8 having a lattice-like planar shape and a gate insulating film 11-1 immediately below them are partitioned by a field insulating film 20 on one main surface of an N-type semiconductor substrate 30. The element formation region 2 is divided into a plurality of partial regions, and source electrode layers 12-1 to 12-5 and drain electrodes are arranged obliquely to the gate electrode layers 3-1 to 3-8 and arranged every other layer. It has layers 10-1 to 10-4, and the source electrode layer 12-3 is connected to a substrate bias region 6 made of a high concentration N-type impurity region provided in one of the partial regions. be.

A field insulating film 20 is selectively formed on an N-type semiconductor substrate 30 to provide an element formation region 2, and the film thickness is, for example, 600 nm.
Gate electrode layer 3-1 made of a polycrystalline silicon film of about m
3-8 are formed in a lattice shape, and within the element formation region 2, a gate oxide film 11-1 . It is configured to function as a gate electrode via... The element formation region 2 is divided into a mesh shape by the gate electrode layers 3-1 to 3-8, and a portion of the island-shaped partial region that will become the substrate bias region 6 is provided with an N-type diffusion opening 7. An N-type impurity such as arsenic is introduced into the N-type semiconductor substrate 30 by diffusion or ion implantation, and the N-type diffusion opening 7 is masked with a resist film in the portion that will become the P-type source region 5. P such as boron in all partial areas
Type impurities are diffused or ion-implanted to a depth of approximately 0.3 to 0.5 microns.

Thereafter, P-type drain region 4. A contact hole 8 is formed in the P-type source region 5 and the substrate bias region 6,
By selectively forming a low resistance material such as aluminum, source electrode layers 12-1 to 12-5. Drain extraction electrode 10. Train electrode layers 10-1 to 10-4, source lead electrode 12, and source electrode layers 12-1 to 12-5 are formed.

In this example, the source electrode is biased to the substrate potential, and the source electrode layer 12-
3 is connected to the substrate bias region through a contact hole to make them at the same potential. With the configuration described above, the P-channel MOS transistor of this embodiment is realized. It goes without saying that in this embodiment, an N-channel MOS transistor can be easily realized by reversing the polarities of the semiconductors.

FIG. 3 is a plan view of a semiconductor chip showing a second embodiment of the present invention.

In this embodiment, the gate voltage f! The structure of the layer is such that the shape of the partial region of the element formation region partitioned by the layer is an equilateral triangle, and as a result, the gate length per unit area is longer than in the case of the first embodiment. It has the advantage of In this embodiment as well, the position of the substrate bias region 6 is arbitrary, and a regular structure is maintained regardless of the presence or absence of this region. In addition, in this example, P
Although a channel MO3) transistor is shown, an N-channel MOS transistor can also be realized by reversing the polarities of the semiconductors.

〔Effect of the invention〕

As explained above, the present invention forms the gate electrode of a MIS transistor in a lattice shape, separates the element formation region into islands with the same shape, and divides the partial regions of the element-shaped regions separated into islands into At least one of them includes a substrate bias region formed by introducing impurities of the same conductivity type as the substrate, and the existence of this substrate bias region provides a regular structure of source, drain regions, etc. around the substrate bias region. This has the effect of not impairing the stability of operation even if the drive current capacity of the M I S transistor is increased, and it is suitable for CMO3 type output phase, which requires drive current capacity and latch-up resistance. Output inverter is enabled.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor chip showing a first embodiment of the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. 1, and FIG. 3 is a semiconductor chip showing a second embodiment of the present invention. 4 and 5 are plan views of semiconductor chips showing conventional examples, respectively.・1...Field region, 2...Element formation region, 3...Gate extraction electrode, 3-1 to 3-8
．． 3-i to 3-j... Gate electrode layer, 4... Drain region, 5... Source region, 6... Substrate bias region, 7... N-type diffusion opening, 8... Contact hole, 10...Drain extraction electrode, 10-1 to 10-4
...Drain electrode layer, 11-1 to 11-7... Gate insulating film, 12... Source extraction electrode, 12-1 to 12
-5... Source electrode layer, 20... Field insulating film, 30... N-type semiconductor substrate. Well 11! I 3 houses no zubo 3 甜φ/, 4 zudo'shi inn Q castle, 3 outside/15-2 nes 4 gum yakashi 4 concave gi 5 fig.

Claims (1)

[Claims] The element-shaped region defined by the field insulating film on one principal surface of the first conductivity type semiconductor substrate is divided into a plurality of partial regions by the gate electrode layer having a lattice-like planar shape and the gate insulating film immediately below the gate electrode layer, and A plurality of source electrode layers and drain electrode layers are arranged obliquely to the gate electrode layer and arranged every other layer, and at least one of the source electrode layers is provided in at least one of the partial regions. High concentration 1st
A MIS transistor characterized in that it is connected to a substrate bias region made of a conductive type impurity region.