JP2006261437A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain an area efficiency good and increase a breakdown voltage, in a power MOSFET (Metal-Oxide Semiconductor Field Effect Transistor). <P>SOLUTION: The semiconductor device is constituted so that the minimum unit sets 30-1 to 30-4, a source region and a drain region are arrayed while being neighbored between the minimum unit sets. The minimum unit set is constituted so that a gate region 31G is a lattice shape, and source regions 32S1-32S6 and drain regions 33D1-32D5 are allotted in the gate region so that the source regions and the drain regions are arranged alternately so as to be the shape of a matrix. A back gate region 34BG1 is allotted in a specified one cell (x2, y2) in the gate region, and the gate region is removed so as not to exist in a part around the back gate region. The back gate regions are distributed with given spaces. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a power MOSFET.

  Power MOSFETs are required to have good area efficiency in order to stabilize manufacturing costs and characteristics, and to increase the withstand voltage as the controlled current is becoming large. It has been. Here, the area efficiency refers to the relationship between the output of the power MOSFET and the area on the semiconductor chip occupied by the power MOSFET, and the area efficiency is good when the area is narrow and the output is high. The breakdown voltage refers to the maximum drain voltage Vd at which the drain current Id can be kept constant.

  FIGS. 6A and 6B show a conventional N-channel power MOSFET 1. 6A is a plan view of the power MOSFET 1, and the metal wiring 10 shown in FIG. 6B is omitted for easy understanding. FIG. 6B is a cross-sectional view taken along line VIB-VIB in FIG.

  In the power MOSFET 1, polysilicon gate regions 4G are arranged in a lattice pattern in a P well region 3 of a substrate 2, and a source region 5S and a drain region 6D are X and X in an active region surrounded by the polysilicon gate region 4G. Alternatingly arranged in the Y direction, a frame-shaped back gate region 7BG is disposed outside the polysilicon gate region 4G so as to surround the polysilicon gate region 4G. .

D is a drain contact and is connected to the voltage terminal Vd. S is a source contact. G is a gate contact and is connected to the voltage terminal Vg. B is a back gate contact. The source contact S and the back gate contact B are connected to the ground terminal. 8 is a field oxide film, and 9 is a BPSG (borophosphosilicate glass) layer. Reference numeral 10 denotes a metal wiring.
Japanese Patent Application Laid-Open No. 11-307763

  Even when a high voltage Vd is applied, the potential of the P well region 3 is ideally maintained at the ground potential over the entire surface.

  However, in the power MOSFET 1 described above, since the back gate region 7BG is disposed outside the polysilicon gate region 4G, the central portion of the active region surrounded by the polysilicon gate region 4G in the P well region 3 is the back gate. When the distance from the region 7BG is long and a high voltage Vd is applied, the potential of the central portion of the active region fluctuates due to an increase in the substrate current or the like. As indicated by lines IA and IIA in FIG. 3, when the drain voltage Vd1 that is not sufficiently high is exceeded, the drain current Id increases, and there is a problem that the withstand voltage is not sufficient.

  Therefore, an object of the present invention is to provide a semiconductor device that solves the above-described problems.

In the present invention, the gate region has a lattice shape, the source region and the drain region are assigned to the cells of the gate region, the source region and the drain region are alternately arranged in a matrix, and the A back gate region is assigned to one specific cell of the gate region, and a minimum unit set that is a configuration in which the gate region is removed and does not exist for a portion around the back gate region,
The source region and the drain region are arranged adjacent to each other between adjacent minimum unit sets.

  According to the present invention, the back gate region is distributed and the well region has a back gate potential at the dispersed portion. Even when a high drain voltage is applied, the well region has no potential. A stable portion is less likely to be generated, the drain current is kept constant up to a higher drain voltage region, and the breakdown voltage increases.

  Further, since the back gate regions are arranged in a distributed manner, the back gate region surrounding the outside of the gate region which has been conventionally required is not required, and the area efficiency is improved accordingly.

  Next, an embodiment of the present invention will be described.

  1A and 1B show an N-channel power MOSFET 20 according to Embodiment 1 of the present invention. FIG. 1A is a plan view of the power MOSFET 20, and the metal wiring 35 shown in FIG. 1B is omitted for easy understanding. FIG. 1B is a cross-sectional view taken along line IB-IB in FIG.

  The power MOSFET 20 has a configuration in which, for example, four minimum unit sets 30 shown in FIGS. 2A and 2B are arranged in the P well region 22 of the substrate 21 as shown in FIG. This is a configuration in which the back gate regions 34BG1 are distributed at regular intervals.

  For convenience of explanation, first, the minimum unit set 30 will be described with reference to FIGS.

  2A is a plan view of the minimum unit set 30, and the metal wiring 35 shown in FIG. 2B is omitted for easy understanding. FIG. 2B is a cross-sectional view taken along line IIB-IIB in FIG.

  The minimum unit set 30 is a configuration in which a total of 12 cells of 4 × 3 are arranged in a matrix. One drain region is changed to a back gate region, and the four polysilicon gates in the back gate region are arranged. This is a configuration in which the area is removed, and is a horizontally long rectangle.

  Specifically, the minimum unit set 30 includes a lattice-shaped polysilicon gate region 31G, six source regions 32S1 to 32S6, five drain regions 33D1 to 32D5, and one back gate region 34BG1. The back gate region 34BG1 is shown with hatching.

  The polysilicon gate region 31G has a lattice shape, and includes a rectangular frame portion 31Ga, X-direction rail portions 31GX1 and 31GX2 extending in the X direction inside the frame portion 31Ga, and extending in the Y direction. Y direction crosspieces 31GY1, 31GY2, and 31GY3. In the polysilicon gate region 31G, a total of 12 cells of 4 × 3 in the horizontal direction represented by coordinates (x1, y1) to (x4, y3) are formed. Represents a cell in coordinates. The source regions 32S1 to 32S6 and the drain regions 33D1 to 32D5 are alternately arranged in the X direction and the Y direction, with each cell being a single source region or drain region. Source regions 32S1 to 32S6 are allocated to the cells (x2, y3), (x4, y3), (x1, y2), (x3, y2), (x2, y1), and (x4, y1), respectively. Drain regions 33D1 to 32D5 are assigned to the cells (x1, y3), (x3, y3), (x4, y2), (x1, y1), and (x3, y1), respectively.

  The cell (x2, y2) is a cell to which a drain region is assigned in the order of arrangement. The back gate region 34BG1 is allocated to the cell (x2, y2).

  An X-direction beam portion and a Y-direction beam portion are not provided in a portion around the back gate region 34BG1.

  D is a drain contact, S is a source contact, G is a gate contact, and B is a back gate contact.

  Reference numerals 35 and 36 denote metal wirings on the contacts. The metal wiring 36 extends between the back gate contact and the source contacts on both sides thereof, and connects one back gate contact and two source contacts. Reference numeral 37 denotes a BPSG film.

  In the minimum unit set 30 having the above configuration, since the back gate region 34BG1 is located in a substantially central portion of the region where the source region and the drain region are arranged in a matrix, Although the farthest part from the back gate region 34BG1 is the lower part of the source region 32S2 and the source region 32S6, the distance is extremely short.

  Next, how the minimum unit sets 30 are arranged will be described with reference to FIGS. 1 (A) and 1 (B).

  The power MOSFET 20 has a configuration in which four minimum unit sets 30-1 to 30-4 are arranged in a matrix so that a source region and a drain region are adjacent to each other between adjacent minimum unit sets.

  In the X direction, the minimum unit sets 30-1 and 30-2, and 30-3 and 30-4 are aligned. Regarding the Y direction, the minimum unit sets 30-3 and 30-4 are shifted by one cell in the X2 direction with respect to the minimum unit sets 30-1 and 30-2, respectively. The minimum unit sets 30-1 to 30-4 are arranged closely without forming a gap therebetween.

  Further, as shown in FIG. 1B, the drain contact D is connected to the voltage terminal Vd. The frame portion 31Ga of the polysilicon gate region 31G is connected to the voltage terminal Vg. The source contact S and the back gate contact B are connected to the ground terminal.

  The frame-shaped back gate region is removed and does not exist around the power MOSFET 20.

The power MOSFET 20 having the above configuration has the following features (1), (2), and (3).
(1) High breakdown voltage.

  Back gate regions 34BG1 are dispersed at regular intervals. For this reason, the P well region 22 does not have a portion far from the back gate region 34BG, and the P well region 22 has a back gate potential which is a ground potential at a dispersed portion, and a high drain voltage Vd is obtained. Even when it is applied, a portion where the potential becomes unstable does not occur in the P well region 22.

Therefore, as shown by lines I and II in FIG. 3, the characteristics of the power MOSFET 20 are such that the drain current Id is kept constant until the drain voltage Vd2 is higher than the drain voltage Vd1, and the range in which the drain current Id is kept constant. Expanding in the direction of high voltage, the power MOSFET 20 has a higher withstand voltage Vd2 than in the conventional case.
(2) Area efficiency is good.

There is no frame-shaped back gate region around it. Further, the source region and the drain region are closely arranged and have no gap. Therefore, the power MOSFET 20 has good area efficiency.
(3) The design efficiency is good.

  Since the minimum unit sets 30-1 to 30-4 are arranged in a matrix so that the source region and the drain region are adjacent between adjacent minimum unit sets, the power MOSFET 20 is efficiently designed. I can do it. Even if the required characteristics of the power MOSFET are different, the number of the minimum unit sets is determined according to the required characteristics, and the minimum unit set is adjacent to the adjacent minimum unit sets. The design is easy because they need only be arranged in a matrix.

  FIG. 4 shows an N-channel power MOSFET 20A according to Embodiment 2 of the present invention. The power MOSFET 20A has a configuration in which a minimum unit set 30 shown in FIG. 2A and another minimum unit set 40 shown in FIG. 5 are arranged in a matrix.

  The minimum unit set 40 has a configuration in which the back gate region 34BG1 in the minimum unit set 30 shown in FIG. 2A is used as a drain region, and a crosspiece is provided around the drain region.

  The minimum unit set 30 and the minimum unit set 40 are appropriately turned by 180 degrees so that the source region and the drain region are adjacent to each other between the adjacent minimum unit sets 30 and 40.

  The minimum unit sets 30-10 and 40-1 have directions changed by 180 degrees from the postures shown in FIGS. 2 (A) and 5.

  In this N-channel power MOSFET 20A, the interval between the back gate regions 34BG1 is wider than that of the N-channel power MOSFET 20, but the number of MOSFETs constituted by cells adjacent in the X and Y directions is as follows. More than the N-channel power MOSFET 20 described above. Therefore, the N-channel power MOSFET 20A has a slightly lower breakdown voltage than the N-channel power MOSFET 20, but the area efficiency is further improved.

  In each of the above embodiments, the minimum unit sets 30-1 to 30-4 may be vertically long rectangles having four cells vertically and three cells horizontally.

  The present invention can also be implemented with a P-channel power MOSFET. In this case, the back gate region is formed in one of the cells to which the drain region is assigned.

It is a figure which shows N channel power MOSFET which becomes Example 1 of this invention. It is a figure which shows the minimum unit set. FIG. 2 is a characteristic diagram of the N-channel power MOSFET of FIG. 1. It is a figure which shows N channel power MOSFET which becomes Example 2 of this invention. It is a figure which shows the minimum unit set. It is a figure which shows the conventional N channel power MOSFET.

Explanation of symbols

20, 20A N-channel power MOSFET
21 Substrate 22 P well region 30, 40 Minimum unit set 31G Polysilicon gate region 31Ga Frame portion 31GX1, 31GX2 X direction beam portion 31GY1, 31GY2, 31GY3 Y direction beam portion 32S1 to 32S6 Source region 33D1 to 32D5 Drain region 34BG1 Back gate region

Claims (5)

The gate region is grid-like,
A source region and a drain region are assigned to cells in the gate region, and the source region and the drain region are alternately arranged in a matrix,
In addition, a back gate region is assigned to a specific cell in the gate region, the back gate regions are arranged in a distributed manner,
A semiconductor device having a configuration in which the gate region is removed and does not exist in a portion around the back gate region. The gate region has a lattice shape, the source region and the drain region are assigned to the cells in the gate region, the source region and the drain region are alternately arranged in a matrix, and the gate region is specified. A back gate region is assigned to one cell of the cell, and the minimum unit set is a configuration in which the gate region is not present in a portion around the back gate region,
A semiconductor device characterized in that the source region and the drain region are arranged adjacent to each other between adjacent minimum unit sets. The semiconductor device according to claim 2,
2. The semiconductor device according to claim 1, wherein the minimum unit set is a rectangular size having four cells in one of two orthogonal directions and three cells in another direction. The gate region has a lattice shape, the source region and the drain region are assigned to the cells in the gate region, the source region and the drain region are alternately arranged in a matrix, and the gate region is specified. A back gate region is allocated to one of the cells, and a first minimum unit set having a configuration in which the gate region is removed and does not exist for a portion around the back gate region;
A second minimum unit having a configuration in which the gate region has a lattice shape, the source region and the drain region are allocated to the cells of the gate region, and the source region and the drain region are alternately arranged in a matrix Set
A semiconductor device characterized in that the source region and the drain region are alternately arranged adjacent to each other between adjacent first and second minimum unit sets. The semiconductor device according to claim 4,
Both of the minimum unit sets have a rectangular size having four cells in one of two orthogonal directions and three cells in another direction.

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