JPH10214971A - Semiconductor device, its designing method and semiconductor integrated-circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To comprehensively enhance a high-frequency characteristic such as, especially, minimum noise figure, a maximum oscillation frequency or the like in a MOSFET which is used in a device for a high-frequency signal. SOLUTION: A large number of unit cells are arranged in a matrix shape inside an active region 21 surrounded by an element isolation part 20 formed on a silicon substrate, and one MOSFET is constituted. In the respective unit cells, regular-octagon ring-shaped gate electrodes 1, drain regions 2 and source regions 3 which are formed inside and outside of the gate electrodes 1 respectively, two each of fate derivation interconnections 4 which are derived from the gate electrodes 1 and which are extended up to the element isolation part 20, substrate contact parts 5 by which a substrate face is exposed and contacts 6, 7, 8, 9 by which these respective parts and the wirings are connected electronically. Respective members such as, e.g., the ring-shaped gate electrodes 1 and the drawing gate wirings 4 are constituted so as to obtain a high-frequency characteristic which is good as much as possible.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (FET) mounted on a high-speed LSI applied to multimedia equipment and mobile communication equipment, and more particularly to a low noise figure and a high maximum oscillation frequency. Regarding the structure to be realized.

[0002]

2. Description of the Related Art In recent years, the market for multimedia devices and mobile communication devices has been steadily expanding due to an increase in consumer needs, sophistication of systems due to advances in related technologies, and development of application fields of mobile communication technologies. ing. According to the latest outlook, the market size of mobile communication services and
It is estimated that it will reach 4.5 trillion yen in 2000 and 11 trillion yen in 2010. Along with this, GH suitable for use in communication equipment, mobile radio base stations, satellite communications, broadcast stations, etc.
a transistor capable of handling a signal in a frequency band in the z region and an I
Improvements more suitable for practical use of C are expected.

Conventionally, GaAs ICs, silicon bipolar ICs, and BiCMOS LSIs have been mainly used as high frequency analog signal devices meeting these purposes. However, for example, in the mobile communication field, when considering realization of low price and low power consumption required by a user, or realization of miniaturization of a system using a single-chip analog / digital mixed LSI, analog signals are transmitted by FETs, especially MOSFETs. High-frequency LSIs that can handle digital signals will be promising options in the future.

Here, when a MOSFET is used as a high-frequency analog signal device, it has the following characteristics as compared with a bipolar transistor (hereinafter, referred to as BJT).

(1) High integration is possible Since finer processing is possible than BJT, the area occupied by transistors on a chip is small.

(2) A point having a low distortion characteristic Although the current-voltage characteristic is an exponential characteristic in BJT,
The SFET has a square characteristic. Therefore, 2f1 ± f2
, 2f2 ± f1 do not appear.

(3) High Gain and High Efficiency Points MOSFET dimensions (gate width, gate length)
High gain and high efficiency can be obtained by optimizing. As a result, the number of module stages can be reduced.
I can be reduced in size and cost.

On the other hand, when a MOSFET is used as a high-frequency analog signal device, there are many points where further improvement in characteristics is desired.

FIG. 20 is an equivalent circuit diagram showing the relationship between the characteristics of each part of the MOSFET. Hereinafter, with reference to FIG. 20, a desired improvement in characteristics of the MOSFET will be described.

(1) Improvement of transconductance gm In order to use a MOSFET as a device for high-frequency analog signals, it is necessary to increase the transconductance gm to obtain a high gain.

Here, the drain current Id of the MOSFET
Is represented by the following equation (1).

Ld = (W / 2L) · μn · Cox · (Vgs−Vt) ² (1) where μn is the electron mobility, Cox is the gate oxide film capacity per unit area, and W and L are the gates, respectively. The width and gate length, Vgs represents a gate-source voltage, and Vt represents a threshold value.

The transconductance gm is represented by the following equation (2).

Gm = dI / dV = (2 μn · Cox · Id · W / L) ^0.5 (2) As can be seen from the above equation (2), when the current Id is constant, it is necessary to increase the transconductance gm. It is necessary to increase the value of W / L, which is the ratio between the gate width and the gate length.

[0015] (2) improving the cutoff frequency f _T of the cut-off frequency f _T represents the frequency of the current gain is 1, which is one of indexes representing the frequency characteristics of the device. Then, a margin about 10 times the operating frequency is required.

Here, the cutoff frequency f _T of the FET is expressed by the following equation (3).

F _T = gm / π (Cgs + Cgd) (3) where Cgs is the gate-source capacitance and Cgd is the gate-source capacitance.
This is the capacitance between drains.

As can be seen from the above equation (3), the cutoff frequency f _T is proportional to the transconductance gm and inversely proportional to the sum of the gate-source capacitance Cgs and the gate-drain capacitance Cgd. Therefore, the cut-off frequency f _T can be improved only by reducing the gate length L,
In addition, it leads to downsizing of the system and low cost.

(3) Reduction of Noise When a MOSFET is used as a device for a high-frequency analog signal, it is necessary to reduce the noise of the FET itself so that a weak input signal is not buried in the noise.

The minimum noise figure NFmin is determined in a region where the sum (Rg + Rs) of the gate resistance Rg and the source resistance Rs is large.
It can be approximated by the following equation (4).

NFmin = 1 + 2π · f · K · Cgs√ ｛(Rg + Rs) / gm｝ (4) The above equation (4) is called Fukui's equation, and K is a constant.

As can be seen from the above equation (4), a transistor having a larger transconductance gm and a smaller gate resistance Rg / source resistance Rs has lower noise.

(4) Improvement of Maximum Oscillation Frequency fmax The maximum oscillation frequency fmax is a frequency at which the power gain becomes 1, and is expressed by the following equation (5).

[0024] _{fmax = f T / 2√ {Rg} (1 / W) · (Rds + 2π · f T · Cgd + Cgs (Ri + Rs)} (5) However, Ri is the channel resistance.

As can be seen from the above equation (5), the maximum oscillation frequency fmax increases as the gate resistance Rg and the source resistance Rs decrease. Although not represented in the above equation (5), it is also known that the maximum oscillation frequency fmax increases as the source inductance Ls decreases.

Therefore, a MOSFET arranged in a conventional high-frequency LSI employs a finger-shaped gate electrode structure in order to improve these high-frequency characteristics. FIGS. 21A to 21C are plan views schematically showing a layout of a MOSFET having such a finger-like gate electrode. That is, for example, as shown in FIG.
A large number of gate electrodes 102 are arranged in a finger shape on top,
The active regions on both sides of the gate electrode 102 are
Alternatively, it functions as the drain region 104. Each of the regions 103 and 104 has a source resistance Rs
Alternatively, a large number of contacts 106 and 107 are formed so as to reduce the drain resistance Rd, and a gate contact 105 is provided in a contact portion 102a of the gate electrode 102 extending above the element isolation 100. FIG.
(B) MOSFE in which the gate resistance Rg is further reduced by further increasing the number of fingers.
T, FIG. 21C is a plan view showing the structure of each of the MOSFETs in which the equivalent gate resistance Rg is reduced by providing contact portions 102 a at both ends of the gate electrode 102.

As shown in FIG. 22, the minimum noise figure NFmin increases as the gate finger length in one unit cell increases. Therefore, in the MOSFET having the shape as shown in FIG. 21B, the minimum noise figure N is obtained by increasing the number of fingers while keeping the total gate width almost constant.
It tries to reduce Fmin.

Further, in the structure shown in FIGS. 21A to 21C, a salicide process in which the gate resistance Rg, the source resistance Rs and the drain resistance Rd can be simultaneously reduced, or only the gate resistance Rg is reduced. The polycide process has also been applied conventionally.

On the other hand, as a device having both high-speed operation and low power consumption required for a high-frequency semiconductor device, S
CMOS devices having an OI (Silicon-On-Insulator) structure have attracted attention.

FIG. 23 is a sectional view of a conventional SOI-MOSFET having a buried oxide film. As shown in the figure, a buried oxide film 112 is provided at a position at a predetermined depth from the upper surface of the silicon substrate 111, and the upper part of the buried oxide film 112 is an active region (semiconductor region). A gate oxide film 117 is formed on the active region.
And an active region located on both sides of the gate electrode 118 are doped with high-concentration impurities to form a source region 113 and a drain region 114.
Are formed. The active region below the gate electrode 118, that is, the region between the source region 113 and the drain region 114, has a conductivity type opposite to that of the impurities in the source region 113 and the drain region and has a threshold control level concentration. The impurity has been introduced, and this region becomes a channel region 115.

In such an SOI structure, the diffusion layer through which the current flows in the active region is separated from the silicon substrate 111 by the buried oxide film 112 which is an insulator. The capacitance between the diffusion layer and the silicon substrate 111 is significantly reduced. Therefore, the MOS device formed on the SOI substrate has a small parasitic capacitance, so that both high-speed operation and low power consumption can be achieved, and has the following excellent characteristics that cannot be obtained with a bulk MOS device.

First, since the substrate bias effect is small, it can be easily operated at a low voltage. Second
In addition, since the parasitic capacitance is small, high-speed operation can be performed at a low voltage according to a high-frequency signal. Third, reliability is high because defects such as radiation are less likely to occur and soft errors are less likely to occur. Fourth, a highly integrated device having a simple structure can be realized by a simple process.

Here, in a MOSFET having a thin film SOI structure in which a buried oxide film is provided on a semiconductor substrate, a fully depleted mode (FD) in which a Si layer in a channel portion is completely depleted during operation of the transistor. Two operation modes of a partially depleted mode (PD: Partially Depleted) in which a region that is not depleted remains in the SOI substrate become possible. Here, in either mode, the SOI
The floating effect of the substrate, which is a problem for practical use of the device, will be considered.

The structure of an SOI transistor differs greatly from that of a bulk transistor in that the channel portion is floating and the substrate potential cannot be fixed. The biggest problem caused by the substrate floating effect is a decrease in the breakdown voltage between the source and the drain. This is because the holes generated by the impact ionization phenomenon in the high electric field region near the drain region 114 shown in FIG. 23 accumulate below the channel region 115 and raise the potential of the channel region 115, so that the parasitic bipolar transistor operates. It is caused by doing.

Various measures have been taken to suppress the parasitic bipolar transistor effect, but the most reliable method is to fix the substrate potential (so-called body contact) as in the bulk device. FIG.
(A) to (c) show typical body fixing methods, respectively. FIG. 24A shows a method called an H-type gate method, in which the active region is extracted from below the gate electrode 118 on the side of the channel region, thereby fixing the potential of the channel region. FIG. 24B shows a method called a source tie method in which a P + region is formed in a source region 113, which is an N + region of an NMOS transistor, and holes generated are collected in the P + region to reduce a substrate potential. It is a method to prevent the rise. FIG. 24C shows a method called a field shield method, in which a field shield electrode is formed separately from the original gate electrode 118 to separate transistors adjacent to each other, and holes are removed from a separation portion below the field shield electrode. It is a method of pulling out.

[0036]

However, finger-type MOSFETs used as the above-mentioned conventional high-frequency analog signal devices have the following problems.

(1) Decrease in maximum oscillation frequency fmax due to increase in source inductance When the number of gate fingers is increased as shown in FIG. The wiring to the drain region and the source region also becomes finger-like, and the inductance of each increases due to the wiring. As described above, since the maximum oscillation frequency fmax is inversely proportional to the source inductance, an increase in the number of fingers leads to a decrease in the maximum oscillation frequency fmax. Therefore, it is difficult to improve the minimum noise figure NFmin in a higher frequency region.

(2) If the number of fingers is increased to achieve low noise, it is impossible to avoid an increase in the occupied area of the active region of the semiconductor device.

(3) Increase in cost by applying a process for lowering the resistance of the gate electrode, etc. If a polycide process or a salicide process is employed to lower the resistance of the gate electrode, etc., the number of steps inevitably increases. Therefore, the manufacturing cost is increased, and the LSI unit price is higher than that of the standard process.

(4) Problems in System LSI When a high-frequency system LSI in which a plurality of circuits having various functions are formed on a common substrate is to be constructed,
If the noise of some circuits is large, the influence on other circuits becomes high, and the above-mentioned problems become remarkable. For this reason, it is difficult to integrate a circuit particularly requiring low noise, and a high-frequency system L in which all circuits are integrated into one chip.
This is a factor that hinders the realization of SI.

(5) Problems in SOI Structure In the conventional body contact methods shown in FIGS. 24A to 24C, the pattern area is increased, the existence of the channel width dependence of the hole extraction effect, the current There is a problem that the flowing direction is limited.

A first object of the present invention is to provide a semiconductor device which has a low-cost MOSFET structure while realizing low noise even in an extremely high frequency range.

A second object of the present invention is to provide a semiconductor device having a structure suitable for use as a high-frequency semiconductor device, having a simplified structure with a regular arrangement, occupying as little active area as possible, and having a low manufacturing cost. An object of the present invention is to provide an apparatus and a design method thereof.

A third object of the present invention is to realize a semiconductor device suitable for a low-noise circuit required for a high-frequency system LSI with a MOSFET structure, thereby realizing various types of circuits used in a high-frequency region. It is an object of the present invention to provide a one-chip semiconductor integrated circuit device.

A fourth object of the present invention is to provide a high-performance SOI device having both high-speed operation and low power consumption in a high-frequency range applied to multimedia equipment and mobile communication equipment.
-To provide a semiconductor device suitable for an LSI.

[0046]

In order to achieve the first object, the present invention provides means relating to the first semiconductor device according to the present invention.

According to a first aspect of the present invention, there is provided a semiconductor device having a unit cell formed in an active region surrounded by element isolation on a semiconductor substrate and functioning as a high-frequency signal FET. The device, wherein the unit cell includes a ring-shaped gate electrode formed on the active region, a drain region formed in a region inside the gate electrode in the active region, and the drain region. A drain contact formed on the source region, a source region formed in a region of the active region outside the gate electrode, a source contact formed on the source region, and a connection to the gate electrode. A gate lead-out line extending from above the source region to above the element isolation; and a gate contact formed on the gate lead-out line. Provided, each member within the unit cell is formed to provide best possible frequency characteristics.

As a result, the current flows radially from the drain region to the source region during the operation of the FET, so that the source resistance is greatly reduced. Therefore, it is possible to reduce the minimum noise figure NFmin represented by the equation (4). Moreover, in an FET having a finger type gate electrode, it is necessary to make the gate electrode offset to the drain side in order to ensure a low source resistance and a high drain withstand voltage. Is formed, there is a limitation in reducing the width of the drain region, that is, the area of the drain region. On the other hand, in such a ring-shaped gate electrode structure, it is easy to form a small drain region for forming a drain contact inside the ring-shaped gate electrode. Therefore, the source resistance can be significantly reduced while the drain withstand voltage is maintained high, and the low noise property required for the high-frequency signal FET can be secured.

In the first aspect, the gate electrode is the second aspect.
The element may be formed in a closed ring shape as described in (1) or in an open ring shape which is split in at least one place as described in (3). Good.

According to a fourth aspect of the present invention, in any one of the first to third aspects, it is preferable that the gate lead-out wiring is configured to reduce a parasitic component that deteriorates high-frequency characteristics. .

According to a fifth aspect of the present invention, in the fourth aspect, the gate lead-out wiring is configured such that a gate resistance that changes depending on the number and shape of the wirings provides as good a high-frequency characteristic as possible. Is preferred.

According to a sixth aspect of the present invention, in any one of the first to fifth aspects, the gate lead-out line is formed by a gate which varies depending on the number and shape thereof.
It is preferable that the source-to-source capacitance is configured to give as good a high-frequency characteristic as possible.

According to the fourth, fifth or sixth aspect, high frequency characteristics can be obtained by reducing the gate resistance without using the salicide process. Thus, while suppressing the manufacturing cost, to reduce the minimum noise figure NFmin represented by improving the high frequency characteristics of the high frequency signal for FET, particularly improved and expressions cutoff frequency f _T of the formula (3) (4) It becomes possible.

According to a seventh aspect of the present invention, in any one of the first to sixth aspects, the length of the ring-shaped gate electrode in the circumferential direction can be changed so that the drain contact can be formed in the drain region. It is preferable to minimize it within a proper range.

As a result, it is possible to minimize the minimum noise coefficient NFmin which increases as the length of the ring-shaped gate electrode in each unit cell in the circumferential direction increases.

As set forth in claim 8, in any one of claims 1 to 7, the source contact may be configured such that the source resistance determined by the number and shape thereof is as small as possible. preferable.

As a result, the minimum noise figure NFmin represented by the equation (4) is reduced, and the maximum oscillation frequency fmax represented by the equation (5) is increased.

As described in claim 9, in claim 8, it is preferable that at least a connection portion between the source region and the source contact is made of silicide.

As a result, the source contact resistance and the sheet resistance of the source region are reduced, so that the source resistance can be kept low even if the number of source contacts is reduced and the area of the source region is reduced. Therefore,
Excellent high-frequency characteristics can be obtained while reducing the area of the FET.

According to a tenth aspect, in any one of the first to ninth aspects, the width of the source region corresponding to the distance between the ring-shaped gate electrode and the element isolation is set to: It is preferable that a region located below the gate lead-out line is configured to be smaller than other regions.

As a result, the gate-source capacitance of the FET is reduced, so that the maximum oscillation frequency fmax represented by the equation (5) is improved.

According to the eleventh aspect, in any one of the first to tenth aspects, it is preferable that the area of the gate lead-out wiring on the element isolation is as large as possible.

As a result, the resistance of the gate lead-out line is reduced, so that the gate resistance is reduced. Therefore, the minimum noise figure NFmin represented by the equation (4) can be reduced.

According to a twelfth aspect of the present invention, in any one of the first to eleventh aspects, the plurality of gate contacts are provided for one region on the element isolation in the gate lead-out wiring. One can be provided.

As a result, the gate contact resistance decreases as the number of gate contacts increases, so that the gate resistance decreases. Therefore, the minimum noise figure NFmin represented by the equation (4) can be further reduced.

According to a thirteenth aspect, in any one of the first to twelfth aspects, each of the members in the unit cell is regularly formed on the main surface of the semiconductor substrate. Is preferred.

As a result, it is possible to reduce the length of the ring-shaped gate in the unit cell in the circumferential direction while securing the required total gate width, and to reduce the minimum noise figure NFmin by reducing the gate resistance. it can.

According to a fourteenth aspect, in any one of the first to thirteenth aspects, at least the gate electrode, the gate lead-out line, the source region and the drain region in each of the unit cells are formed of the semiconductor. It is preferable that the ring-shaped gate electrode is formed on the main surface of the substrate so as to be rotationally symmetric with respect to the center point of the ring-shaped gate electrode.

Thus, it becomes possible to form one FET by arranging the unit cells regularly. Therefore, the entire FET is compact, and the regular arrangement also simplifies the wiring structure, thereby reducing the manufacturing cost.

The gate electrode according to any one of the first to fourteenth aspects may be, for example, a quadrangular ring shape having an angle between sides of 90 degrees as described in the fifteenth aspect. As described in No. 16, an octagonal ring shape having an angle between sides of 135 degrees can be considered.

As described in claim 17, in any one of claims 1 to 16, it is preferable that the semiconductor substrate is a silicon-based substrate.

As a result, the cost of the semiconductor device can be greatly reduced as compared with the case of using a compound semiconductor substrate, and a device having characteristics practically inferior to a high-frequency device using a compound semiconductor can be obtained. it can.

In order to achieve the above-mentioned second object, the present invention employs means relating to the second semiconductor device according to claims 18 to 27.

According to a second aspect of the present invention, there is provided a semiconductor device comprising:
A semiconductor device having a plurality of unit cells formed in an active region surrounded by element isolation on a semiconductor substrate, wherein each of the unit cells is formed on the active region. A ring-shaped gate electrode; a drain region formed in a region inside the gate electrode in the active region; a drain contact formed on the drain region; and a drain contact formed in the active region. A source region formed in an outer region, a source contact formed on the source region, a gate lead-out line connected to the gate electrode, extending from the source region to the element isolation, A gate contact formed on a gate lead-out line, wherein each member in each of the unit cells includes a plurality of units in the active region. Toseru has a regular shape so as to be regularly arranged.

As a result, each unit cell is regularly arranged with the occupation area of the entire FET as small as possible. Then, a structure in which a wiring for connecting each of the gate contact, the drain contact, the source contact, and the substrate contact can be obtained by a simple repetitive wiring.

According to a nineteenth aspect, in the eighteenth aspect, at least the gate electrode, the gate lead-out line, the source region, and the drain region in each of the unit cells are formed on the main surface of the semiconductor substrate by the ring. It can be formed to be rotationally symmetric with respect to the center point of the gate electrode.

According to a twentieth aspect, in the eighteenth aspect, the shape of each of the members in one unit cell of the plurality of unit cells and the shape of the one member are determined.
It may be formed so that the shape of each member in another unit cell adjacent to one unit cell is line-symmetric.

The gate electrode according to any one of claims 18 to 20 may have a quadrangular ring shape in which the angle between the sides is 90 degrees, for example, as described in claim 21. As described in No. 22, an octagonal ring shape with an angle between each side of 135 degrees can be considered.

According to a twenty-third aspect, in any one of the eighteenth to twenty-second aspects, each member of each unit cell is formed so as to give as good a high-frequency characteristic as possible. Is preferred.

According to a twenty-fourth aspect of the present invention, in the twenty-third aspect, a source contact wiring connecting the tips of the source contacts is further provided, and the source contact wiring is formed in the first layer by the drain contact. In addition, it can be formed over the entire region except the region where the gate contact is formed and its periphery.

As a result, the source contact wiring is formed over almost the entire surface, so that the source inductance becomes extremely small and the maximum oscillation frequency fmax becomes large.

According to a twenty-fifth aspect, in the twenty-third aspect, a substrate contact portion formed on a part of the active region; a substrate contact formed on the substrate contact portion; The semiconductor device may further include a source contact wiring and a substrate contact wiring for connecting the tips of the source contact and the substrate contact.

As a result, since the source inductance can be further reduced, a structure suitable for a device requiring a particularly high maximum cutoff frequency fmax can be obtained.

According to a twenty-sixth aspect, in the twenty-third aspect, a substrate contact portion provided only in a unit cell arranged in a peripheral portion among the unit cells in the active region; The semiconductor device may further include a substrate contact formed on the portion, and a substrate contact wiring connecting the tips of the substrate contacts.

As a result, the wiring can be simplified.

As described in claim 27, in any one of claims 23 to 26, the semiconductor substrate is preferably a silicon-based substrate.

As a result, the cost of the semiconductor device can be greatly reduced as compared with the case of using a compound semiconductor substrate, and a device having characteristics practically inferior to a high-frequency device using a compound semiconductor can be obtained. it can.

In order to achieve the third object, in the present invention, means relating to the third semiconductor device described in claims 28 to 33 is provided.

A third semiconductor device according to the present invention is a semiconductor device according to claim 28.
As described in the above, on an insulating portion of the substrate, a semiconductor region, an element isolation surrounding the semiconductor region, a semiconductor device including a unit cell, wherein the unit cell,
A ring-shaped gate electrode formed on the semiconductor region, a channel region including a low-concentration first-conductivity-type impurity formed in a region of the semiconductor region below the ring-shaped gate electrode, and the semiconductor region And a drain region formed in a region inside the gate electrode and containing a high concentration of the second conductivity type impurity, and a high concentration second region formed in a region outside the gate electrode in the semiconductor region. A source region containing a conductivity type impurity, a gate lead-out line connected to the gate electrode and extending from above the source region to above the element isolation, and a high concentration first conductivity type impurity formed in a part of the semiconductor region. And a substrate contact portion.

Thus, even when a large number of unit cells are arranged in the active region, a substrate contact portion is provided for each unit cell, so that a substrate contact portion is provided for each unit cell. The substrate potential can be fixed by utilizing this, and the operation of the parasitic bipolar transistor can be suppressed as much as possible. In addition, since the ring-shaped gate electrode is provided, there is no edge transistor generated near the boundary between the finger-type gate electrode and the element isolation. Therefore, an SOI transistor having stable electric characteristics without a parallel transistor phenomenon is provided. can get. Furthermore, the area of the source region is a normal FET
Therefore, even when the semiconductor region on the insulating portion is thinner, the source resistance can be reduced as compared with the conventional SOI transistor.

According to a twenty-ninth aspect, in the twenty-eighth aspect, the substrate contact portion is provided outside the source region, and is connected to the gate electrode and extends from the source region to the substrate contact portion. An extended carrier lead-out line and a carrier lead-out region formed in a region of the semiconductor region below the carrier lead-out line and containing a low-concentration first conductivity type impurity can be further provided.

As a result, in each unit cell, carriers generated by impact ionization in the channel region are easily discharged from the carrier lead-out region to the substrate contact portion, so that the potential of the channel region is fixed to generate the parasitic bipolar transistor. Can be effectively suppressed.

According to a twenty-third aspect, in the twenty-eighth aspect, the substrate contact portion is formed so as to extend from the channel region to the outside of the source region by dividing the source region. it can.

As a result, in each unit cell, the carriers generated by the impact ionization in the channel region are more easily discharged directly to the substrate contact portion, so that the potential of the channel region is fixed and the generation of the parasitic bipolar transistor is prevented. It can be suppressed effectively.

The gate electrode according to any one of claims 28 to 30 may have a closed ring shape as described in claim 31, or may have at least one of the gate electrodes described in claim 32. An element isolation may be interposed in the above-mentioned divided region as an open ring divided at several places.

As described in claim 33, in any one of claims 28 to 32, it is preferable that each member in the unit cell is formed so as to give as good a high-frequency characteristic as possible.

In order to achieve the second object, the present invention provides means for designing a semiconductor device according to the present invention.

According to a third aspect of the present invention, there is provided a method of designing a semiconductor device having a plurality of unit cells each having a regular shape and formed on a common semiconductor substrate. Forming a shape of the one unit cell using layout data of any one of the plurality of unit cells, and then using the layout data of the one unit cell to form the shape of the one unit cell. This is a method of forming the shape of another unit cell adjacent to one unit cell.

According to this method, a regular shape of each unit cell in the semiconductor device can be easily and quickly formed, and a highly integrated semiconductor device can be stably manufactured at low manufacturing cost. .

According to a thirty-fifth aspect, in the thirty-fourth aspect, when the shape of the another unit cell is formed, the layout data of the one unit cell is inverted, or the layout data is inverted and translated. Can be performed.

According to a thirty-sixth aspect, in the thirty-fourth aspect, when forming the shape of the another unit cell, the layout data of the one unit cell is rotationally moved or rotated on a plane. A combination of movement and translation can also be performed.

According to a thirty-seventh aspect, in any one of the thirty-fourth to thirty-sixth aspects, each of the unit cells is formed on an active region of the semiconductor substrate surrounded by element isolation. A ring-shaped gate electrode, a drain region formed in a region inside the gate electrode in the active region, and a source region formed in a region outside the gate electrode in the active region. It is preferable that the semiconductor device further includes a gate lead-out line connected to the gate electrode and extending from above the source region to above the element isolation.

According to this method, the high degree of symmetry of the ring-shaped gate electrode increases the degree of freedom when using layout data. For example, a method in which layout data of one unit cell is rotated and moved around a drain region inside a ring-shaped gate electrode to obtain layout data of another unit cell can be easily implemented.

According to a thirty-eighth aspect, in any one of the thirty-fourth to thirty-seventh aspects, it is preferable that each member in the unit cell is formed so as to give as good a high-frequency characteristic as possible. .

According to this method, a semiconductor device having a high-frequency characteristic having the above-mentioned ring-shaped gate electrode can be formed quickly and easily.

In order to achieve the fourth object, in the present invention, means relating to the semiconductor integrated circuit device according to claims 39 to 41 are provided.

The semiconductor integrated circuit device according to the present invention is as follows.
As described in 9, a semiconductor integrated circuit device provided with a plurality of circuits formed on a common semiconductor substrate and having different functions, wherein at least one of the plurality of circuits is An element isolation formed to surround a region to be an active region of the semiconductor substrate; a ring-shaped gate electrode formed on the active region; and a region in the active region to be inside the gate electrode. A drain region formed, a source region formed in a region of the active region outside the gate electrode, and a gate lead-out line connected to the gate electrode and extending from above the source region to above the element isolation. And each member in the unit cell is formed so as to give as good a high-frequency characteristic as possible.

As a result, any one or more of a plurality of circuits formed on a common substrate can be constituted by an FET having a ring-shaped gate electrode structure having excellent high-frequency characteristics. For example, by configuring a circuit requiring high low noise as described above with an FET having a ring-shaped gate electrode structure, it is possible to obtain an advantageous effect that an adverse effect on other circuits provided on the same substrate can be avoided. . Also, by utilizing the high cut-off frequency characteristic of the ring-shaped gate electrode structure FET, a circuit particularly used in a high frequency region is used for the FET having the ring-shaped gate electrode structure.
Can also be configured. And, as mentioned above,
An FET having a ring-shaped gate electrode structure can exhibit excellent high-frequency characteristics without using a compound semiconductor substrate, so that many circuits of a semiconductor integrated circuit device used in a high-frequency region can be accommodated in one chip, The size and cost of the integrated circuit device can be reduced.

According to a forty-third aspect, in the thirty-ninth aspect, a circuit other than the at least one of the plurality of circuits surrounds a region to be an active region of the semiconductor substrate. Element isolation formed in
A unit cell having a linear gate electrode formed on the active region and source / drain regions formed in regions of the active region on both sides of the gate electrode may be provided.

Accordingly, taking into account that the FET having the ring-shaped gate electrode structure often occupies a larger area than the FET having the finger type gate electrode structure, the occupied area of the entire semiconductor integrated circuit device is reduced. Can be reduced.

According to a forty-first aspect, when the semiconductor integrated circuit device is an LSI for a cellular phone, the at least one circuit is a low-noise amplifier. Is preferred.

[0112]

Embodiments of the present invention will be described below.

(First Embodiment) FIG. 1 is a plan view schematically showing a layout in a unit cell of a MOSFET according to a first embodiment. FIG. FIG. 16 is a plan view illustrating a unit cell structure according to the present embodiment as an example to show the cell array structure of the MOSFET according to the fifth embodiment.

As shown in FIG. 6, an active region 21 is formed in a region surrounded by element isolation on a silicon substrate, and a large number of unit cells are provided in the active region 21. In FIG. 1, only one unit cell is shown. On the silicon substrate in the active region 21, a regular octagonal ring-shaped gate electrode 1 is provided via a gate oxide film (not shown). The region inside the gate electrode 1 in the active region 21 is the drain region 2, and the region outside the gate electrode 1 is the source region 3.
And a high concentration impurity of the same conductivity type is introduced into the drain region 2 and the source region 3 in the substrate contact portion 5. A region below the gate electrode 1 (that is, below the gate oxide film) has a conductivity type opposite to that of the impurities in the source region 3 and the drain region 2 and is a channel region into which impurities having a threshold control level are introduced. It has become. The substrate contact portion 5 has the same conductivity type as that of the impurity in the channel region.
A high-concentration impurity of a conductivity type opposite to that of the impurity inside is introduced. Further, two gate lead-out lines 4 are led out of two opposing sides of each of the sides of the octagon forming the ring-shaped gate electrode 1, and the gate lead-out lines 4 are connected to the source region in the active region 21. After extending over the element isolation 3 and over the element isolation, a contact portion 4a for signal connection with an upper wiring is provided at the end thereof. Although not shown, a gate oxide film made of a silicon oxide film is also interposed between the gate lead-out line 4 and the silicon substrate. However, a gate insulating film made of a silicon nitride film or a silicon oxynitride film may be used instead of the silicon oxide film.

Then, from the upper wiring, the MOSFET
There is provided a contact for making an electrical connection to each part in the inside. One gate contact 6 is provided for each of the two contact portions 4a of the gate lead-out line 4, one drain contact 7 is provided at the center of the drain region 2, and a total of six source contacts 8 are provided for the source region 3. One substrate contact 9 is provided in each of the two substrate contact portions 5.

According to the structure of one unit cell of the MOSFET of this embodiment, the drain region 2 is connected to one drain contact 7 by the regular octagonal ring-shaped gate electrode 2.
Is small enough to be able to be drawn out, so that the circumferential length of the ring-shaped gate electrode 1 can be made as short as possible. Moreover, since the gate lead-out wiring 4 is drawn out from two places of the ring-shaped gate electrode 1 and two gate contacts 6 are provided, the gate resistance Rg can be reduced. That is, by making the circumferential length of the ring-shaped gate electrode 1 as small as possible,
The minimum noise figure NFmin can be reduced as in the case where the finger length of the conventional MOSFET having the finger-shaped gate electrode shown in FIGS. 21A to 21C is short.

Further, one source contact 8 is arranged at 45 ° intervals surrounding the ring-shaped gate electrode 1,
Since six source contacts 8 are provided per unit cell, the source resistance Rs is reduced. A conventional MOSFET having a finger-shaped gate electrode (FIG. 21)
In (a) to (c)), since the region 104 between the gates serving as the source regions is shared by the two finger-shaped gate electrodes, the source contact resistance increases. However, in the case of the configuration of the present embodiment, the source contact 8 is arranged in a circular shape around the gate electrode 1 and, moreover,
Since the source contact 8 is not shared with another gate electrode, the contact resistance of the source region 3 is small.
Further, the inside of the ring-shaped gate electrode 1 is
And the outside is the source region 3, the source region 3
The current flows radially between the drain region 2 without bias. Since the current flows radially and the source region 3 is wide, the source resistance Rs becomes extremely small.

As a result, the gate resistance Rg and the source resistance Rs can be reduced in the MOSFET according to the present embodiment in which a plurality of unit cells are regularly arranged. And the minimum noise figure N
Fmin can be effectively reduced.

Further, since such a small source resistance can be realized, the resistance can be sufficiently reduced without applying a salicide process for greatly reducing the gate resistance, the source resistance and the drain resistance. . That is, a high-frequency signal having a low minimum noise figure NFmin similar to the high-frequency signal device formed by the salicide process at a low cost without increasing the manufacturing cost due to an increase in the number of steps as in the case of employing the salicide process. Forming a device for use.

Next, the structure of a MOSFET constituted by arranging the unit cells in a matrix will be described. FIG. 6 is a plan view schematically showing a layout of MOSFETs configured by arranging the unit cells of the present embodiment in a matrix. In the active region 21 surrounded by the element isolation 20, four unit cells in each of the vertical and horizontal directions, that is, a total of 16 unit cells are arranged. The number of the unit cells is determined by the gate width W required for the characteristics of the MOSFET.
Determined by In the active region 21, element isolation for arranging the gate contact portion 4a is discretely present.

The MOSFET of the present embodiment has a structure in which one unit cell has a two-rotation symmetry around the center point of the ring-shaped gate electrode 1 (that is, the center point of the drain region 2). Each unit cell is arranged in a matrix without causing
It becomes easy to configure T. To obtain the required gate width, it is only necessary to add units. This will be described below.

In forming the cell array structure as shown in FIG. 6, if there is layout data of one unit cell, layout data of another unit cell is easily and quickly generated using the layout data. be able to. For example, when the layout data of the unit cell at the upper end on the right side of FIG. 6 is rotated 180 degrees around the drain contact 7 and then translated, the layout data of the lower unit cell adjacent to this unit cell is obtained. Can be When the layout data of the unit cell at the upper end on the right side of FIG. 6 is folded back (reversed) by a line connecting the centers of the lower substrate contact 9 and the gate contact 6, the lower unit adjacent to this unit cell is turned over. The cell layout data is obtained. Further, FIG.
When the layout data of the unit cell at the upper end on the right side is rotated by 90 degrees around the lower left gate contact 6, the layout data of the lower unit cell adjacent to this unit cell is obtained. Similarly, according to the symmetry of the unit cell, the rotational movement of the layout data,
Reverse movement, combination of rotation movement and parallel movement, combination of reverse movement and parallel movement, combination of rotation movement and reverse movement,
Alternatively, layout data of another unit cell can be easily generated by performing any one of the combination of the rotation movement, the inversion movement, and the parallel movement. Such use of the layout data of one unit cell can be similarly applied to other embodiments described later. At this time, the substrate contact portion 5, the substrate contact 9, the island-shaped element isolation 20, the gate contact portion 4a, and the gate contact 6 are shared by all four unit cells (four unit cells in this embodiment). become.

Each member of the unit cell of the present invention does not need to be symmetrical with respect to the center point of the ring-shaped gate electrode 1, but may be tertiary or higher. However, if the rotational symmetry is too high, the degree of freedom is rather narrowed. Therefore, it is preferable that the rotational symmetry be at most 6 or less. This can be similarly applied to the following embodiments.

(Second Embodiment) FIG. 2 is a plan view schematically showing a layout of one unit cell of a MOSFET according to a second embodiment. MOSFE of this embodiment
T has a regular octagonal ring-shaped gate electrode 1, a drain region 2 is provided inside the gate electrode 1, and a source region 3 is provided outside the gate electrode 1. The MOSFET of the first embodiment has the same structure as that of the MOSFET of the first embodiment, but has a structure in which the source region 3 (active region) is narrowed below the gate lead-out line 4.
And different. That is, in the region R4 below the gate lead-out line 4, the element isolation portion is closer to the gate electrode 1, and the distance between the element isolation portion and the gate electrode 1 is short.

According to the MOSFET of this embodiment,
By reducing the area of the source region 3 below the gate lead-out line 4, the gate-source capacitance Cgs is reduced. On the other hand, as shown in the above equation (3), the cutoff frequency f _{T of the} MOSFET
It is inversely proportional to the sum of the source capacitance Cgs and the gate-drain capacitance Cgd. Therefore, in the present embodiment, in particular gate - by reducing source capacitance Cgs, it is possible to realize a MOSFET having a high cut-off frequency f _T.

(Third Embodiment) FIG. 3 is a plan view schematically showing a layout of one unit cell of a MOSFET according to a third embodiment. MOSFE of this embodiment
T has a regular octagonal ring-shaped gate electrode 1, a drain region 2 provided inside the gate electrode 1, a source region 3 provided outside the gate electrode 1, and a source region provided below the gate lead-out line 4. 3 (active region) has the same structure as the MOSFET of the second embodiment, but the gate contact portion 4a is made as wide as possible.
As a result, the point that the gate lead-out line 4 between the gate electrode 1 and the gate contact part 4a is extremely short is different from the MOSFET of the second embodiment.

According to the MOSFET of this embodiment, the gate contact portion 4a is expanded to a portion where the source region 3 is narrowed down by isolating the element closer to the gate electrode 1, and the gate lead-out wiring 4 is shortened. Can be made particularly small. That is, as can be seen from the above equation (4), a MOSFET having a low minimum noise figure NFmin can be obtained.

In the structure of the MOSFET shown in FIG. 3, only one gate contact 6 is provided in one gate contact portion 4a. However, since the gate contact portion 4a is expanded in this manner, one gate contact portion is formed. It is easy to provide several gate contacts in the contact portion 4a, so that the gate resistance Rg can be further reduced and the high frequency characteristics can be improved.

(Fourth Embodiment) FIG. 4 is a plan view schematically showing a layout of one unit cell of a MOSFET according to a fourth embodiment. In the present embodiment, a structure of a MOSFET particularly when a salicide process is applied is shown. The MOSFET of this embodiment has a regular octagonal ring-shaped gate electrode 1, and has a drain region 2 inside the gate electrode 1 and a source region 3 outside the gate electrode 1. MOSFE of first to third embodiments
It has the same structure as T. However, the MOSF of the present embodiment
ET has only one source contact 8 at each of two positions that are symmetric about two rotations with respect to the center point of the gate electrode 1.
Only have.

Since the MOSFET of this embodiment is formed by a salicide process, the manufacturing cost is higher than that of the MOSFETs of the first to third embodiments.
However, by adopting such a structure suitable for the salicide process, the number of source contacts 8 can be made much smaller than in a normal process, so that the occupied area of the source region 3 can be made extremely small. Therefore, the source resistance R is as small as that of the first to third embodiments.
It is possible to obtain a MOSFET having an extremely small occupation area while having s and the gate resistance Rg.

(Fifth Embodiment) FIG. 5 is a plan view schematically showing a layout of one unit cell of a MOSFET according to a fifth embodiment. MOSFE of this embodiment
T has a regular quadrangular ring-shaped gate electrode 1 in an active region 21 surrounded by element isolation.
The fourth embodiment is different from the MOSFETs of the first to third embodiments in that the gate lead-out lines 4 are led out of the four locations and the gate contact portions 4a are provided at the four locations on the element isolation. The point that the inside of the gate electrode 1 is the drain region 2 and the outside of the gate electrode 1 is the source region 3, the gate contact portion 4 a, the drain region 2 and the source region 3
Further, the point that contacts 6, 7, and 8 are provided are the same as the MOSFETs of the first to third embodiments. The point that the source region 4 is reduced below the gate lead-out line 4 is the same as the MOSFET of the second embodiment.

The MOSFET according to this embodiment is basically
The same effect as the MOSFET of the second embodiment can be exerted. In addition, the MOSFET of the present embodiment
Has the gate lead-out wiring 4 connected to the four positions of the gate electrode 1, and therefore has an advantage that the gate resistance Rg can be further reduced.

Note that the MOSFET constituted by arranging a plurality of unit cells in the second to fifth embodiments is arranged.
Although the illustration and description of the overall layout of the first embodiment are omitted, the MOSFE in the first embodiment shown in FIG.
Similar to T, a layout in which the unit cells are arranged in a matrix can be employed.

However, in the present invention, each unit cell does not need to be arranged in a matrix. For example, a regular triangular ring-shaped gate is provided, and the members in each unit cell are positioned three times with respect to the center point of the ring-shaped gate. If each unit cell is regularly arranged, such as being formed to be rotationally symmetric and each unit cell being arranged in a honeycomb shape,
The arrangement and wiring can be facilitated, and the occupied area can be reduced.

(Sixth Embodiment) Sixth Embodiment In each of the following embodiments, an embodiment relating to a wiring structure will be described. For convenience, the structure of the MOSFET according to the first embodiment (see FIG. 6) will be described. The case where wiring is performed will be described as an example.

FIG. 7 is a plan view schematically showing a wiring layout according to the sixth embodiment, and FIG. 8 is a VIII diagram shown in FIG.
FIGS. 8A and 8B are cross-sectional views of the semiconductor device taken along line VIII, each showing a structure in which wiring is added to the MOSFET shown in FIG. 6. However, in FIG. 7, the first layer wiring is not shown in order to avoid a complicated figure. As shown in FIG. 7 and FIG.
The source contact wiring 15 connects between them, and the source contact wiring 15 is formed almost in a solid state in a wide area excluding the formation area of the drain contact 7, the gate contact 6 and the substrate contact 9 in the drawing. Drain contact wirings 10a to 10d connecting between the drain contacts 7 of each unit cell are provided as a second layer wiring, and gate contact wirings 11a to 11c connecting between the gate contacts 6 are provided as a third layer wiring. And substrate contact wirings 12a and 12b (not shown in the cross-sectional view of FIG. 8) connecting between the substrate contacts 9 are provided alternately in a direction inclined by 45 degrees with respect to the second-layer wiring. . However, the first to third interlayer insulating films are interposed between the substrate surface and the first-layer wiring and between the wiring of each layer and the wiring thereon.

According to the wiring structure of the MOSFET of the present embodiment, the source contact wiring 15 is formed in a wide area almost solid, so that the source inductance Ls is reduced. Although not appearing in the equation (5), it is known that the maximum oscillation frequency fmax is improved when the source inductance is reduced as described above. Therefore, according to the MOSFET of the present embodiment, the maximum oscillation frequency fma
It is possible to obtain a MOSFET having a high x.

(Seventh Embodiment) FIG. 9 is a plan view schematically showing a wiring layout according to a seventh embodiment. FIG. 10 is a cross-sectional view of the semiconductor device taken along the line XX shown in FIG. FIG.
1 shows a structure in which wiring is added. In FIG.
The first layer wiring is not shown to avoid complicating the drawing. As shown in FIG. 10, the first layer wiring is a source contact wiring / substrate contact wiring 16 for connecting between each source contact 8 and the substrate contact 9, and the source contact wiring / substrate contact wiring 16 is a drain contact in FIG. 7 and the gate contact 6 are formed in a wide area except for the area where the gate contact 6 is almost solid. Further, as shown in FIG. 9, the second layer wiring is a drain wiring 10a connecting between the drain contacts 7.
To 10d, and inter-gate wirings 12a to 12d connecting between the gate contacts 6.

In the present embodiment, the source contact wiring and the substrate contact wiring 16 formed by short-circuiting the source contact wiring and the substrate contact wiring are laid flat, so that the source inductance Ls can be particularly reduced, and an oscillator or the like can be used. This wiring is suitable for a circuit requiring a high maximum oscillation frequency fmax. Further, since the number of wiring layers is two, there is an advantage that the number of steps is small and the manufacturing cost can be reduced.

(Eighth Embodiment) FIG. 11 is a plan view schematically showing a wiring layout according to an eighth embodiment, and shows a structure in which wiring is added to the MOSFET shown in FIG. In the present embodiment, since the sectional structure of the semiconductor device can be easily inferred from FIGS. 8 and 10, illustration of the sectional pattern is omitted. Although the first layer wiring is not shown in FIG. 11, the first layer wiring is a source wiring connecting between the source contacts 8 and forming the drain contact 7, the gate contact 6 and the substrate contact 9 in the figure. The source wiring is formed in a wide area excluding the area almost in a solid color state. The second layer wiring includes drain wirings 10 a to 10 d connecting the drain contacts 7 and a gate contact wiring 1 connecting the gate contacts 6.
1a to 11d. In the present embodiment, the substrate contacts are taken out only from the substrate contact portions of the peripheral unit cells.

In this embodiment, the structure of the wiring is simplified, so that there is an advantage that the manufacturing cost can be reduced.

Next, data showing the effects of the semiconductor devices according to the first to eighth embodiments will be described.

FIG. 12 shows the minimum noise figure NFmin and the gain G
a, M having a conventional finger-shaped gate electrode
MO having OSFET and ring-shaped gate electrode of the present invention
It is the figure which compared with SFET. In the figure, the horizontal axis is the unit gate width Wu of one unit, and this unit gate width Wu is the length in the circumferential direction of one ring-shaped gate electrode in the MOSFET of the present invention. Then, it is the finger length of one finger gate. In addition, as for a conventional MOSFET, data is shown for a case where a contact is provided only at one end of a gate electrode (1 contact) and a case where a contact is provided at both ends of a gate electrode (2 contacts). . Further, the conventional MOSFETs are all based on the salicide process, but the data of the MOSFET of the present invention is obtained for the MOSFET of the first embodiment in which the salicide process is not performed. However, in all MOSFETs, the total gate width Wg
Is 200 μm, the gate length in the channel direction is 0.3 μm, and the frequency of the used signal is 2 GHz.
It is. As shown in FIG.
According to this, even without performing the salicide process, the minimum noise figure NFmin can be reduced and the gain Ga can be improved as compared with the conventional MOSFET formed by the salicide process. That is, the effects described in the first embodiment and the like are supported.

FIG. 13 shows MSG (maximum stable gain).
FIG. 7 is a diagram comparing a MOSFET having a conventional finger-shaped gate electrode with a MOSFET having a ring-shaped gate electrode according to the present invention for MAG (maximum available gain). In the figure, the horizontal axis is frequency,
The intersection of the MAG straight line and the horizontal axis is the maximum oscillation frequency fmax. However, the unit gate width Wu of one unit is 5μ.
m, and the unit gate width Wu is the MOS of the present invention.
In the case of the FET, it is the length of one ring-shaped gate electrode in the circumferential direction, and in the case of the conventional MOSFET, it is the finger length of one finger gate. In addition, conventional MOS
For the FET, data are shown for a case where a contact is provided only at one end of the gate electrode (1 contact) and a case where a contact is provided at both ends of the gate electrode (2 contacts). In each MOSFET, the total gate width Wg is 200 μm, the gate length in the channel direction is 0.3 and μm, and the drain voltage is 2 V. As shown in FIG.
According to the SFET, it can be seen that the maximum oscillation frequency fmax is greatly improved.

Next, the relationship between the number of gate lead-out lines and the minimum noise figure NFmin will be described. When the number of gate lead-out lines increases, the gate resistance Rg decreases, but on the other hand, the gate-source capacitance Cgs increases. However, the gate resistance Rg and the gate-source capacitance Cgs are
It changes depending not only on the number of gate lead-out wires but also on its shape.

FIG. 14 shows the number ngt of gate lead-out lines when the shape of the gate lead-out lines is fixed,
It is a figure showing the relation with minimum noise figure NFmin. As can be seen from FIG. 14, by determining the shape of the gate lead-out wiring in advance, the optimum gate lead-out wiring number ngtop for minimizing the minimum noise figure NFmin as much as possible,
An appropriate range Rop for obtaining a minimum noise figure NFmin equal to or less than a desired value can be determined. The minimum noise figure NFmin can be further reduced by adjusting the shape of the gate lead-out wiring so that the optimum gate lead-out number ngtop becomes a natural number.

In each of the above embodiments, a silicon substrate is used as a semiconductor substrate. However, the present invention is not limited to this embodiment. For example, an SOI substrate or a germanium substrate may be used. .

(Ninth Embodiment) Next, a ninth embodiment as an example in which the present invention is applied to an SOI device will be described.

FIG. 15 shows a MOSFET according to this embodiment.
FIG. 17 is a plan view showing a layout of one unit of FIG.
Are MOs according to the present embodiment and a tenth embodiment to be described later.
FIG. 2 is a plan view illustrating a unit cell structure according to the embodiment as an example to show a cell array structure of an SFET.
As shown in FIG. 17, an active region 43 is formed in a region surrounded by element isolation on a silicon substrate, and a large number of unit cells are provided in the active region 43 (see FIG. 17). FIG. 15 shows only one unit cell. A regular octagonal ring-shaped gate electrode 31 is provided on the silicon substrate in the active region 43 via a gate oxide film (not shown). The region inside the gate electrode 31 in the active region 43 is the drain region 32, and the region outside the gate electrode 31 is the source region 33 and the substrate contact portion 35, and the drain region 32 and the source region 33 , High-concentration impurities of the same conductivity type are introduced. Also,
A region below the gate electrode 31 (that is, below the gate oxide film) is a channel region having a conductivity type opposite to that of the impurities in the source region 33 and the drain region 32 and doped with an impurity at a threshold control level. ing. Then, a high-concentration impurity of the same conductivity type as that of the impurity in the channel region and of a conductivity type opposite to that of the impurity in the source region 33 and the drain region 32 is introduced into the substrate contact portion 35. Further, two gate lead-out lines 3 are formed from two opposing sides of each of the sides of the octagon forming the ring-shaped gate electrode 31.
The gate lead-out line 34 extends over the source region 33 in the active region 43 and over the element isolation, and then has a contact portion for signal connection with the upper line at its tip. 34a. Although not shown, a gate oxide film made of a silicon oxide film is also interposed between the gate lead-out line 34 and the silicon substrate. However, a gate insulating film made of a silicon nitride film or a silicon oxynitride film may be used instead of the silicon oxide film.

From the upper wiring, MOSFET
There is provided a contact for making an electrical connection to each part in the inside. One gate contact 36 is provided at each of two contact portions 34a of the gate lead-out wiring 34, one drain contact 37 is provided at the center of the drain region 32, and a total of four source contacts 38 are provided at the source region 33. Two substrate contact portions 35
Are provided with one substrate contact 39, respectively.

The present embodiment is characterized in that two carrier leading wires 34c extending from the ring-shaped gate 31 to the substrate contact portion 35, and a leading end portion 34d formed at the leading end of the carrier leading wire 34c. Is provided. Note that the carrier leading-out wiring 34c
Extend in a direction orthogonal to the above-mentioned first gate lead-out line 34. Then, each source contact 38
One is provided for each source region 33 divided into four by one gate lead-out line 34 and two carrier lead-out lines 34c.

That is, in the present embodiment, the active region 43
In the inside, an impurity of the same conductivity type and the same concentration as that of the channel region is introduced below the carrier leading-out wiring 34c drawn out from the central ring-shaped gate electrode 31 to form a carrier leading-out region 34b. The use region 34b divides the source region 33 and is connected to a substrate contact portion 35 which is a substrate potential fixing region. Therefore, the holes generated in the high electric field region near the drain region 32 in the channel region below the ring-shaped gate electrode 31 are formed in the channel region of the region below the ring-shaped gate electrode 31 into which the impurity of the same conductivity type is introduced. Through a region that does not become a channel region and a region that does not become a channel region (a region below the intersection with the carrier extraction wiring 34c), further passes through a carrier lead-out region 34b and a substrate contact portion 35, and is provided for each unit. The contact 39 is pulled out.

As described above, the SOI-MOS of this embodiment
According to the FET, the carrier lead-out wiring 34c that extends from the ring-shaped gate electrode 31 and extends to reach the substrate contact portion 35 is provided. There is a carrier leading-out region 34b connected to the lower region and the substrate contact portion 35 (substrate potential fixing region).
Therefore, surplus carriers accumulated below the gate of the substrate due to impact ionization or the like can be stably extracted regardless of the gate width dimension, and a stable substrate potential independent of the gate width can be fixed. Therefore, the parasitic bipolar transistor does not operate, and a decrease in the breakdown voltage between the source and drain regions can be suppressed.

Further, since the ring-shaped gate electrode 31 is provided, the finger-type gate electrode does not have an edge transistor generated near the boundary between element isolation, and therefore, has stable electric characteristics without a parallel transistor phenomenon. An SOI-MOSFET having the above is obtained.

Further, the area of the source region 33 is equal to the normal M
Since it is larger than that of the OSFET, the source resistance can be reduced as compared with the conventional SOI-MOSFET even when the upper semiconductor region in the SOI substrate becomes thinner.

(Tenth Embodiment) FIG. 16 is a plan view showing a layout pattern of an SOI-MOSFET according to a tenth embodiment. Also in the present embodiment, the point that the ring-shaped gate electrode 31, the drain region 32, the source region 33, the gate lead-out wiring 34 and the like are provided in the active region 43 is basically the same as the ninth embodiment. It is the same, about the member attached | subjected with the same code | symbol as FIG.
Description is omitted.

Here, the feature of this embodiment is that instead of providing the carrier leading-out wiring, the substrate contact portion 44 (the substrate potential fixing region) extending from the end of the ring-shaped gate electrode 31 to the region to be the substrate contact portion is provided. ) Is that high-concentration impurities of the same conductivity type as the impurities in the channel region and of a conductivity type opposite to that of the impurities in the source region 33 and the drain region 32 are introduced.

Therefore, the SOI-M according to the present embodiment is
Also in the OSFET, the substrate contact portion 44 (substrate potential fixing region) divides the source region 33 and connects the region below the ring-shaped gate electrode 31 containing the impurity of the same conductivity type to the region where the substrate contact 39 is formed. And is enlarged as compared with the other embodiments. Therefore, the holes generated in the high electric field region near the drain region 32 in the channel region below the ring-shaped gate electrode 31 are formed in the channel region of the region below the ring-shaped gate electrode 31 into which the impurity of the same conductivity type is introduced. Through the region that becomes the channel contact region and the region that does not become the channel region (the region below the intersection with the substrate contact portion 44).
Through the (substrate potential fixing region), it is pulled out to the substrate contact 39 provided for each unit.

As described above, the SOI-MOS of this embodiment
According to the FET, since a very small gate length of each unit has a wide substrate contact portion 44 connected to a region below the ring-shaped gate electrode 31 and a formation region of the substrate contact 39, the ring is formed by impact ionization or the like. Excess carriers accumulated below the gate electrode 31 can be stably extracted regardless of the size of the gate width, and a stable substrate potential independent of the gate width can be fixed. Therefore, the parasitic bipolar transistor does not operate, and a decrease in the breakdown voltage between the source and drain regions can be suppressed.

In particular, the SOI-MOSFET of the present embodiment
Is a substrate contact portion 44 into which a high concentration impurity is introduced.
Is connected directly to the region below the ring-shaped gate electrode 31, and has the advantage that holes are quickly extracted.

Although the illustration and description of the overall layout of the SOI-MOSFET constituted by arranging a plurality of unit cells according to the present embodiment are omitted, the SOI-MOSFET according to the ninth embodiment shown in FIG. −MO
Similar to the SFET, a layout in which the unit cells are arranged in a matrix can be employed. This is because in both of the ninth and tenth embodiments, the structure of the unit cell is point-symmetric with respect to the drain contact 37.

(Eleventh Embodiment) FIG. 18 is a plan view schematically showing a wiring layout according to an eleventh embodiment, showing a structure in which wiring is added to the SOI-MOSFET shown in FIG. I have. In FIG. 18, the first layer wiring is not shown in order to avoid a complicated diagram.
The source contact wiring connects between them, and the source contact wiring is formed almost in a solid state in a wide area excluding the formation area of the drain contact 37, the gate contact 36 and the substrate contact 39 in the drawing. Further, as second layer wiring, drain contact wirings 40a and 40b connecting between the drain contacts 37 of each unit cell and gate / substrate contact wiring 4 connecting between the gate contact 36 and the substrate contact 39 are provided.
1a to 41c are provided in parallel and alternately with each other. However, the first and second interlayer insulating films are interposed between the substrate surface and the first-layer wiring and between the first-layer wiring and the second-layer wiring, respectively.

According to the wiring structure of the SOI-MOSFET of the present embodiment, the source contact wiring is formed in a wide area almost solid, so that the source inductance Ls is reduced. In other words, bulk MOSFET
Similar to the sixth to eighth embodiments, the SOI
-For MOSFETs.

In particular, in the present embodiment, when the unit cells are laid out in a cell array, the gate / substrate contact wirings 41a to 41c in which the gate contact wiring and the substrate contact wiring are shared are provided. The substrate fixed potential becomes the same. Therefore, a so-called DT-MOSFET (Dynamic
Threshold-Voltage MOSFET) can be realized without using dedicated wiring and without increasing the occupied area.

(Twelfth Embodiment) Next, a description will be given of a twelfth embodiment relating to an LSI for a mobile phone equipped with a MOSFET having a ring-shaped gate electrode as in the above embodiments.

FIG. 19 shows a portable telephone L according to this embodiment.
FIG. 2 is a block diagram of an SI, in which an RF / IF signal processing circuit 50 and a baseband signal processing circuit 60 are provided on a common semiconductor substrate. The RF / IF signal processing circuit 50 includes an antenna switch 5 for switching a signal connection with the antenna 51 between a reception mode and a transmission mode.
2, a low-noise amplifier (LNA) 53 for amplifying a high-frequency signal input from the antenna switch 52, a power amplifier 57 for transmitting a high-frequency signal for transmission to the antenna switch 52, and a PLL circuit 54; Local oscillator 5
5 and a mixer 56 are arranged. The baseband signal processing circuit 60 includes a demodulation circuit 61 that receives a reception signal from the low noise amplifier 53 via the mixer 56,
A modulation circuit 66 for transmitting a transmission signal to the power amplifier 57 via the mixer 56; and a frame processing circuit 62 for receiving the output of the demodulation circuit 61 and transmitting the transmission signal to the modulation circuit 66.
And a CODEC circuit 6 that converts a signal received from the frame processing circuit 62 and sends the signal to the speaker 64, and converts a signal received from the microphone 65 and sends the signal to the frame processing circuit 62.
3 are arranged.

Here, the performance of the low-noise amplifier 53 (LNA) has a large effect on the circuit, especially when other circuits are provided on a common semiconductor substrate. Special considerations are required for manufacturing.
For this reason, it has conventionally been particularly difficult to integrate a low-noise amplifier (LNA) into an LSI such as an LSI for a mobile phone to form a single chip. Here, in the present invention, as described in the above embodiments, by using a MOSFET having a ring-shaped gate structure having excellent noise characteristics and a high gain, the MOSFET structure is formed on a common substrate with other circuits. It is possible to construct a mobile phone LSI or the like by incorporating the various circuits included therein.

It is to be noted that circuits other than the low noise amplifier 53 (LNA) may have a ring-shaped gate structure, but the MOSFET having the ring-shaped gate structure occupies a slightly larger area than the MOSFET having the finger-type gate structure. There is one side to increase. Therefore, only circuits that require particularly low noise characteristics are constituted by MOSFETs having a ring-shaped gate structure, and the other circuits are different types of MOs.
It is preferable to use an SFET or the like.

In this embodiment, all the circuits shown in FIG. 19 are mounted on a common substrate to form one chip, but a part of these circuits is formed on another semiconductor chip. Needless to say, it may be done.

(Other Embodiments) In each of the above embodiments, the planar shape of the ring-shaped gate electrode is changed to a quadrangle or 8
Although the shape is a polygon, the present invention is not limited to such an embodiment, and may be a polygon such as a hexagon or a triangle, or a circle. However, in the case of an octagon, there is an advantage that a ring shape with as high a symmetry as possible can be realized within a range in which the resolution of the reticle is good and layout data is accurately maintained.

In the above embodiments, the ring-shaped gate electrodes are all closed ring-shaped, but a part of the gate electrodes may be open. In that case, it is preferable that the element isolation is provided below the particularly open portion. This is because, even when impurity ions are implanted from above the gate electrode when forming the source / drain regions, the source and drain regions are not connected via the open portion of the ring-shaped gate.

[0172]

According to claims 1 to 17, at least 1
As a configuration of a high-frequency semiconductor device having two unit cells, a drain region and a source region are respectively provided inside and outside a ring-shaped gate, and further, a gate lead-out wiring extending from a gate electrode and extending over element isolation is provided. Since the gate resistance and the gate-source capacitance determined by the number and shape of the lead-out wirings are configured to give as good a high-frequency characteristic as possible, even if the salicide process is not adopted, the gate resistance and the gate-source capacitance can be reduced. The cut-off frequency can be improved and the minimum noise figure can be increased, and a high-frequency device that is inexpensive and has excellent characteristics can be provided.

In particular, according to the fourteenth to seventeenth aspects, a plurality of unit cells are regularly arranged in one active region to function as one high-frequency FET as a whole, and each part of each unit cell is electrically connected. In addition, the source inductance has been further reduced and the wiring has been simplified by contriving the wiring for the purpose of connection. Therefore, it is possible to provide a high-frequency device having excellent high-frequency characteristics and a small occupation area. it can.

According to the eighteenth to twenty-seventh aspects, as a configuration of a semiconductor device having a plurality of unit cells formed in an active region, a drain region and a source region are provided inside and outside a ring-shaped gate, respectively. Since a gate lead-out wiring that is drawn out and extends over the element isolation is provided, and each member in each unit cell is formed in a regular shape so that a plurality of unit cells are regularly arranged in the active region, a simple structure is provided. By such a repetitive wiring, a structure can be obtained in which wiring for connecting each of the gate contact, the drain contact, the source contact and the substrate contact can be obtained.

According to Claims 28 to 33, the unit cell of the SOI type semiconductor device is provided with a ring-shaped gate electrode, a channel region, a drain region formed inside the gate electrode, and a gate electrode. Since it is composed of the formed source region, the gate lead-out wiring extending from above the source region to above the element isolation, and the substrate contact portion, even when a large number of unit cells are arranged, each unit cell has a substrate contact portion. Thus, it is possible to suppress the operation of the parasitic bipolar transistor due to the effect of fixing the substrate potential, and to provide an SOI transistor having stable electric characteristics due to no parallel transistor phenomenon and small source resistance characteristics.

According to Claims 34 to 38, any one of the methods for designing a semiconductor device having a plurality of unit cells each having a regular shape and formed on a common substrate is described.
Since the shape of the unit cell and the shape of the other unit cells are formed using the layout data of one unit cell, the regular shape of each unit cell in the semiconductor device can be easily and quickly formed. Thus, a highly integrated semiconductor device can be stably manufactured at low manufacturing cost.

According to Claims 39 to 41, as a semiconductor integrated circuit device having a plurality of circuits having different functions formed on a common semiconductor substrate, at least one of the plurality of circuits includes: A ring-shaped gate electrode;
Providing a unit cell having a drain region formed inside the gate electrode, a source region formed outside the gate electrode, and a gate lead-out line extending from above the source region to above the element isolation; Are formed so as to give as good a high-frequency characteristic as possible, so that a circuit requiring good low-noise performance is constituted by an FET having a ring-shaped gate electrode structure, so that other circuits provided on the same substrate can be provided. To avoid adverse effects on the circuit
A large number of semiconductor integrated circuit devices used in a high-frequency region, while a circuit used in a high-frequency region is constituted by an FET having a ring-shaped gate electrode structure by utilizing a high cutoff frequency characteristic of a ring-shaped gate electrode structure FET and the like. This circuit can be accommodated in one chip, so that the size and cost of the semiconductor integrated circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing a layout of a unit cell of a MOSFET having a regular octagonal ring-shaped gate electrode in the first embodiment.

FIG. 2 is a plan view schematically showing a layout of a unit cell of a MOSFET having a regular octagonal ring-shaped gate electrode and a reduced source region below a gate lead-out wiring according to a second embodiment.

FIG. 3 illustrates an M having a regular octagonal ring-shaped gate electrode, a reduced source region below a gate lead-out line, and an enlarged gate contact portion according to the third embodiment.
FIG. 3 is a plan view schematically showing a layout of an OSFET unit cell.

FIG. 4 is a plan view schematically showing a layout of a unit cell of a MOSFET having a regular octagonal ring-shaped gate electrode formed by a salicide process, a source region, and a drain region in a fourth embodiment. .

FIG. 5 is a plan view schematically showing a layout of a unit cell of a MOSFET having a regular square ring-shaped gate electrode and a reduced source region below a gate lead-out line according to a fifth embodiment.

FIG. 6 shows a first example of a MOSFET configured by arranging unit cells in a matrix in the first embodiment.
It is a top view which shows roughly the layout of MOSFET applicable to 5th Embodiment.

FIG. 7 shows a MOSF according to a sixth embodiment in which the unit cells of the first embodiment are arranged in a matrix and wiring is added.
It is a top view which shows the layout of ET roughly.

8 is a cross-sectional view showing a structure of the semiconductor device taken along line VIII-VIII in FIG. 7;

FIG. 9 is a plan view schematically showing a layout of a MOSFET in which unit cells according to a seventh embodiment are arranged in a matrix and wiring is added.

FIG. 10 is a cross-sectional view showing the structure of the semiconductor device along line XX in FIG. 9;

FIG. 11 is a plan view schematically showing a layout of a MOSFET in which unit cells according to an eighth embodiment are arranged in a matrix and wiring is added.

FIG. 12 shows a MOSFET of the present invention and a conventional MOSFET.
FIG. 9 is a diagram showing data on the gate width dependence of the minimum noise figure and the gain of FIG.

FIG. 13 shows a MOSFET of the present invention and a conventional MOSFET.
FIG. 9 is a diagram showing data on the frequency dependence of the gain of FIG.

FIG. 14 is a characteristic diagram showing a change in minimum noise figure with respect to the number of gate lead-out lines of a MOSFET having a ring-shaped gate electrode.

FIG. 15 is an SOI-M having a regular octagonal ring-shaped gate electrode and a carrier leading-out wiring according to the ninth embodiment;
FIG. 3 is a plan view schematically showing a layout of an OSFET unit cell.

FIG. 16 is a plan view schematically showing a layout of an SOI-MOSFET unit cell having a regular octagonal ring-shaped gate electrode and a substrate potential fixed region directly connected to a region below the gate electrode in the tenth embodiment; FIG.

FIG. 17 is a plan view schematically showing a layout of MOSFETs that can be applied to the ninth and tenth embodiments, taking a MOSFET configured by arranging unit cells in a matrix in the ninth embodiment as an example.

FIG. 18 shows an MO according to an eleventh embodiment in which the unit cells of the ninth embodiment are arranged in a matrix and wiring is added.
FIG. 3 is a plan view schematically showing a layout of an SFET.

FIG. 19 is a block circuit diagram schematically showing a configuration of a one-chip LSI for a cellular phone according to a twelfth embodiment.

FIG. 20 is an equivalent circuit diagram of a general MOSFET.

FIG. 21 shows an MO having a conventional finger-like gate electrode.
It is a top view which shows the example of various structures of SFET.

FIG. 22 shows an MO having a conventional finger-like gate electrode.
FIG. 4 is a characteristic diagram showing a change in minimum noise figure with respect to a finger length in an SFET.

FIG. 23 is a sectional view of a unit cell of a conventional SOI-MOSFET.

FIG. 24 is a plan view showing a conventional method of fixing a substrate potential.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Gate electrode 2 Drain region 3 Source region 4 Gate lead-out wiring 4a Gate contact part 5 Substrate contact part 6 Gate contact 7 Drain contact 8 Source contact 9 Substrate contact 10 Drain contact wiring 11 Gate contact wiring 12 Substrate contact wiring 20 Element isolation 21 Active Region 31 Gate electrode 32 Drain region 33 Source region 34 Gate lead-out line 34a Gate contact part 34b Carrier lead-out area 34c Carrier lead-out wiring 34d Carrier lead-out area 35 Substrate contact part 36 Gate contact 37 Drain contact 38 Source contact 39 Substrate contact 40 Drain contact wiring 41 Gate contact wiring 42 Substrate contact wiring 43 Active area 44 Substrate Tact area 50 RF / IF signal processing circuit 51 Antenna 52 Antenna switch 53 Low noise amplifier 54 PLL circuit 55 Local oscillator 56 Mixer 57 Power amplifier 60 Baseband signal processing circuit 61 Demodulation circuit 62 Frame processing circuit 63 CODEC circuit 64 Speaker 65 Microphone 66 Modulation circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/41 (72) Inventor Takashi Nakamura 1006 Ojidoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (41)

[Claims] 1. A semiconductor device having a unit cell formed in an active region surrounded by element isolation on a semiconductor substrate and functioning as a high-frequency signal FET, wherein the unit cell is formed on the active region. A ring-shaped gate electrode, a drain region formed in a region inside the gate electrode in the active region, a drain contact formed on the drain region, and a drain contact formed in the active region. A source region formed in an outer region, a source contact formed on the source region, a gate lead-out line connected to the gate electrode and extending from the source region to the element isolation, And a gate contact formed on the gate lead-out wiring. A semiconductor device formed to give high frequency characteristics. 2. The semiconductor device according to claim 1, wherein said gate electrode has a closed ring shape. 3. The semiconductor device according to claim 1, wherein the gate electrode has an open ring shape divided at least at one location, and element isolation is interposed in the divided region. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the gate lead-out wiring is configured to reduce a parasitic component that degrades high-frequency characteristics. Semiconductor device. 5. The semiconductor device according to claim 4, wherein said gate lead-out wiring is configured such that a gate resistance that changes depending on the number and shape thereof provides high-frequency characteristics as good as possible. Semiconductor device. 6. The high-frequency characteristic of the semiconductor device according to claim 1, wherein said gate lead-out wiring has a gate-source capacitance that varies depending on the number and shape thereof and has as good a potential as possible. A semiconductor device characterized by being configured to provide: 7. The semiconductor device according to claim 1, wherein a length of the ring-shaped gate electrode in a circumferential direction is a minimum in a range where the drain contact can be formed in the drain region. A semiconductor device characterized by being formed into a semiconductor device. 8. The semiconductor device according to claim 1, wherein the source contact is configured such that a source resistance determined by the number and shape of the source contact is as small as possible. Semiconductor device. 9. The semiconductor device according to claim 8, wherein at least a connection portion between said source region and said source contact is made of silicide. 10. The semiconductor device according to claim 1, wherein a width of the source region corresponding to a distance between the ring-shaped gate electrode and the element isolation is equal to the width of the gate lead-out line. A semiconductor device configured to be smaller in a region located below the other than in other regions. 11. The semiconductor device according to claim 1, wherein an area of said gate lead-out wiring on said element isolation is made as large as possible. apparatus. 12. The semiconductor device according to claim 1, wherein a plurality of the gate contacts are provided for one region on the element isolation in the gate lead-out line. A semiconductor device. 13. The semiconductor device according to claim 1, wherein each member in the unit cell is regularly formed on a main surface of the semiconductor substrate. Characteristic semiconductor device. 14. The semiconductor device according to claim 1, wherein at least the gate electrode, the gate lead-out line, the source region, and the drain region in each of the unit cells are formed on a main surface of the semiconductor substrate. A semiconductor device, wherein the semiconductor device is formed so as to be rotationally symmetric with respect to a center point of the ring-shaped gate electrode. 15. The semiconductor device according to claim 1, wherein the gate electrode has a quadrangular ring shape with an angle between sides of 90 degrees. apparatus. 16. The semiconductor device according to claim 1, wherein the gate electrode has an octagonal ring shape with an angle between sides of 135 degrees. apparatus. 17. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon-based substrate. 18. A semiconductor device having a plurality of unit cells formed in an active region surrounded by element isolation on a semiconductor substrate, wherein each of the unit cells is a ring-shaped gate formed on the active region. An electrode, a drain region formed in a region inside the gate electrode in the active region, a drain contact formed on the drain region, and a region outside the gate electrode in the active region. A source contact formed on the source region; a source contact formed on the source region; a gate lead-out line connected to the gate electrode and extending from the source region to the element isolation; And a gate contact formed on the unit cell, wherein each member in each unit cell includes the plurality of units in the active region. A semiconductor device having a regular shape so that cells are regularly arranged. 19. The semiconductor device according to claim 18, wherein at least the gate electrode, the gate lead-out line, the source region and the drain region in each of the unit cells are located at the center of the ring-shaped gate electrode on the main surface of the semiconductor substrate. A semiconductor device formed to be rotationally symmetric with respect to a point. 20. The semiconductor device according to claim 18, wherein the shape of each member in one unit cell of the plurality of unit cells and each member in another unit cell adjacent to the one unit cell. A semiconductor device formed so as to be line-symmetric with the shape of the semiconductor device. 21. The semiconductor device according to claim 18, wherein the gate electrode has a quadrangular ring shape with an angle between sides of 90 degrees. apparatus. 22. The semiconductor device according to claim 18, wherein the gate electrode has an octagonal ring shape with an angle between sides of 135 degrees. apparatus. 23. The semiconductor device according to claim 18, wherein each member of each unit cell is formed so as to give as good a high-frequency characteristic as possible. Semiconductor device. 24. The semiconductor device according to claim 23, further comprising: a source contact wiring connecting the tips of the source contacts to each other; wherein the source contact wiring forms the drain contact and the gate contact in a first layer. A semiconductor device characterized by being formed over the entire region except for the region and its periphery. 25. The semiconductor device according to claim 23, wherein: a substrate contact portion formed in a part of the active region; a substrate contact formed on the substrate contact portion; And a source contact wiring and a substrate contact wiring for connecting the tips of the semiconductor devices. 26. The semiconductor device according to claim 23, wherein a substrate contact portion provided only in a unit cell arranged in a peripheral portion among the unit cells in the active region, and formed on the substrate contact portion. A semiconductor device, further comprising: a substrate contact formed by the above-mentioned method; and a substrate contact wiring for connecting tips of the respective substrate contacts. 27. The semiconductor device according to claim 23, wherein the semiconductor substrate is a silicon-based substrate. 28. A semiconductor region on an insulating portion of a substrate,
A semiconductor device comprising: an element isolation surrounding a semiconductor region; and a unit cell, wherein the unit cell includes a ring-shaped gate electrode formed on the semiconductor region, and a ring-shaped gate of the semiconductor region. A channel region including a low-concentration first conductivity-type impurity formed in a region below the electrode; and a high-concentration second conductivity-type impurity formed in a region of the semiconductor region inside the gate electrode A drain region, a source region formed in a region outside the gate electrode in the semiconductor region and containing a high-concentration second-conductivity-type impurity, and connected to the gate electrode; A semiconductor device comprising: a gate lead-out line extending up; and a substrate contact portion formed in a part of the semiconductor region and containing a high-concentration first conductivity type impurity. Conductor device. 29. The semiconductor device according to claim 28, wherein the substrate contact portion is provided outside the source region, is connected to the gate electrode, and extends from the source region to the substrate contact portion. A semiconductor further comprising: a carrier leading-out wiring extending; and a carrier leading-out region formed in a region of the semiconductor region below the carrier leading-out wiring and containing a low-concentration first conductivity type impurity. apparatus. 30. The semiconductor device according to claim 28, wherein the substrate contact portion extends from the channel region to the outside of the source region by dividing the source region. 31. The semiconductor device according to claim 28, wherein the gate electrode has a closed ring shape. 32. The semiconductor device according to claim 28, wherein the gate electrode has an open ring shape divided at at least one position, and the divided region includes an element. A semiconductor device, wherein separation is interposed. 33. The semiconductor device according to claim 28, wherein each member in the unit cell is formed so as to give as good a high-frequency characteristic as possible. Semiconductor device. 34. A method of designing a semiconductor device having a plurality of unit cells each having a regular shape and formed on a common semiconductor substrate, comprising the steps of: After forming the shape of the one unit cell using the layout data, using the layout data of the one unit cell,
A method for designing a semiconductor device, comprising: forming a shape of another unit cell adjacent to the one unit cell. 35. The method of designing a semiconductor device according to claim 34, wherein, when forming the shape of said another unit cell, inversion movement of the layout data of said one unit cell or a combination of inversion movement and parallel movement. A method of designing a semiconductor device. 36. The method of designing a semiconductor device according to claim 34, wherein when forming the shape of said another unit cell, the layout data of said one unit cell is rotationally moved on a plane.
Alternatively, a method of designing a semiconductor device, comprising performing a combination of a rotational movement and a parallel movement. 37. The method of designing a semiconductor device according to claim 34, wherein each of the unit cells is formed on an active region of the semiconductor substrate surrounded by element isolation. A gate electrode, a drain region formed in a region inside the gate electrode in the active region, a source region formed in a region outside the gate electrode in the active region, A method for designing a semiconductor device, comprising: a gate lead-out line connected to a gate electrode and extending from above the source region to above the element isolation. 38. The method of designing a semiconductor device according to claim 34, wherein each member in said unit cell is formed so as to give as good a high-frequency characteristic as possible. Semiconductor device design method. 39. A semiconductor integrated circuit device comprising a plurality of circuits formed on a common semiconductor substrate and having different functions, wherein at least one of the plurality of circuits is one of the semiconductor substrates Element isolation formed so as to surround a region to be an active region; a ring-shaped gate electrode formed on the active region; and a drain formed in a region inside the gate electrode in the active region. A unit having a region, a source region formed in a region outside the gate electrode in the active region, and a gate lead-out line connected to the gate electrode and extending from above the source region to above the element isolation. A semiconductor integrated circuit, wherein each member in the unit cell is formed so as to give as good a high-frequency characteristic as possible. Apparatus. 40. The semiconductor integrated circuit device according to claim 39, wherein other circuits of the plurality of circuits except for the at least one circuit are formed so as to surround an active region of the semiconductor substrate. A unit cell having: a device isolation; a linear gate electrode formed on the active region; and source / drain regions formed in regions of the active region on both sides of the gate electrode. A semiconductor integrated circuit device. 41. The semiconductor integrated circuit device according to claim 39, wherein the semiconductor integrated circuit device is a mobile phone LSI, and the at least one circuit is a low-noise amplifier. Integrated circuit device.