CN104899343A - Layout design of crossing grid structure MOSFET and multi-crossing finger grid structure MOSFET - Google Patents

Abstract

The present invention provides a layout design of a MOSFET with a cross-gate structure and a MOSFET with a multi-finger gate structure. The layout design of the MOSFET with a cross-gate structure includes: a semiconductor substrate, a cross-shaped cross-gate structure, a source region, and a drain region; The zigzag gate structure includes a first strip gate and a second strip gate perpendicular to the first strip gate, the first strip gate and the second strip gate divide the semiconductor substrate into four regions; the source regions and drain regions are alternately arranged in the four regions. The invention can improve the utilization rate of the active area, increase the driving current, reduce the gate resistance, and increase the maximum oscillation frequency; the cross-gate structure is adopted, and the source and drain are distributed in a spiral shape, which fully utilizes the layout area and can realize multiple The interdigitated gate structure can meet the needs of the designed circuit for the device; at the same time, if the connection of the gate is connected with four terminals, the gate resistance can be effectively reduced, thereby significantly improving the power gain and maximum oscillation frequency of the device.

Description

Layout Design of Cross Gate Structure MOSFET and Multi-Finger Gate Structure MOSFET

technical field

The invention relates to a MOSFET layout design, in particular to a layout design of a cross gate structure MOSFET and a multi-finger gate structure MOSFET.

Background technique

With the continuous development of semiconductor technology, metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in integrated circuit design. MOSFET is a voltage-controlled device. When the gate bias voltage is higher than the threshold voltage of the device, the MOSFET channel forms an inversion layer, and a conductive channel is formed between the source and drain. When the gate voltage is lower than the threshold voltage, the conduction channel is closed and the device is turned off. When the device is turned on, a signal is applied to the gate or source, and the drain will have a corresponding signal output. When semiconductor technology is applied in the field of radio frequency technology, due to parasitic effects, such as parasitic resistance and parasitic capacitance, the performance of the device will be affected. With the continuous improvement of semiconductor technology, the cut-off frequency of the device is also continuously improved.

Radio frequency technologies often require high power transfer characteristics. The maximum oscillation frequency is closely related to parasitic effects, especially the gate resistance, source-drain resistance, etc. The reduction of parasitic resistance requires continuous optimization of layout design. Therefore, while continuously increasing the cut-off frequency of the device, it is necessary to optimize the layout, reduce the parasitic effect of the device, and continuously improve the power gain and maximum oscillation frequency of the device.

In view of the above defects in the prior art, the object of the present invention is to provide a layout design of a cross gate structure MOSFET and a multi-finger gate structure MOSFET, so as to improve the utilization rate of the active region, increase the driving current, and reduce the gate current. Resistor, increase the maximum oscillation frequency.

Contents of the invention

In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a layout design of a cross-gate structure MOSFET and a multi-finger gate structure MOSFET, so as to improve the utilization rate of the active region, increase the driving current, and reduce the gate resistance. , increase the maximum oscillation frequency.

In order to achieve the above purpose and other related purposes, the present invention provides a layout design of a MOSFET with a cross-gate structure, and the layout design includes:

Semiconductor substrate, cross gate structure, source region and drain region;

The cross gate structure includes a first strip gate and a second strip gate perpendicular to the first strip gate, the first strip gate and the second strip gate separate the semiconductor substrate into four regions; the source regions and drain regions are alternately arranged in the four regions.

As a preferred solution of the layout design of the cross-gate structure MOSFET of the present invention, the ends of the cross-shaped cross-gate structure are two-terminal interconnection, three-terminal interconnection or four-terminal interconnection.

As a preferred solution of the layout design of the cross-gate structure MOSFET of the present invention, the cross-shaped cross-gate structure includes a dielectric layer bonded to the surface of the semiconductor substrate and an electrode layer bonded to the surface of the dielectric layer.

As a preferred scheme of the layout design of the cross-gate MOSFET of the present invention, the shape of the source region and the drain region is rectangular.

As a preferred scheme of the layout design of the cross-gate structure MOSFET of the present invention, the shape of the source region and the drain region is a frame shape distributed along the edge of the cross-shaped cross-gate structure.

As a preferred solution of the layout design of the cross-gate MOSFET of the present invention, each of the source regions is short-circuited through a metal interconnection line, and each of the drain regions is short-circuited through a metal interconnection line.

The present invention also provides a layout design of a MOSFET with a multi-finger gate structure, including:

Semiconductor substrate, multi-fingered gate structure, source region and drain region;

The multi-fingered gate structure includes a first strip gate and a plurality of second strip gates perpendicular to the first strip gate, and the first strip gate and the second strip gate connect the semiconductor substrate The bottom is divided into a plurality of regions; the source region and the drain region are alternately arranged in the plurality of regions.

As a preferred solution of the layout design of the multi-fingered gate structure MOSFET of the present invention, the multiple ends of the multi-fingered gate structure are partially interconnected or fully interconnected.

As a preferred scheme of the layout design of the multi-finger gate structure MOSFET of the present invention, the multi-finger gate structure includes a dielectric layer bonded to the surface of the semiconductor substrate and an electrode layer bonded to the surface of the dielectric layer.

As a preferred scheme of the layout design of the multi-fingered gate structure MOSFET of the present invention, each of the source regions is short-circuited through a metal interconnection line, and each of the drain regions is short-circuited through a metal interconnection line.

As mentioned above, the present invention provides a layout design of a MOSFET with a cross-gate structure and a MOSFET with a multi-finger gate structure. The layout design of the MOSFET with a cross-gate structure includes: a semiconductor substrate, a cross-shaped cross-gate structure, a source region and a drain region The cross gate structure includes a first strip gate and a second strip gate perpendicular to the first strip gate, the first strip gate and the second strip gate connect the semiconductor substrate Divided into four regions; the source regions and drain regions are alternately arranged in the four regions. Compared with ordinary interdigitated devices, the present invention can improve the utilization rate of the active area, increase the driving current, reduce the gate resistance, and increase the maximum oscillation frequency; the present invention adopts a cross-gate structure, and adopts a spiral distribution of source and drain , make full use of the layout area as much as possible, and realize the multi-finger (multi-finger) structure, which can meet the needs of the design circuit for devices; at the same time, the connection to the gate can be connected by one end, two ends, or three ends , four-terminal connection, etc.; when four-terminal connection is used, the gate resistance can be effectively reduced, so the power gain and maximum oscillation frequency of the device can be significantly improved.

Description of drawings

FIG. 1 shows a schematic structural diagram of a layout design of a MOSFET with a cross-gate structure according to the present invention.

Fig. 2 is a schematic diagram showing the layout design A-A' cross-section of the cross-gate structure MOSFET in Fig. 1 of the present invention.

Fig. 3 is a schematic structural diagram of the layout design B-B' section of the cross-gate structure MOSFET in Fig. 1 of the present invention.

FIG. 4 is a schematic diagram of an equivalent circuit of a layout design of a MOSFET with a cross-gate structure according to the present invention.

FIG. 5 is a schematic structural diagram of another embodiment of the layout design of the MOSFET with a cross-gate structure according to the present invention.

FIG. 6 is a schematic diagram showing the layout design of the multi-fingered MOSFET of the present invention.

Component designation description

Detailed ways

Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1 to Figure 6. It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the component layout type may also be more complicated.

Example 1

Figures 1 to 3 show schematic structural diagrams of the layout design of the MOSFET with a cross-gate structure in this embodiment, wherein Figure 2 is a schematic structural diagram of the AA' section in Figure 1, and Figure 3 is a schematic diagram of the BB' section in Figure 1 Schematic diagram of the structure.

FIG. 4 shows an equivalent circuit diagram of the cross-gate MOSFET of this embodiment.

As shown in FIGS. 1 to 4 , this embodiment provides a layout design of a MOSFET with a cross-gate structure, and the layout design includes:

a semiconductor substrate, a cross gate structure 10, a source region 20 and a drain region 30;

The cross gate structure 10 includes a first strip gate 101 and a second strip gate 102 perpendicular to the first strip gate 101, the first strip gate 101 and the second strip gate 102 will The semiconductor substrate is divided into four regions; the source regions 20 and drain regions 30 are alternately arranged in the four regions.

As an example, the semiconductor substrate may be an SOI substrate, a bulk silicon substrate, a GaAs substrate, a GaN substrate, an InP substrate, etc. In this embodiment, the semiconductor substrate is an SOI substrate, and the The SOI substrate includes a silicon substrate 90, a buried oxide layer 80 and top silicon. It should be noted that, generally, the layout design of this embodiment can be applied to the design of MOSFETs based on various material substrates.

As an example, the ends of the cross gate structure 10 are two-terminal interconnection, three-terminal interconnection or four-terminal interconnection. In this embodiment, as mentioned above, the end of the cross-shaped cross-gate structure 10 is a four-terminal interconnection (the metal interconnection layer is not shown), this design can effectively reduce the gate resistance, and can significantly improve the performance of the device. power gain and maximum oscillation frequency.

As shown in FIG. 2 , as an example, the cross gate structure 10 includes a dielectric layer 103 bonded to the surface of the semiconductor substrate and an electrode layer 104 bonded to the surface of the dielectric layer 103 . The dielectric layer 103 can be made of silicon dioxide, silicon nitride and other materials, and the electrode layer 104 can be made of metal electrodes, polysilicon and other materials. It should be noted that the several materials listed above are only some preferred solutions of the present invention, and are not limited thereto in actual production.

As shown in FIG. 3 , a channel region 70 is located below the cross-shaped cross-gate structure 10 , and the channel region 70 separates each of the source regions 20 and each of the drain regions 30 from each other.

As shown in FIG. 1 , as an example, the shape of the source region 20 and the drain region 30 is a rectangle.

As an example, each of the source regions 20 is short-circuited by a metal interconnection 40, and each of the drain regions 30 is short-circuited by a metal interconnection 40, wherein the metal interconnection 40 is connected to each of the source regions 20 or each of the source regions 20 through a contact hole 50. The drain region 30 is connected.

As an example, the layout design of this embodiment further includes an isolation structure 60 located on the periphery of the device for device isolation. The isolation structure 60 may be, for example, a shallow trench isolation structure (STI).

Fig. 4 shows the equivalent circuit diagram of the cross-gate structure MOSFET of this embodiment, adopting the layout design of the cross-gate structure MOSFET of this embodiment, it can be equivalent to four MOSFETs connected in parallel, but in fact, this embodiment only needs Making two sources and two drains greatly improves the utilization rate of the active area and increases the driving current of the MOSFET.

Example 2

As shown in Figure 5, this embodiment provides a layout design of a MOSFET with a cross gate structure, its basic structure is as in Embodiment 1, wherein the shape of the source region 20 and drain region 30 is along the 10 edge-distributed box shapes. The layout design of this structure can realize the design of the source region 20 and the drain region 30 with different areas, so as to meet various performance requirements of the MOSFET, and can greatly improve the selectivity of the performance of the MOSFET.

Example 3

As shown in FIG. 6, this embodiment provides a layout design of a MOSFET with a multi-fingered gate structure, including:

a semiconductor substrate, a multi-fingered gate structure, a source region 20 and a drain region 30;

The multi-fingered grid structure includes a first stripe grid 101 and a plurality of second stripe grids 102 perpendicular to the first stripe grid 101, the first stripe grid 101 and the second stripe grid 102 The semiconductor substrate is divided into multiple regions; the source regions 20 and drain regions 30 are alternately arranged in the multiple regions.

As an example, the multiple ends of the multi-finger structure are partially interconnected or fully interconnected. Partially or completely interconnecting the multiple ends of the multi-fingered gate structure, especially when all interconnecting, can effectively reduce the gate resistance, and can obviously improve the power gain and maximum oscillation frequency of the device.

As an example, the multi-finger gate structure includes a dielectric layer 103 bonded to the surface of the semiconductor substrate and an electrode layer 104 bonded to the surface of the dielectric layer 103 . The dielectric layer 103 can be made of silicon dioxide, silicon nitride and other materials, and the electrode layer 104 can be made of metal electrodes, polysilicon and other materials. It should be noted that the several materials listed above are only some preferred solutions of the present invention, and are not limited thereto in actual production.

As an example, the source regions 20 are short-circuited by metal interconnection lines, and the drain regions 30 are short-circuited by metal interconnection lines (the peripheral metal interconnection lines are not shown).

It should be noted that the number of the second stripe gates 102 in this embodiment can be increased or decreased as required, and is not limited thereto. In addition, the layout design of the multi-fingered gate structure MOSFET in this embodiment design other components Reference can be made to Example 1, which will not be repeated here.

As mentioned above, the present invention provides a layout design of a MOSFET with a cross-gate structure and a MOSFET with a multi-finger gate structure. The layout design of the MOSFET with a cross-gate structure includes: a semiconductor substrate, a cross-shaped cross-gate structure 10, a source region 20 and Drain region 30; the cross gate structure 10 includes a first strip gate 101 and a second strip gate 102 perpendicular to the first strip gate 101, the first strip gate 101 and the second strip gate The semiconductor substrate is divided into four regions by the shape gate 102; the source regions 20 and the drain regions 30 are alternately arranged in the four regions. Compared with ordinary interdigitated devices, the present invention can improve the utilization rate of the active area, increase the driving current, reduce the gate resistance, and increase the maximum oscillation frequency; the present invention adopts a cross-gate structure, and adopts a spiral distribution of source and drain , make full use of the layout area as much as possible, and realize the multi-finger (multi-finger) structure, which can meet the needs of the design circuit for devices; at the same time, the connection to the gate can be connected by one end, two ends, or three ends , four-terminal connection, etc.; when four-terminal connection is used, the gate resistance can be effectively reduced, so the power gain and maximum oscillation frequency of the device can be significantly improved. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

The above-mentioned embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed in the present invention should still be covered by the claims of the present invention.

Claims (10)

1. intersect a layout design of grid structure MOSFET, it is characterized in that, comprising:

Semiconductor substrate, decussation grid structure, source region and drain region;

Described decussation grid structure comprises the first strip grid and second strip grid vertical with described first strip grid, and described Semiconductor substrate is divided into four regions by described first strip grid and the second strip grid; Described source region and drain region are alternately arranged in described four regions.

2. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: the end of described decussation grid structure is two ends interconnection, three end interconnection or the interconnection of four ends.

3. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: described decussation grid structure comprises the dielectric layer being incorporated into described semiconductor substrate surface and the electrode layer being incorporated into described dielectric layer surface.

4. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: the shape in described source region and drain region is rectangle.

5. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: the shape in described source region and drain region is the shaped as frame of the marginal distribution along described decussation grid structure.

6. the layout design of intersection grid structure MOSFET according to claim 1, is characterized in that: respectively this source region is by metal interconnection wire short circuit, and respectively this drain region is by metal interconnection wire short circuit.

7. multi-fork refers to a layout design of grid structure MOSFET, it is characterized in that, comprising:

Semiconductor substrate, multi-fork refer to grid structure, source region and drain region;

Described multi-fork refers to that grid structure comprises the first strip grid and multiple second strip grids vertical with described first strip grid, and described Semiconductor substrate is divided into multiple region by described first strip grid and the second strip grid; Described source region and drain region are alternately arranged in described multiple region.

8. multi-fork according to claim 7 refers to the layout design of grid structure MOSFET, it is characterized in that: described multi-fork refers to that multiple ends of grid structure interconnect for part or all interconnect.

9. multi-fork according to claim 7 refers to the layout design of grid structure MOSFET, it is characterized in that: described multi-fork refers to that grid structure comprises the dielectric layer being incorporated into described semiconductor substrate surface and the electrode layer being incorporated into described dielectric layer surface.

10. multi-fork according to claim 7 refers to the layout design of grid structure MOSFET, it is characterized in that: respectively this source region is by metal interconnection wire short circuit, and respectively this drain region is by metal interconnection wire short circuit.