CN105047720B - Silicon-on-insulator RF switching devices structure - Google Patents
Silicon-on-insulator RF switching devices structure Download PDFInfo
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- CN105047720B CN105047720B CN201510491513.1A CN201510491513A CN105047720B CN 105047720 B CN105047720 B CN 105047720B CN 201510491513 A CN201510491513 A CN 201510491513A CN 105047720 B CN105047720 B CN 105047720B
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- silicon
- region
- insulator
- heavily doped
- switching devices
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- 239000012212 insulator Substances 0.000 title claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 33
- 229920005591 polysilicon Polymers 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
Abstract
The present invention provides a kind of silicon-on-insulator RF switching devices structure, including：Buried oxide layer as insulating layer, the device region being arranged in the active layer in buried oxide layer and body area；Channel region, source area and drain region are formed in device region；Moreover, wherein, grid oxic horizon and grid polycrystalline silicon are sequentially arranged on channel region；First end on the extending direction of grid polycrystalline silicon, grid polycrystalline silicon are connected to gate metal by through-hole and connect up；Second end on the extending direction of grid polycrystalline silicon, the first heavily doped region for being in same layer with channel region and being abutted with channel region are connected to the first end of metal connecting wiring by through-hole；The second end of metal connecting wiring is connected to the second heavily doped region by through-hole；With the second heavily doped region be in same layer and in same layer and with adjacently arranging lightly doped district；Connection polysilicon is disposed in lightly doped district；Connection polysilicon is connected to gate metal by through-hole and connects up.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of silicon-on-insulator RF switch
Device architecture.
Background technology
Silicon materials are the most widely used main raw material(s)s of semicon industry, and most of chips are manufactured with silicon chip.
Silicon-on-insulator (SOI, Silicon-on-insulator) is a kind of special silicon chip, and structure is mainly characterized by active
Insulating layer (buried oxide layer) is inserted between layer and substrate layer to separate the electrical connection between active layer and substrate, this knot
Structure feature brings that ghost effect is small, speed is fast, low in energy consumption, integrated level is high, capability of resistance to radiation for the device of silicon-on-insulator class
Many advantages, such as strong.
Now, switching device is manufactured using soi process.Generally, for specific electronic circuit
Using the linearity is an important indicator of silicon-on-insulator RF switching devices.It is existing but for some specific applications
Silicon-on-insulator RF switching devices isolation performance and the linearity be not met by requiring.It is therefore desirable to be able to provide one
Kind can effectively improve the isolation performance of silicon-on-insulator RF switching devices and the device architecture of the linearity.
Invention content
The technical problems to be solved by the invention are to be directed to that drawbacks described above exists in the prior art, and providing one kind can be effective
Improve the isolation performance of silicon-on-insulator RF switching devices and the device architecture of the linearity in ground.
In order to realize above-mentioned technical purpose, according to the present invention, a kind of silicon-on-insulator RF switching devices structure is provided,
Including：Buried oxide layer as insulating layer, the device region being arranged in the active layer in buried oxide layer and body area；
Channel region, source area and drain region are formed in device region；Moreover, wherein, on channel region be sequentially arranged grid oxic horizon and
Grid polycrystalline silicon；First end on the extending direction of grid polycrystalline silicon, grid polycrystalline silicon are connected to gate metal by through-hole
Wiring；Second end on the extending direction of grid polycrystalline silicon is in same layer and abutted with channel region first with channel region
Heavily doped region is connected to the first end of metal connecting wiring by through-hole；The second end of metal connecting wiring is connected to by through-hole
Second heavily doped region；With the second heavily doped region be in same layer and in same layer and with adjacently arranging lightly doped district；
Connection polysilicon is disposed in lightly doped district；Connection polysilicon is connected to gate metal by through-hole and connects up.
Preferably, lightly doped district, the first heavily doped region and the second heavily doped region have identical doping type.
Preferably, the doping type of lightly doped district, the first heavily doped region and the second heavily doped region is adulterated for p-type.
Preferably, the doping type of polysilicon and mixing for lightly doped district, the first heavily doped region and the second heavily doped region are connected
Miscellany type is opposite.
Preferably, the side for connecting polysilicon is disposed with side wall.
Preferably, the side wall is in above the second heavily doped region.
Preferably, silicon layer, channel region, source area and the drain region in body area are isolated area's encirclement.
Preferably, isolated area is shallow trench isolation.
Preferably, buried oxide layer is arranged in silicon substrate layer.
Description of the drawings
With reference to attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And be more easily understood its with the advantages of and feature, wherein：
Fig. 1 schematically shows bowing for silicon-on-insulator RF switching devices structure according to the preferred embodiment of the invention
View.
Fig. 2 schematically shows silicon-on-insulator RF switching devices structure according to the preferred embodiment of the invention edges to scheme
The schematic cross-section of 1 line A-A '.
Fig. 3 schematically shows silicon-on-insulator RF switching devices structure according to the preferred embodiment of the invention along figure
The schematic cross-section of 1 line B-B '.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that represent that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to make present disclosure more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
Fig. 1 schematically shows bowing for silicon-on-insulator RF switching devices structure according to the preferred embodiment of the invention
View.Fig. 2 schematically shows silicon-on-insulator RF switching devices structure according to the preferred embodiment of the invention along Fig. 1's
The schematic cross-section of line A-A '.Fig. 3 schematically shows silicon-on-insulator RF switch according to the preferred embodiment of the invention
Schematic cross-section of the device architecture along the line B-B ' of Fig. 1.
As shown in Figure 1, Figure 2 and Figure 3, silicon-on-insulator RF switching devices structure packet according to the preferred embodiment of the invention
It includes：Buried oxide layer 60 as insulating layer, the device region in the active layer being arranged in buried oxide layer 60 and body area.
Wherein, channel region 30, source area 31 and drain region 32 are formed in device region；Moreover, wherein, on channel region 30
It has been sequentially arranged grid oxic horizon 41 and grid polycrystalline silicon 10.
First end on the extending direction of grid polycrystalline silicon 10, grid polycrystalline silicon 10 are connected to gate metal by through-hole
Wiring 21；Second end on the extending direction of grid polycrystalline silicon 10, with channel region 30 be in same layer and with channel region 30 it is adjacent
The first heavily doped region 91 connect is connected to the first end of metal connecting wiring 24 by through-hole；The second end of metal connecting wiring 24
Second heavily doped region 92 is connected to by through-hole；With the second heavily doped region 92 be in same layer and in same layer and with adjoining
Lightly doped district 34 is arranged on ground；Connection polysilicon 80 is disposed in lightly doped district 34；Connection polysilicon 80 is connected to by through-hole
Gate metal wiring 21.
As a result, in silicon-on-insulator RF switching devices structure according to the preferred embodiment of the invention, such as the dotted line of Fig. 3
Shown in diode, a vertical diode is formed between lightly doped district 34 and connection polysilicon 80, so as to reinforced insulation body
The isolation performance and the linearity of upper silicon RF switching devices.
Lightly doped district 34, the first heavily doped region 91 and the second heavily doped region 92 have identical doping type, such as p-type is mixed
It is miscellaneous.
Preferably, the doping type of connection polysilicon 80 and lightly doped district 34, the first heavily doped region 91 and the second heavy doping
The doping type in area 92 is on the contrary, such as n-type doping.
Preferably, the side of connection polysilicon 80 is disposed with side wall 81；Moreover, the side wall 81 is in the second heavily doped region
92 tops.
Further, specifically, the silicon layer in body area 200, channel region 30, source area 31 and drain region 32 are isolated area 50
It surrounds, to be separated with other devices.
Wherein, specifically, for example, isolated area 50 is shallow trench isolation.
Wherein, specifically, as shown in Figures 2 and 3, buried oxide layer 60 is arranged in silicon substrate layer 70.Wherein silicon substrate
Bottom 70 provides mechanical support for the device architecture in buried oxide layer 60 and buried oxide layer 60 above.
For example, as shown in figure 3,34 and second heavily doped region 92 of lightly doped district is arranged in shallow trench isolation 51, with its
Its structure separates.
Furthermore, it is necessary to explanation, unless stated otherwise or is pointed out, the otherwise term in specification " first ", " the
Two ", the descriptions such as " third " are used only for distinguishing various components, element, step in specification etc., each without being intended to indicate that
Logical relation or ordinal relation between component, element, step etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any those skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications are all made to technical solution of the present invention using the technology contents of the disclosure above or are revised as
With the equivalent embodiment of variation.Therefore, every content without departing from technical solution of the present invention, technical spirit pair according to the present invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
Claims (9)
1. a kind of silicon-on-insulator RF switching devices structure, it is characterised in that including：Buried oxide layer as insulating layer,
The device region being arranged in the active layer in buried oxide layer and body area；Be formed in device region channel region, source area and
Drain region；Moreover, wherein, grid oxic horizon and grid polycrystalline silicon are sequentially arranged on channel region；In the extension of grid polycrystalline silicon
First end on direction, grid polycrystalline silicon are connected to gate metal by through-hole and connect up；On the extending direction of grid polycrystalline silicon
Second end, be in same layer with channel region and metal be connected to by through-hole with the first heavily doped region that channel region abuts and connect
The first end of wiring；The second end of metal connecting wiring is connected to the second heavily doped region by through-hole；At the second heavily doped region
Arrange in same layer and adjacently lightly doped district；Connection polysilicon is disposed in lightly doped district；Connection polysilicon passes through through-hole
It is connected to gate metal wiring；Connect the doping type of polysilicon and the doping type of lightly doped district on the contrary, in lightly doped district and
Diode is formed between connection polysilicon.
2. silicon-on-insulator RF switching devices structure according to claim 1, which is characterized in that lightly doped district, first
Heavily doped region and the second heavily doped region have identical doping type.
3. silicon-on-insulator RF switching devices structure according to claim 1 or 2, which is characterized in that lightly doped district,
The doping type of one heavily doped region and the second heavily doped region is adulterated for p-type.
4. silicon-on-insulator RF switching devices structure according to claim 1 or 2, which is characterized in that connection polysilicon
Doping type it is opposite with the doping type of lightly doped district, the first heavily doped region and the second heavily doped region.
5. silicon-on-insulator RF switching devices structure according to claim 1 or 2, which is characterized in that connection polysilicon
Side be disposed with side wall.
6. silicon-on-insulator RF switching devices structure according to claim 5, which is characterized in that the side wall is in the
Above two heavily doped regions.
7. silicon-on-insulator RF switching devices structure according to claim 1 or 2, which is characterized in that the silicon in body area
Floor, channel region, source area and drain region are isolated area's encirclement.
8. silicon-on-insulator RF switching devices structure according to claim 7, which is characterized in that isolated area is shallow trench
Isolation.
9. silicon-on-insulator RF switching devices structure according to claim 1 or 2, which is characterized in that buried oxide
Layer arrangement is in silicon substrate layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510491513.1A CN105047720B (en) | 2015-08-11 | 2015-08-11 | Silicon-on-insulator RF switching devices structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510491513.1A CN105047720B (en) | 2015-08-11 | 2015-08-11 | Silicon-on-insulator RF switching devices structure |
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| CN105047720A CN105047720A (en) | 2015-11-11 |
| CN105047720B true CN105047720B (en) | 2018-06-29 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683417A (en) * | 2012-05-17 | 2012-09-19 | 中国科学院微电子研究所 | Silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) transistor |
| CN103441131A (en) * | 2013-08-29 | 2013-12-11 | 上海宏力半导体制造有限公司 | Partially-depleted silicon-on-insulator device structure |
| CN104766889A (en) * | 2015-04-17 | 2015-07-08 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switch device structure |
| CN104810406A (en) * | 2015-04-17 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switching device structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014041731A1 (en) * | 2012-09-12 | 2014-03-20 | パナソニック株式会社 | Semiconductor device |
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2015
- 2015-08-11 CN CN201510491513.1A patent/CN105047720B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102683417A (en) * | 2012-05-17 | 2012-09-19 | 中国科学院微电子研究所 | Silicon-on-insulator (SOI) metal-oxide-semiconductor (MOS) transistor |
| CN103441131A (en) * | 2013-08-29 | 2013-12-11 | 上海宏力半导体制造有限公司 | Partially-depleted silicon-on-insulator device structure |
| CN104766889A (en) * | 2015-04-17 | 2015-07-08 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switch device structure |
| CN104810406A (en) * | 2015-04-17 | 2015-07-29 | 上海华虹宏力半导体制造有限公司 | Silicon-on-insulator radio frequency switching device structure |
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| CN105047720A (en) | 2015-11-11 |
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