CN109599441B - SOI diode - Google Patents
SOI diode Download PDFInfo
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- CN109599441B CN109599441B CN201811632266.2A CN201811632266A CN109599441B CN 109599441 B CN109599441 B CN 109599441B CN 201811632266 A CN201811632266 A CN 201811632266A CN 109599441 B CN109599441 B CN 109599441B
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- silicon
- type injection
- injection region
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- 239000000758 substrate Substances 0.000 claims abstract description 59
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 49
- 239000010703 silicon Substances 0.000 claims abstract description 49
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 44
- 238000002347 injection Methods 0.000 claims abstract description 32
- 239000007924 injection Substances 0.000 claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 23
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 20
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 20
- 210000000746 body region Anatomy 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 7
- 239000007943 implant Substances 0.000 claims description 14
- 238000002513 implantation Methods 0.000 description 22
- 238000000034 method Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 239000012212 insulator Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Abstract
The invention discloses an SOI diode.A silicon dioxide intermediate layer is formed above the middle part of a silicon substrate layer; an upper silicon layer is formed above the silicon dioxide middle layer; the upper silicon layer is provided with an upper P-type injection region, a body region and an upper N-type injection region which are sequentially adjacent along the transverse direction; the upper silicon layer and the silicon dioxide middle layer are isolated from the silicon substrate layer in the transverse direction by a shallow trench isolation region; the polysilicon gate is formed right above the body region and is isolated from the upper silicon layer by an insulating dielectric layer; a substrate P-type injection region is formed on the silicon substrate layer on the upper P-type injection region side, and the upper P-type injection region and the substrate P-type injection region are in short circuit connection with each other; and a substrate N-type injection region is formed on the silicon substrate layer on the upper N-type injection region side, and the upper N-type injection region and the substrate N-type injection region are in short circuit with each other. The SOI diode has smaller device size and lower on-resistance.
Description
Technical Field
The invention relates to a semiconductor technology, in particular to an SOI diode.
Background
As shown in fig. 1, a conventional BULK silicon process diode is formed by injecting P-type and N-type impurity ions into a BULK silicon (BULK silicon) region, and only one current path is provided when the diode is forward conducted, which greatly limits the forward conduction capability of the device, increases the on-resistance of the device, and increases the size of the device to occupy the area of the chip and reduce the utilization rate of the chip when the device is designed.
With the development of microelectronic technology, SOI (Silicon-on-Insulator) devices are widely used. Due to the advantages of low power consumption, radiation resistance, latch-up resistance, etc., SOI technology has gradually become the mainstream technology for manufacturing high-speed, low-power, high-reliability integrated circuits, and the use of SOI diodes is also gaining more and more attention. With the use of SOI diodes in the fields of radio frequency and optoelectronics, the structure of conventional SOI diodes is constantly being updated.
An existing SOI diode is shown in fig. 2, which includes an SOI substrate 1, the SOI substrate 1 includes a Si/SiO2/Si three-layer structure, an N + doped region 2 is disposed on a Si layer on an upper portion of the SOI substrate 1, the N + doped region 2 extends from an upper surface of the Si layer on the upper portion of the SOI substrate 1 to a SiO2 layer in a middle portion of the SOI substrate 1, and a thickness of the N + doped region 2 is less than or equal to a thickness of the Si layer on the upper portion of the SOI substrate 1; arranging an N-epitaxial layer 3 on the upper surface of the SOI substrate 1, arranging an annular groove on the N-epitaxial layer 3, extending the groove from the upper surface of the N-epitaxial layer 3 to an SiO2 layer in the middle of the SOI substrate 1, filling polycrystalline silicon 6 in the groove, and arranging a first silicon oxide layer 5 between the side wall of the groove 4 and the polycrystalline silicon 6; the upper surfaces of the grooves are respectively provided with a second silicon oxide layer 7, and the second silicon oxide layers 7 cover the upper surfaces of the grooves 4 and are connected with the first silicon oxide layer 5; and N + doped regions 2 are arranged on the N-epitaxial layer 3 and the SOI substrate 1 at two sides of the groove, and a P + doped region 8 is arranged at the upper part of the N-epitaxial layer 3. The SOI diode with the structure has the advantages of insufficient voltage resistance level, large dark current, large junction capacitance, long response time and insufficient sensitivity.
Disclosure of Invention
The invention aims to provide an SOI diode which has smaller device size and lower on-resistance.
In order to solve the technical problem, the silicon dioxide intermediate layer 203 is formed above the middle part of the silicon substrate layer of the SOI diode provided by the invention; an upper silicon layer is formed over the silicon dioxide intermediate layer 203;
the upper silicon layer is an upper P-type implantation region 204, a body region 206 and an upper N-type implantation region 205 which are adjacent in sequence along the transverse direction;
the upper silicon layer and the silicon dioxide middle layer 203 are isolated from the silicon substrate layer 200 in the transverse direction by a shallow trench isolation region 214;
polysilicon gate 213 is formed over body region 206 and is isolated from the upper silicon layer by an insulating dielectric layer;
a substrate P-type injection region 201 is formed on the silicon substrate layer 200 at the upper P-type injection region 204 side, and the upper P-type injection region 204 and the substrate P-type injection region 201 are in short circuit with each other;
the silicon substrate layer 200 on the upper N-type implant region 205 side is formed with a substrate N-type implant region 202, and the upper N-type implant region 205 is shorted to the substrate N-type implant region 202.
Preferably, sidewalls 212 are formed between the upper silicon layer and the lateral ends of the polysilicon gate 213.
Preferably, the polysilicon gate 213 is floating.
Preferably, the polysilicon gate 213 is shorted to the substrate P-type implantation region 201.
Preferably, the polysilicon gate 213 is shorted to the substrate N-type implant 202.
Preferably, the thickness of the upper silicon layer is 0.01 to 1 μm.
Preferably, the thickness of the silicon dioxide intermediate layer 203 is 0.005 μm to 1.5 μm.
The SOI diode is an SOI polysilicon isolation self-aligned diode, an upper P-type injection region 204 is in short circuit with a substrate P-type injection region 201 as a positive electrode of the SOI polysilicon isolation self-aligned diode, an upper N-type injection region 205 is in short circuit with a substrate N-type injection region 202 as a negative electrode of the SOI polysilicon isolation self-aligned diode, and two current conduction paths are provided when the SOI diode is conducted in the positive direction: one is located in the upper silicon layer and flows from the upper P-type implantation region 204 to the upper N-type implantation region 205, and the other is located in the silicon substrate layer 200 and flows from the substrate P-type implantation region 201 to the substrate N-type implantation region 202, so that the forward conducting current capability of the diode is enhanced compared with that of a traditional bulk silicon process diode, two forward conducting current paths of the SOI diode are respectively located above and below the silicon dioxide middle layer 203 in spatial positions, no redundant chip area is occupied, and the SOI diode has smaller device size and lower on-resistance.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the present invention are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional bulk silicon process diode structure;
FIG. 2 is a schematic diagram of a prior art SOI diode structure;
FIG. 3 is a schematic structural diagram of an SOI diode according to an embodiment of the present invention;
FIG. 4 is a schematic layout diagram of an SOI diode according to an embodiment of the present invention;
fig. 5 is a schematic diagram of structure-layout correspondence of an SOI diode according to an embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example one
As shown in fig. 3, in an SOI (Silicon on Insulator) diode, a Silicon dioxide intermediate layer 203 is formed over the middle of a Silicon substrate layer 200; an upper silicon layer is formed over the silicon dioxide intermediate layer 203;
the upper silicon layer is an upper P-type implantation region 204, a body region 206 and an upper N-type implantation region 205 which are adjacent in sequence along the transverse direction;
the upper silicon layer and the silicon dioxide middle layer 203 are isolated from the silicon substrate layer 200 in the transverse direction by a shallow trench isolation region 214;
polysilicon gate 213 is formed over body region 206 and is isolated from the upper silicon layer by an insulating dielectric layer;
a substrate P-type injection region 201 is formed on the silicon substrate layer 200 at the upper P-type injection region 204 side, and the upper P-type injection region 204 and the substrate P-type injection region 201 are in short circuit with each other;
the silicon substrate layer 200 on the upper N-type implant region 205 side is formed with a substrate N-type implant region 202, and the upper N-type implant region 205 is shorted to the substrate N-type implant region 202.
The SOI diode according to the first embodiment is an SOI polysilicon isolated self-aligned diode, the upper P-type implantation region 204 is short-circuited with the substrate P-type implantation region 201 as a positive electrode of the SOI polysilicon isolated self-aligned diode, the upper N-type implantation region 205 is short-circuited with the substrate N-type implantation region 202 as a negative electrode of the SOI polysilicon isolated self-aligned diode, and two current conduction paths are provided when the SOI diode is in forward conduction: one is located in the upper silicon layer and flows from the upper P-type implantation region 204 to the upper N-type implantation region 205, and the other is located in the silicon substrate layer 200 and flows from the substrate P-type implantation region 201 to the substrate N-type implantation region 202, so that the forward conducting current capability of the diode is enhanced compared with that of a traditional bulk silicon process diode, two forward conducting current paths of the SOI diode are respectively located above and below the silicon dioxide middle layer 203 in spatial positions, no redundant chip area is occupied, and the SOI diode has smaller device size and lower on-resistance.
The SOI diode according to the first embodiment may be completely manufactured by using an SOI conventional process flow without an additional photolithography process, and a layout of an embodiment of the SOI diode is shown in fig. 4, which includes: a Poly layer (Poly mask layer), an AA layer (Active mask layer), an SDP layer (P + Implant mask layer), an SDN layer (N + Implant mask layer), a GBA layer (SOI Active mask layer), and a SOI api layer (SOI epi mask layer). The Poly layer, the AA layer, the SDP layer, the SDN layer and the GBA layer are all located in the SOIEPI layer area, wherein the GBA layer area contains the AA layer and the Poly layer, and the Poly layer is partially overlapped with the AA layer.
As shown in fig. 5, the overlapped portions 301 and 304 of the SDP layer and the AA layer correspond to the substrate P-type implantation region 201 and the upper P-type implantation region 204 in fig. 2, respectively, wherein the SDP layer covers a portion of the Poly layer. The overlapping portions 302 and 305 on the other side of the SDN layer and the AA layer correspond to the substrate N-type implantation region 202 and the upper N-type implantation region 205 in fig. 2, respectively, wherein the SDN layer covers a portion of the Poly layer without an overlapping region with the SDP layer, and the Poly layer corresponds to the polysilicon gate 213 in fig. 2.
Example two
In the SOI diode according to the first embodiment, the lateral ends of the polysilicon gate 213 and the upper silicon layer are respectively formed with the side walls 212.
Preferably, the polysilicon gate 213 is floating.
Preferably, the polysilicon gate 213 is shorted to the substrate P-type implantation region 201.
Preferably, the polysilicon gate 213 is shorted to the substrate N-type implant 202.
Preferably, the thickness of the upper silicon layer is 0.01 to 1 μm.
Preferably, the thickness of the silicon dioxide intermediate layer 203 is 0.005 μm to 1.5 μm.
The above are merely preferred embodiments of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (7)
1. An SOI diode, characterized in that a silicon dioxide intermediate layer (203) is formed over the middle of the silicon substrate layer; an upper silicon layer is formed above the silicon dioxide intermediate layer (203);
the upper silicon layer is an upper P-type injection region (204), a body region (206) and an upper N-type injection region (205) which are adjacent in sequence along the transverse direction;
the upper silicon layer and the silicon dioxide middle layer (203) are separated from the silicon substrate layer (200) in the transverse direction by a shallow trench isolation region (214);
a polysilicon gate (213) formed directly over the body region (206) and isolated from the upper silicon layer by an insulating dielectric layer;
a substrate P-type injection region (201) is formed on the silicon substrate layer (200) at the upper P-type injection region (204) side, and the upper P-type injection region (204) and the substrate P-type injection region (201) are in short circuit connection;
a substrate N-type injection region (202) is formed on the silicon substrate layer (200) on the side of the upper N-type injection region (205), and the upper N-type injection region (205) is in interconnection short circuit with the substrate N-type injection region (202).
2. The SOI diode of claim 1,
side walls 212 are respectively formed between the lateral ends of the polysilicon gate (213) and the upper silicon layer.
3. The SOI diode of claim 1,
the polysilicon gate (213) is suspended.
4. The SOI diode of claim 1,
the polysilicon gate (213) is shorted to the substrate P-type implant region (201).
5. The SOI diode of claim 1,
the polysilicon gate (213) is shorted to the substrate N-type implant region (202).
6. The SOI diode of claim 1,
the thickness of the upper silicon layer is 0.01-1 μm.
7. The SOI diode of claim 1,
the thickness of the silicon dioxide intermediate layer (203) is 0.005 to 1.5 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811632266.2A CN109599441B (en) | 2018-12-29 | 2018-12-29 | SOI diode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811632266.2A CN109599441B (en) | 2018-12-29 | 2018-12-29 | SOI diode |
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| Publication Number | Publication Date |
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| CN109599441A CN109599441A (en) | 2019-04-09 |
| CN109599441B true CN109599441B (en) | 2022-03-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201811632266.2A Active CN109599441B (en) | 2018-12-29 | 2018-12-29 | SOI diode |
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| CN110265382A (en) * | 2019-06-19 | 2019-09-20 | 上海华力微电子有限公司 | Binary channels diode string |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1357926A (en) * | 2000-12-12 | 2002-07-10 | 国际商业机器公司 | Transverse polycrystal silicon PIN diode and its manufacture |
| CN107316871A (en) * | 2016-04-26 | 2017-11-03 | 恩智浦美国有限公司 | Semiconductor-on-insulator with retaining ring（SOI）Block |
| CN206992117U (en) * | 2017-05-05 | 2018-02-09 | 西安科锐盛创新科技有限公司 | A kind of double-deck PiN diodes |
| CN108541343A (en) * | 2016-05-02 | 2018-09-14 | 华为技术有限公司 | Electrostatic discharge protection structure |
-
2018
- 2018-12-29 CN CN201811632266.2A patent/CN109599441B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1357926A (en) * | 2000-12-12 | 2002-07-10 | 国际商业机器公司 | Transverse polycrystal silicon PIN diode and its manufacture |
| CN107316871A (en) * | 2016-04-26 | 2017-11-03 | 恩智浦美国有限公司 | Semiconductor-on-insulator with retaining ring（SOI）Block |
| CN108541343A (en) * | 2016-05-02 | 2018-09-14 | 华为技术有限公司 | Electrostatic discharge protection structure |
| CN206992117U (en) * | 2017-05-05 | 2018-02-09 | 西安科锐盛创新科技有限公司 | A kind of double-deck PiN diodes |
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| CN109599441A (en) | 2019-04-09 |
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