KR20110128419A - Power semiconductor device with trench gate structure - Google Patents

Abstract

PURPOSE: A power semiconductor device with a trench gate structure is provided to improve the strength of the power semiconductor device by preventing parasitic bipolar transistor element from being turned on in an UIS(Unclamped Inductive Load) mode. CONSTITUTION: A power semiconductor device of a trench gate structure includes an active cell and a pillar area(320). A P pillar is formed in the pillar area and is horizontally divided by the active cell and the trench structure. An active cell includes a P type conductive base area, an N+ source area, and a trench structure. The N+ source area is formed on the upper side of the base area. A trench structure(210) is formed on the base area and the source area and includes a gate electrode(160).

Description

Power semiconductor device with trench gate structure

The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device having a trench gate structure.

Semiconductor devices are an important element in power electronics, which are developed to meet the needs of a wide range of industries, including automotive applications as well as high isolation voltages, low conduction losses, switching speeds, and low switching losses. It is becoming. For example, semiconductor devices including insulated gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field effect transistors (power MOSFETs), and various types of thyristors continue to develop in response to such demands.

In general, power MOSFETs used in the field of power electronics have a structure in which electrodes are arranged in two opposing planes. That is, a source electrode and a drain electrode are disposed on the front and rear surfaces of the semiconductor body, respectively, and a gate insulating film and a gate electrode are formed on the front surface of the semiconductor body adjacent to the source metal electrode.

Such a semiconductor device has a current flowing in the semiconductor device in a vertical direction in an on state and depletion regions in the semiconductor device due to a reverse bias voltage applied to the semiconductor device in an off state. It is formed extending in the vertical and horizontal directions.

In order to have a high breakdown voltage, the distance between the aforementioned electrodes must be increased, and for this purpose, the resistivity and thickness of the drift layer are increased. However, this results in an increase in on-resistance of the semiconductor device, thereby reducing conductivity, resulting in a decrease in performance of the semiconductor device. Although an important characteristic index of the power semiconductor device is breakdown voltage and on-resistance during conduction, as described above, breakdown voltage and on-resistance during conduction have a trade off relationship.

In order to solve this problem, a super junction semiconductor device including a drift region including N regions (N pillars) and P regions (P pillars) extending and alternately arranged in a vertical direction is provided. Proposed. A superjunction semiconductor device is a PN junction required to obtain the same breakdown voltage by forming a fully depleted region when a reverse voltage is applied to the semiconductor device by a charge balance between alternating N-fillers and P-pillars. The concentration of can be made higher, and as a result, the on resistance can be reduced.

However, in the conventional superjunction semiconductor device, when an unclamped inductive load (UIS) mode occurs, an avalanche current flows intensively through a P-pillar, and parasitic bipolar transistor components are turned on so that the semiconductor device can be easily failed. There was a problem.

The above-described background technology is technical information that the inventor holds for the derivation of the present invention or acquired in the process of deriving the present invention, and can not necessarily be a known technology disclosed to the general public prior to the filing of the present invention.

The present invention is to provide a power semiconductor device having a trench gate structure that can improve the ruggedness by preventing the turn-on of parasitic bipolar transistor components even when the UIS (Unclamped Inductive Load) mode occurs.

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the present invention, a power semiconductor device having a trench gate structure, comprising: an active cell; And a pillar region in which a first conductivity type pillar is formed and horizontally divided by the active cell and the trench structure, thereby providing a power semiconductor device having a trench gate structure.

The active cell may include a base region of a first conductivity type; A source region formed on the base region; And a trench structure formed on side surfaces of the base region and the source region and including a gate electrode.

In the filler region, the first conductive filler and the second conductive filler in a horizontal direction may be alternately formed in a stripe shape.

The first conductive filler and the second conductive filler in the horizontal direction may be alternately formed in the lower portion of the active cell in a stripe shape.

The second conductivity type filler may be formed to be electrically insulated from the source metal electrode formed thereon.

The formation depth of the first conductivity type pillar may be formed relatively deeper than the etching depth of the trench structure.

An upper surface of at least one of the first conductivity type pillars spaced apart in the horizontal direction may be electrically connected to a source metal electrode formed thereon.

One or more of the plurality of closed regions planarly formed by interconnection of the plurality of trench structures may be designated as the filler regions.

The first region SJ1 and the second region SJ2 which are vertically divided to form a first conductive filler and a second conductive filler are formed in the lower portion of the active cell and the pillar region, and the first region and The second region may be formed to have different formation patterns of the first conductive filler and the second conductive filler, respectively.

The first conductive filler and the second conductive filler formed in the second region may be formed to have a super junction structure.

The first conductivity type may be any one of P type and N type, and the second conductivity type may be another one of P type and N type.

The power semiconductor device may be a power MOSFET or an IGBT.

Other aspects, features, and advantages will become apparent from the following drawings, claims, and detailed description of the invention.

According to an embodiment of the present invention, the parasitic bipolar transistor component is turned on by maintaining a high breakdown voltage and a low on-resistance as well as preventing an avalanche current flowing through the P pillar from flowing into the active cell when the UIS mode occurs. This can increase the robustness of the UIS mode.

1 is a view showing a cross-sectional structure of a semiconductor device for superjunction power according to the prior art.
2 is a cross-sectional view of a semiconductor device for superjunction power in a trench gate structure according to the prior art.
3 is a cross-sectional view illustrating a semiconductor device for a superjunction power source having a trench gate structure in accordance with an embodiment of the present invention.
4 illustrates a method of forming the SJ1 region of FIG. 3 in accordance with an embodiment of the present invention.
FIG. 5A illustrates a method of forming the SJ1 region of FIG. 3 in accordance with another embodiment of the present invention. FIG.
FIG. 5B is a cross-sectional view of the portion aa 'of FIG. 5A; FIG.
5C is a cross-sectional view of the bb ′ portion of FIG. 5A.
FIG. 6 illustrates a method of forming the SJ1 region of FIG. 3 according to another embodiment of the present invention. FIG.
7 is a diagram illustrating a method of forming the SJ1 region of FIG. 3 according to another embodiment of the present invention.
8 illustrates a method of forming the SJ1 region of FIG. 3 according to another embodiment of the present invention.
9 illustrates a method of forming the SJ2 region of FIG. 3 in accordance with embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

If an element such as a layer, region or substrate is described as being on or "onto" another element, the element may be directly above or directly above another element and There may be intermediate or intervening elements. On the other hand, if one element is mentioned as being "directly on" or extending "directly onto" another element, no other intermediate elements are present. In addition, when one element is described as being "connected" or "coupled" to another element, the element may be directly connected to or directly coupled to another element, or an intermediate intervening element may be present. have. On the other hand, when one element is described as being "directly connected" or "directly coupled" to another element, no other intermediate element exists.

"Below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" Relative terms such as "vertical" may be used herein to describe a relationship of one element, layer or region to another element, layer or region, as shown in the figures. It is to be understood that these terms are intended to encompass other directions of the device in addition to the orientation depicted in the figures.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, hereinafter, the description will be given based on an insulated gate bipolar transistor (IGBT), but it is obvious that the technical concept of the present invention can be applied or expanded in the same or similar manner to various types of semiconductor devices such as power MOSFETs.

1 is a view showing a cross-sectional structure of a semiconductor device for superjunction power according to the prior art.

Referring to FIG. 1, in the power semiconductor device, a superjunction region 115 is formed on an N conductive first drift region 110. In the superjunction region 115, conductive pillars 130 and N pillars 135 opposite to each other are alternately disposed in the lateral direction. The side interface of the P pillar 130 and the N pillar 135 is formed as a PN junction structure, and the structure of the P pillar 130 and the N pillar 135 may be understood as a structure forming a charge balancing layer or a super junction structure. have.

The P pillar 130 and the N pillar 135 epitaxially grow a layer (that is, a second conductive drift layer of N conductivity type) for forming the superjunction region 115 on the first drift region 110. It may be formed by performing selective impurity ion implantation or selective impurity doping during epitaxial growth. The N pillar 135 may be set to a region other than the P pillar 130 formed by selectively ion implanting or doping P-type impurities into the epitaxially grown layer.

After forming the P pillar 130 and the N pillar 135 in the superjunction region 115, an N conductive third drift region 120 is formed thereon. Selective P conductivity type impurity ion implantation or doping is performed on the formed third drift region 120 to form a P conductivity type base region 140, and the base region 140 is formed to contact the P pillar 130. . The third drift region 120 remaining on the side of the base region 140 contacts the N pillar 135 that is the second drift region.

In addition, the P pillar 130 and the N pillar 135 are formed by forming the third drift region 120 and then performing high energy ion implantation, or forming a trench for forming the P pillar 130. It can also be formed by a method such as forming a layer of P conductivity type filling the P, or doping the P conductivity type impurity through the inner wall of the formed trench.

Meanwhile, an emitter region 145 of N + conductivity type may be formed in the base region 140. That is, the N + emitter region 145 may be formed by selectively doping and diffusing N + conductive impurities in a predetermined region of the upper surface of the base region 140. In this case, after the N + ion layer is formed in the base region 140, both sides of the N + ion layer left by forming the P + well 150 by doping and diffusing P + conductive impurities in the formed N + ion layer are formed in the N + emitter region ( 145).

After forming the N + emitter region 145, an emitter metal electrode 155 is formed that contacts the base region 140 and the N + emitter region 145. A gate electrode 160 is formed along the gate insulating layer 165 to set a portion of the base region 140 between the surface region of the third drift region 120 and the N + emitter region 145 as a channel. An insulating layer and / or a passivation layer is further formed to cover the gate electrode 160 and the like.

An anode region 170 is formed below the first drift region 110, and an anode metal electrode 175 is formed below the anode region 170. A field stop region (not shown) may be formed between the anode region 170 and the first drift region 110 to prevent the depletion region from extending into the anode region 170. The anode region 170 may be formed by N or P conductive impurities, depending on whether the power semiconductor device is a power MOSFET or an IGBT.

2 is a cross-sectional view showing a semiconductor device for a superjunction power of a trench gate structure according to the prior art.

The power semiconductor device shown in FIG. 2 is formed in a superjunction structure as a trench gate structure. Since the method of forming the superjunction structure and the forming method of the P pillar 130 and the N pillar according to the alternating arrangement of the P pillar 130 and the N pillar 135 is the same as described above with reference to FIG. 1, a description thereof will be omitted.

The trench structure 210 is formed to extend in the downward direction through the N conductivity type drift regions 115 and 120. For example, the trench structure 210 may be formed to penetrate through the P-conductive base region 140 extending in the horizontal direction to reach the N-conductive drift regions 115 and 120.

Trench structure 210 includes gate electrode 160, which is insulated by gate dielectric 165 from adjacent silicon regions, and dielectric dome 220 over gate electrode 160. The silver source metal electrode 155 is insulated from the gate electrode 160. The source metal electrode 155 is electrically connected to the N + source region 145, and a P conductive type having a high concentration of P + well 150 and P + well 150 therein is formed under the N + source region 145. Base regions 140 are each formed.

In addition, a drain region 170 is formed under the N conductive drift region 110, and a drain metal electrode 175 is formed under the drain region 170.

In the case of the power semiconductor device having a superjunction structure, the smaller the pitch of the N pillar 135 and the P pillar 130, the higher the impurity concentration of the N pillar 135 and the P pillar 130. . The power semiconductor device shown in FIG. 2 has a structure in which a high pitch trench gate cell is applied by reducing the pitch of the filler.

In the power semiconductor device of the illustrated structure, the P pillar 130 is connected to the P-conductive base region 140 of the active cell, and the drain current is trenched in the direction of the arrow shown during the conduction. The width of the base region 140, which is a distance between the trench structure 210 and the trench structure 210, to flow through a channel formed in the gate wall, is determined to be wider than the width of the P pillar 130. do.

However, when an unclamped inductive load (UIS) mode occurs in the application of the power semiconductor device, an avalanche current flows intensively along the P pillar 130. Accordingly, the parasitic bipolar transistor component formed by the N conductive drain region 170, the P pillar 130, and the N + source region 145 may be turned on, thereby easily destroying the power semiconductor device.

3 is a cross-sectional view illustrating a semiconductor device for a superjunction power source having a trench gate structure according to an embodiment of the present invention, and FIG. 4 illustrates a method of forming the SJ1 region of FIG. 3 according to an embodiment of the present invention. One drawing. 5 is a diagram illustrating a method of forming the SJ1 region of FIG. 3 according to another embodiment of the present invention, and FIG. 6 is a diagram illustrating a method of forming the SJ1 region of FIG. 3 according to another embodiment of the present invention. . 7 is a diagram illustrating a method of forming the SJ1 region of FIG. 3 according to another embodiment of the present invention, and FIG. 8 is a diagram illustrating a method of forming the SJ1 region of FIG. 3 according to another embodiment of the present invention. 9 is a view illustrating a method of forming the SJ2 region of FIG. 3 according to embodiments of the present invention.

Referring to FIG. 3, in the superjunction power semiconductor device having a trench gate structure, the active cell 310 and the P pillar region 320, which are divided based on the trench structure 210, are alternately disposed in the lateral direction. The active cell 310 and the P pillar region 320 (or the filler region 510 of FIG. 5A) may be configured to have separate contacts.

As described with reference to FIG. 2, the active cell 310 has a P conductivity type base region 140, a P + well 150 formed inside the base region 140, and a base region 140. And an N + source region 145 is formed on top of the P + well 150. The N + source region 145 is electrically connected to the source metal electrode 155 formed thereon, and the N pillar 135 is disposed under the base region 140.

The P pillar 130 is disposed in the P pillar region 320. The P pillar 130 is formed to extend to the surface of the N + semiconductor substrate, and a portion of the upper surface of the P pillar 130 is formed such that the source metal electrode 155 is electrically connected or is formed by the gate dielectric 165. It may be formed to be electrically insulated from the electrode 155.

As shown in FIG. 3, the superjunction power semiconductor device having the trench gate structure according to the exemplary embodiment of the present invention may be formed such that the active cell 310 and the P pillar 130 are structurally separated from each other. The method of forming the active cell 310 and the P pillar 130 to be structurally separated may vary as described later with reference to FIG. 4. Thereby, the pitch of each filler can be formed relatively narrow, and the impurity concentration of the N pillar 135 and the P pillar 130 can further be increased. Of course, in some or all regions, the active cell 310 and the P pillar 130 may be formed in a structure in which structurally not completely separated.

The illustrated superjunction power semiconductor device may independently form the upper region SJ1 and the lower region SJ2 in the formation process. For example, the patterns forming the shape of the filler in each of the regions SJ1 and SJ2 may be different, as exemplarily described in FIGS. 4 to 9, and are formed to balance charges only for SJ2 among SJ1 and SJ2. can do. Naturally, the superjunction structure formed on SJ1 and / or SJ2 can be variously structurally modified.

4 to 8 are conceptual views illustrating a method of forming SJ1, which is an upper region of the superjunction region 115, respectively.

4 illustrates a case in which the SJ1 region is formed such that the active cell 310 of the stripe pattern and the P pillar 130 of the stripe pattern are alternately arranged in the transverse direction. Although not shown, an N pillar 135 may be formed below the active cell 310 as described with reference to FIG. 3. In this case, in the pillar region 510, the P pillar and the N pillar may be formed in a stripe structure in the transverse direction as illustrated in FIG. 5A.

FIG. 5A illustrates a case in which the SJ1 region is formed in a stripe shape in which the active cell 310 having the stripe pattern in the longitudinal direction and the filler region 510 of the stripe pattern are alternately arranged in the lateral direction.

FIG. 5B shows a cross-sectional view of a-a 'of FIG. 5A and FIG. 5C shows a cross-sectional view of b-B' of FIG. 5A. As shown, P pillars 130 and N pillars 135 alternately arranged in the lateral direction will be formed under the active cells 310 formed in the longitudinal direction, respectively.

6 to 8 illustrate an embodiment in which the SJ1 region is arranged in a lattice form with the active cell 310 and the P pillar region 320. Here, the P-pillar region 320 may be defined as an inner region of a closed region (eg, polygonal) partitioned by the connection of the trench structure 210, and the polyhedral outer region may function as the active cell 310. . The trench structure 210 is connected in the longitudinal and transverse directions, for example, as shown in FIG. 6 to distinguish the active cell 310 and the P pillar region 320, or as shown in FIGS. 7 and 8, respectively. Likewise, the active cell 310 and the P-pillar region 320 may be distinguished from each other by being connected only in the longitudinal direction.

9 illustrates a method of forming SJ2, which is a lower region of the superjunction region 115, as viewed from the top.

In the formation of SJ2, the P-pillar 130 has a circular cross section as illustrated in (a), or a longitudinal stripe pattern as illustrated in (b), or as illustrated in (c). Likewise, it may be formed in a lateral stripe pattern.

Shapes formed of SJ1 and SJ2 described above with reference to FIGS. 4 to 9 are only examples, and it is natural that the shapes formed of SJ1 and SJ2 may be varied in addition to these.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims And changes may be made without departing from the spirit and scope of the invention.

110: first drift region 115: superjunction region (second drift region)
120: third drift region 130: P filler
135: N filler 140: Base area
145: emitter region (source region) 150: P + well
155 emitter metal electrode (source metal electrode)
160: gate electrode 165: gate insulating layer
170: anode area (drain area)
175: anode metal electrode (drain metal electrode)
210: trench structure 310: active cell
320: P filler area

Claims (12)

In the power semiconductor device of the trench gate structure,
Active cell; And
A power semiconductor device having a trench gate structure including a pillar region having a first conductive pillar formed thereon and arranged to be horizontally divided by the active cell and the trench structure.
The method of claim 1,
The active cell,
A base region of a first conductivity type;
A source region formed on the base region; And
And a trench structure formed on side surfaces of the base region and the source region, the trench structure including a gate electrode.
The method of claim 1,
The pillar region is a power semiconductor device of a trench gate structure, characterized in that the horizontally the first conductive filler and the second conductive filler in the horizontal direction alternately formed in a stripe shape.
The method of claim 3,
The lower portion of the active cell is a power semiconductor device of a trench gate structure, characterized in that the horizontally formed in the transverse direction the first conductive filler and the second conductive filler alternately formed in a stripe shape.
The method of claim 4, wherein
And the second conductivity type filler is electrically insulated from the source metal electrode formed thereon.
The method of claim 2,
Forming depth of the first conductivity type pillar is a power semiconductor device of a trench gate structure, characterized in that relatively deeper than the etching depth of the trench structure.
The method of claim 1,
An upper surface of at least one of the first conductivity type pillars spaced apart in the horizontal direction is electrically connected to the source metal electrode formed on the upper portion of the power semiconductor device of the trench gate structure.
The method of claim 2,
And at least one of a plurality of closed regions planarly formed by interconnection of a plurality of trench structures is designated as the filler region.
The method of claim 1,
The first region SJ1 and the second region SJ2 that are vertically divided to form a first conductive filler and a second conductive filler are formed in the lower portion of the active cell and the pillar region.
And the first region and the second region each have a different pattern of formation of a first conductivity type filler and a second conductivity type filler.
10. The method of claim 9,
The first conductive filler and the second conductive filler formed in the second region have a super junction structure, the power semiconductor device of a trench gate structure.
10. The method of claim 9,
The first conductive type is any one of P type and N type, and the second conductive type is a power semiconductor device of a trench gate structure, characterized in that the other one of the P type and N type.
The method of claim 1,
The power semiconductor device is a power semiconductor device having a trench gate structure, characterized in that the power MOSFET or IGBT.

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