JPH03293759A - Capacitor to be incorporated into mos integrated circuit device - Google Patents

Abstract

PURPOSE:To form a capacitor having a desired capacitance value in a small chip area by providing a conductor facing a semiconductor area on an oxide film covering semiconductor area and an electrode film which faces the conductor and is connected with the semiconductor area at the same potential on an insulating film covering the conductor. CONSTITUTION:An electrode film 50 is formed on an insulating film 40 and the film 50 is connected with the connecting layer 10a of a semiconductor area 10 through a window opened through the insulating film 40 so as to connect the film 50 with the area 10 at the same potential. At the same time, a wiring film 30a which is connected with the conductor 30 in a conductive state through the window of the film 40 is also provided. Accordingly, a capacitor which uses the film 40 as a dielectric body is formed between the conductor 30 and electrode film 50 and connected in parallel with a conventional capacitor between the conductor 30 and semiconductor area 10 and the wiring film 30a and electrode film 50 work as the pair of terminals T of the composite capacitor as shown in the figure. Therefore, the composite capacitor can be incorporated into a small chip area through a simple process.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to capacitors incorporated within MO5 integrated circuit devices.

[Prior Art] In an MO3 integrated circuit device, a capacitor is usually formed using a conductor, an oxide film, and a silicon semiconductor, and this will be explained below with reference to the drawings.

FIG. 5 shows a conventional example in which a metal is used as a conductor as a capacitor electrode. An n-type layer 3 is diffused with a high impurity concentration into the window opened in the process oxide film 2 covering the n-type substrate l, an oxide film 5 is formed on it, and a metal such as aluminum is further applied as a capacitor electrode on top of it. The electrode film 6 is arranged as shown.

The capacitor is formed between the n-type layer 3 and the electrode film 6, sandwiching an oxide film 5 as a dielectric, and a glabella insulator M9 is used for the connection.
The wiring films 3a and 6 are in conductive contact with each other through the wiring films 3a and 6.
8 to form a pair of terminals T.

FIG. 6 shows a conventional example in which polycrystalline silicon for the gate is used as the conductor. Instead of the n-type layer 3 in the previous example, a P-type well 4 is diffused at the same time as for the field effect transistor.
A conductor 7 made of polycrystalline silicon is provided on the surface of which is covered with a thin oxide film 5 that is the same as the gate oxide film, and a well 4
A p-type connection layer 8 is diffused at a high impurity concentration into a part of the surface.

The capacitor is formed between the well 4 and the conductor 70 using the oxide film 5 as a dielectric, and the wiring film 4 is used for connection with the integrated circuit.
a and 7a are provided.

[tsn that the invention attempts to solve]

When integrating the above-mentioned capacitor into a chip of a MOS integrated circuit device, it is desirable to be able to fabricate it in the same process as the MOS transistor and in as small an area as possible.

As is well known, recently polycrystalline silicon is used for the gates of MOS transistors, so from the above point of view, using metal for the conductor 6 as in the conventional example shown in FIG. 5 is disadvantageous for standardizing the process. be. Furthermore, if the process of applying the oxide film 5 is made common, there is a problem that the required chip area tends to increase because the film thickness cannot be made very thin.

On the other hand, in the conventional example shown in FIG. 6, the oxide film 5 and the conductor 6 can be formed in the same process as the gate oxide film and the gate of the MOS transistor, respectively, and the thickness of the oxide film 5 can be several hundred hundreds. Since it can be made as thin as a human being, a capacitance of several tens of fF can be obtained per 1n square, which has the advantage that the required chip area for the capacitor can be reduced by about one order of magnitude compared to the case of FIG.

However, even with the structure shown in Fig. 6, a chip area of about 100 μ square is required to fabricate a capacitor of several hundred pF, so recently, circuit elements such as MOS transistors are being made with high design rules of 1 μ or less. With the advent of integration, capacitors have been left behind, and the chip area required for them has become much larger than that of other circuit elements.

In addition, in the capacitor having the structure shown in FIG. 6, since the well 4 with a relatively low impurity concentration is used for one electrode, when a voltage is applied, a depletion layer is generated near the surface in contact with the oxide film 5. There is a problem in that the equivalent film thickness becomes large and the capacitance value decreases considerably. Such voltage dependence of the capacitance value can be eliminated if the potential of the conductor 7 can be maintained lower than that of the well 4, but in the actual use of integrated circuit devices, it is often difficult to always satisfy this condition. It is necessary to configure the capacitor size to be larger in advance to account for the decrease in capacitance.

Based on the current situation, the present invention provides a highly integrated MOS
It is an object of the present invention to provide a capacitor that can be incorporated in a chip area as small as possible through a simple process so as to be suitable for an integrated circuit device.

[Means to solve the problem]

According to the present invention, a semiconductor region within an integrated circuit chip;
A thin oxide film covering the surface, a conductor disposed on the oxide film facing the semiconductor region, and an insulating film between the eyebrows covering the conductor.
The above object is achieved by providing a conductor and an electrode film facing each other thereon, connecting the semiconductor region and the electrode film to the same potential, and forming a capacitor between them and the conductor. Can be done.

Note that the oxide film, conductor, insulating film, and electrode film in the above structure should be formed at the same time when providing the gate oxide film, gate, eyebrow insulating film, and wiring film for the MOS transistor of the integrated circuit device. This method is advantageous in that a capacitor can be fabricated without increasing any steps other than those required to fabricate a MOS transistor in an integrated circuit device.

In an advantageous embodiment of the invention, the conductor is formed in a pattern with a plurality of openings, through which impurities are implanted into the semiconductor substrate and thermally diffused to cover the highly doped semiconductor region with the conductor. By forming a planar pattern on the lower side, generation of a depletion layer in the semiconductor region is prevented and a capacitor whose capacitance value is not dependent on voltage is obtained.

In a different embodiment U of the present invention, the conductor is formed in a pattern having a plurality of openings, and impurities of the other conductivity type are diffused into the semiconductor region of one conductivity type through these openings into the semiconductor substrate. By implanting and thermally diffusing another semiconductor region with a high impurity concentration, a surface pattern is created with a high impurity concentration, and the other semiconductor region and the electrode film are connected to the same potential to form a semiconductor region and a conductive film that are also connected to the same potential. By forming a capacitor between the semiconductor region and the other semiconductor region, the voltage dependence of the capacitance can be eliminated as described above, and the capacitor can be formed using the junction capacitance of the ρn junction between one semiconductor region and another semiconductor region. Increase capacitance.

In yet another embodiment of the invention, the conductor is formed in a pattern with a plurality of openings, and impurities of one conductivity type are introduced into the semiconductor region of one conductivity type previously diffused into the semiconductor substrate through these openings. By implanting a conductive region with a high impurity concentration in a pattern corresponding to the opening in the semiconductor region, the conductor and the conductive region are connected to the same potential, and the semiconductor region connected to the same potential and By forming a capacitor between the semiconductor region and the conductive region opposite to that of the semiconductor region, the pn
The capacitance of the capacitor is further increased by utilizing the junction capacitance of the junction.

[Effect]

The present invention forms an additional capacitor by providing an insulating film and an electrode film on a conductor, effectively utilizing the conventional idle space on the conductor, and connects the electrode film to the same potential as the semiconductor region. By connecting a capacitor in parallel to a conventional capacitor between a semiconductor region and a conductive film, its capacitance value is increased.

In this configuration of the present invention, the interlayer insulating film and wiring film for the MO3I-randisk can be used as the insulating film and electrode film for the additional capacitor, respectively, so the present invention adds a process to increase the capacitance value of the capacitor. There's no particular need to do that.

The effects of the above-mentioned advantageous embodiments of the present invention are as described in the next section.

〔Example〕

Hereinafter, some embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows, in cross section, a basic embodiment structure of a capacitor for incorporation into a MOS integrated circuit device according to the present invention.

In the example shown in FIG. 1, the substrate 1 is of n-type, and a P-type semiconductor region 1O
is diffused to a depth of several μm and an oxide film 20 of 0.2 μm is formed on the surface.
The conductor 30 is applied with a thickness of ~0.8n and 0.5n is applied on top of it.
After forming polycrystalline silicon with a thickness of ~1μ, a p-type connection layer 10a is diffused in the semiconductor region 10 with a high impurity concentration,
Then, an insulating film 40 is grown on the entire surface by CVD to a thickness of about 0.5 nm.

Note that the upper semiconductor region 10. Oxidation! 120. conductor 30
and insulation M40 is a MOS) transistor well.

The gate oxide film, the gate, and the interlayer insulating film can be formed in the same process, and the process up to this point is the same as the conventional example shown in FIG. 6 described above. Furthermore, silicon oxide or phosphorus silicate glass can be used for the insulating film 40, as in the case of the glabellar insulating film.

Next, an electrode film 50 with a thickness of 0.5 to 1 nm is formed on the insulating film 40 using aluminum or the like for a wiring film of a MOS transistor.
This electrode film 50 is connected to the same potential as the semiconductor region 10 by forming the electrode film 50 and at the same time bringing it into conductive contact with the connection layer 10a for the semiconductor region 10 through a window opened in the insulating film.

At the same time, a wiring film 30a is provided which is in conductive contact with the conductor 30 through the window of the insulating IW 40. As a result, the insulating film 4 is formed between the conductor 30 and the T-shaped film 50.
A capacitor having 0 as a dielectric is formed and connected in parallel with the conventional capacitor between the conductor 30 and the semiconductor region IO, and the wiring film 30a and the electrode film 53 are connected to a pair of terminals of such a composite capacitor as shown in the figure. Fulfills the role of T.

However, as is, the capacitance of the additional capacitor above with respect to the conventional capacitor is quite small because the insulating film 40 is much thicker than the oxide 11I20.

For this reason, in the embodiment shown in FIG. 1, an etching process is used to open connection windows for the semiconductor region 10 and the conductor 30 in the insulating film 40, so that fine etching is performed on the surface of the insulating layer 140 in contact with the electrode WA50. By digging a large number of concave portions, the effective thickness of the electrode M50 is reduced and the capacitance of the capacitor is increased.

To this end, windows for the insulator 1140 are formed by opening windows and slits with a much smaller diameter and width at a narrow arrangement pitch for the recesses on the photoresist film, and the insulator 1140 is etched using a plasma etching method or the like. It is good to dig into it. In the large opening, the connection window is cut through the insulating film 40, but in the small opening, the connection window is dug only halfway to form a recess. The insulating film 4 under the electrode M2O
By providing the capacitor on the entire surface of the capacitor, it is easy to reduce the effective thickness to about half, and the capacitance of the capacitor of this embodiment can be increased by 30 to 50% compared to the conventional capacitor.

In the embodiment shown in FIG. 2, a conductor is formed in a pattern having a plurality of openings, and a semiconductor region is formed by implanting and diffusing impurities through the openings.

For this purpose, a conductor 31 made of polycrystalline silicon or the like disposed on the oxide film 20 formed on the surface of the substrate 1 is formed in a pattern having a plurality of openings as shown in the figure.

The conductor 31 is formed into a cross-shaped or net-like pattern as a whole by arranging small slit-like circular or rectangular openings at a fine pitch of preferably about 5 fm or less.

Next, impurities are introduced into the surface of the substrate 1 through the openings by ion implantation using the conductor 31 as a mask, and the impurities are also diffused in the direction along the surface of the substrate 1 during thermal diffusion. Now, on the surface of the n-type substrate 1, a p-type semiconductor region 11 is formed at least 10'! Atom/C4
After that, after covering the entire surface with a slightly thinner insulating film 40, a conductive film 50 of aluminum or the like is formed in the same manner as in the previous embodiment. A connecting film 31a for the body 31 is provided to form a pair of terminals T.

In the embodiment shown in FIG. 2, the capacitor between the conductor 31 and the electrode film 50 is connected in parallel to the capacitor between the conductor 31 and the semiconductor region 110, but even when a high voltage is applied to the latter, the semiconductor region 110 Since the impurity concentration is high, the oxide film 20
A depletion layer is not generated near the interface with the capacitor, and therefore a capacitor with capacitance that is independent of voltage can be fabricated. Note that in this embodiment, the insulating film 40 is thicker than in the previous embodiment, but as shown in the figure, the opposing area between the conductor 31 and the electrode film 500 is increased, creating a capacitor with a capacitance 20 to 40% larger than that of the conventional one. is obtained.

In the embodiment shown in FIG. 3, two semiconductor regions are created in addition to the embodiment shown in FIG. 2, thereby adding a capacitor that utilizes the junction capacitance between the blue regions.

For this purpose, a p-type semiconductor region 10 corresponding to the well of a MOS transistor is diffused and placed on an n-type substrate 1, and a conductor with a plurality of openings is formed in the same manner as in the previous embodiment. 31 is disposed, and another semiconductor region 12 is formed in a planar pattern on the surface of the semiconductor region 10 with an opposite n-type impurity concentration.

Further, after covering the entire surface with an insulating film 40, an electrode film 50 is provided to be connected to another semiconductor region 12, and at the same time, in this embodiment, a connecting film 31a for a conductor 31 is formed on a connecting layer 1 as shown in the figure.
It is provided so as to be connected to the semiconductor region 10 via 0a.

As a result, in this embodiment, a capacitor utilizing the junction capacitance of the pn junction between the semiconductor region 10 and another semiconductor region 12 is connected in parallel in addition to the capacitor according to the previous embodiment.

In the embodiment shown in FIG. 3, since the other semiconductor region 12 in contact with the oxide film 20 has a high impurity concentration, the capacitance of the capacitor has no voltage dependence (as in the previous embodiment). The capacitance value increases by the addition of a capacitor that utilizes the junction capacitance between Since it is necessary to use the capacitor with a reverse bias applied to the pn junction between the bidirectional conductor regions 10 and 12, there are restrictions on polarity when using the capacitor.

In the figure, the positive side terminal of the capacitor is shown as Tρ, and the negative side terminal is shown as Tn.

In the embodiment shown in FIG. 4, a p-type semiconductor region is diffused into an n-type substrate 1 and covered with an oxide film 20, and a conductor 31 with an opening is disposed thereon, as in the previous embodiment. However,
The slit-shaped opening is widened as shown, and the conductor 31 is formed as a whole in a comb-shaped pattern, for example. In addition, by using the conductor 31 as a mask and reducing the thermal diffusion range of the n-type impurity ion-implanted through its wide opening, a region with a high impurity concentration of preferably 10!0 atoms/cd or more can be formed. As shown in the figure, a pattern corresponding to the opening is formed in the p-type semiconductor region 10, but the overall pattern is a comb-shaped pattern intricately connected to the conductor 31 to form an n-type conductive region 32.

Thereafter, an electrode film 50 is provided on the entire surface covered with an insulating film 40, but in this embodiment, this electrode film 50 is connected to the same potential as the semiconductor region 10 via a connection layer 10a as shown in the figure. Furthermore, for the conductor 31, as shown in the figure, there is an arrangement for it! 1Il 131a is brought into conductive contact with the conductive region 32 within the window of the insulating film 40, thereby connecting it to the same potential.

Therefore, in this embodiment, as shown in the figure, the conductor 3
A capacitor using the oxide film 20 between the semiconductor region 1 and the semiconductor region 10 as a dielectric, the conductor 31 and the conductive region 32, and the electrode film 5
0 between the p-type semiconductor region 10 and the n-type conductive region 32;
Three parallel-connected capacitors using n-junctions are built in, and a semiconductor region 10 and a conductive region 32 are formed.
Since the junction area between them can be made larger than in the embodiment shown in FIG. 3, the overall capacitance can be further increased compared to the previous embodiments, to about three times that of the conventional one. In this embodiment, as in the previous embodiment, there are restrictions on the polarity of the voltage applied to the capacitor, and the capacitance has some voltage dependence, although to a lesser extent than in the embodiment of FIG.

As can be seen from the above examples, the present invention is not limited to these examples, and can be implemented in various ways within the scope of the invention. The embodiments are merely illustrative, and the present invention can be practiced by appropriately combining the specific configurations and connection modes depending on the purpose or necessity.

〔Effect of the invention〕

As described above, the present invention includes a semiconductor region, an oxide film covering the semiconductor region, a conductor disposed on the semiconductor region facing the semiconductor region, an insulating film covering the semiconductor region, and a semiconductor region disposed on the semiconductor region facing the conductor. By configuring a capacitor with an electrode film connected to the same potential as the capacitor, the following effects can be achieved.

(a) In addition to the capacitor between the conductor and the semiconductor region, a parallel-connected capacitor can be formed between the conductor and the electrode film, making effective use of the previously unused area on the conductor, allowing the desired chip to be formed within a smaller chip area than before. A capacitor with a capacitance value of

(b) Since the parallel-connected capacitor can be constructed using the components of the MOS transistor as they are, there is no need to particularly increase the number of manufacturing steps for the MO3 integrated circuit device.

(C) Furthermore, according to an advantageous embodiment of the invention, it is possible to make the capacitance value voltage dependent (and to build a capacitor with a larger capacitance value within a given chip area).

[Brief explanation of drawings]

1 to 4 relate to the present invention, FIG. 1 is a sectional view of a basic embodiment of a capacitor for incorporation into a MOS integrated circuit device according to the present invention, and FIGS. 2 to 4 relate to the present invention. FIG. 2 is a sectional view showing different embodiments of the invention in the same manner as FIG. 1; FIGS. 5 and 6 relate to the prior art, and FIGS. 5 and 6 are cross-sectional views showing different conventional capantors for incorporation into a MOS integrated circuit device in the same manner as FIG. 1. In these figures, 12 substrates, 2: process oxide film, 3: n-type layer, 3a: wiring film, 4: well, 4a: wiring film, 5: # film, 6: pole film, 6a: wiring Film, 7: Conductor, 7a: Wiring film, 8:
connection layer, 9: interlayer insulating film, 10, 11: semiconductor region,
10a: Connection layer, 12: Another semiconductor region, 20 Dioxide film, 30.31: Conductor, 30a+31a: Wiring film, 32: Conductive region, 40: Insulating film, 50: Electrode film, T
: Capacitor terminal, Tn: Capacitor negative terminal, Tp
:￥2 figure 3rd figure

Claims (1)

[Claims] A semiconductor region within a chip in which an integrated circuit is fabricated, a thin oxide film covering the surface of the semiconductor region, a conductor provided on the oxide film facing the semiconductor region, an insulating film covering the conductor, and the A MOS integrated circuit comprising an electrode film provided above and facing a conductor, the semiconductor region and the electrode film being connected to the same potential to form a capacitor between them and the conductor. Capacitor for built-in device.