JPH08298307A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH08298307A
JPH08298307A JP10374195A JP10374195A JPH08298307A JP H08298307 A JPH08298307 A JP H08298307A JP 10374195 A JP10374195 A JP 10374195A JP 10374195 A JP10374195 A JP 10374195A JP H08298307 A JPH08298307 A JP H08298307A
Authority
JP
Japan
Prior art keywords
layer electrode
lower layer
electrode
insulating film
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10374195A
Other languages
Japanese (ja)
Other versions
JP2690709B2 (en
Inventor
Toshimichi Hatakeyama
利通 畠山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Yamagata Ltd
Original Assignee
NEC Yamagata Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Yamagata Ltd filed Critical NEC Yamagata Ltd
Priority to JP7103741A priority Critical patent/JP2690709B2/en
Publication of JPH08298307A publication Critical patent/JPH08298307A/en
Application granted granted Critical
Publication of JP2690709B2 publication Critical patent/JP2690709B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To improve the frequency characteristic without increasing the mounting area by forming a decoupling capacitor in the MIM structure. CONSTITUTION: A capacitor in the MIM structure is formed of an upper electrode 5 for a ground electrode connected to a lower layer electrode 2 provided on a silicon substrate 1 in a microwave integrated circuit chip through a contact hole 4 of an insulating film 3 and an upper layer electrode 6 for a power supply electrode opposed on the lower layer electrode 2 through the insulating film 3 so as to allow reduction of a mounting area as compared to a case of an outboard capacitor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
マイクロ波集積回路のデカップリングコンデンサに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a decoupling capacitor for a microwave integrated circuit.

【0002】[0002]

【従来の技術】マイクロ波集積回路、特に広帯域増幅器
を基板上に配置、使用する場合には、外部電源から誘起
されるリップル等の雑音が周波数特性等に影響を及ぼ
し、帯域特性の低下、及びフラットネス特性の悪化等を
招き、増幅器本来の特性を基板上で再現出来ないことが
ある。
2. Description of the Related Art When a microwave integrated circuit, especially a wide band amplifier is arranged and used on a substrate, noise such as ripples induced from an external power source affects frequency characteristics and the like, resulting in deterioration of band characteristics. The flatness characteristic may be deteriorated and the original characteristics of the amplifier may not be reproduced on the substrate.

【0003】よって、従来は図2に示すように、外部電
源端子に集積回路電源端子を接続するために基板上に形
成された配線と接地端子との間にチップコンデンサ等の
外付けコンデンサ(通常デカップリングコンデンサと呼
ぶ)を接続して配置することにより、外部電源からのリ
ップル等を接地端子に落していた。
Therefore, conventionally, as shown in FIG. 2, an external capacitor such as a chip capacitor (usually, between a wiring formed on a substrate for connecting an integrated circuit power supply terminal to an external power supply terminal and a ground terminal is used). By connecting and arranging a decoupling capacitor), ripples from the external power supply were dropped to the ground terminal.

【0004】また、配置されるコンデンサは、集積回路
が広帯域で使われるものほど、各周波数帯毎に数種類の
容量値(10000pF、1000pF、100pF、
10pF等)のコンデンサを組合わせて配置する必要が
あった。
As for the arranged capacitors, the wider the integrated circuit is used, the several kinds of capacitance values (10000 pF, 1000 pF, 100 pF) for each frequency band.
It was necessary to combine and arrange capacitors of 10 pF or the like).

【0005】[0005]

【発明が解決しようとする課題】この従来の半導体装置
では、外付けデカップリングコンデンサを用いているた
め、実装時に部品点数が多くなり、大きな実装スペース
が必要になるという問題があった。
In this conventional semiconductor device, since the external decoupling capacitor is used, there is a problem that the number of parts is increased at the time of mounting and a large mounting space is required.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
Si基板上に形成した下層電極と、前記下層電極を含む
前記Si基板の表面に形成した絶縁膜と、前記絶縁膜に
設けて前記下層電極の一端の表面を露出させるコンタク
トホールと、前記コンタクトホール内に露出した前記下
層電極に電気的に接続した第1の上層電極と、前記第1
の上層電極以外の前記下層電極上に前記絶縁膜を介して
形成し前記下層電極と対向させた第2の上層電極とを有
する。
According to the present invention, there is provided a semiconductor device comprising:
A lower layer electrode formed on a Si substrate, an insulating film formed on the surface of the Si substrate including the lower layer electrode, a contact hole provided in the insulating film to expose a surface of one end of the lower layer electrode, and the contact hole A first upper layer electrode electrically connected to the lower layer electrode exposed inside;
A second upper-layer electrode formed on the lower-layer electrode other than the upper-layer electrode via the insulating film and facing the lower-layer electrode.

【0007】[0007]

【実施例】次に、本発明について図面を参照して説明す
る。
Next, the present invention will be described with reference to the drawings.

【0008】図1(a),(b)は本発明の一実施例を
示す平面図及びA−A′線断面図である。
FIGS. 1A and 1B are a plan view and a sectional view taken along the line AA 'showing an embodiment of the present invention.

【0009】図1(a),(b)に示すように、マイク
ロ波集積回路チップ内のSi基板1の上に選択的に下層
電極2を形成し、下層電極2を含むSi基板1の上に厚
さ約400nmの絶縁膜3堆積して下層電極2の上の絶
縁膜3の上部を選択的にエッチングして50nmの厚さ
まで薄くする。次に、下層電極2の一端の絶縁膜3にコ
ンタクトホール4を形成して下層電極2の表面を露出さ
せ、コンタクトホール4を含む絶縁膜3の表面に金属膜
を堆積してパターニングし、コンタクトホール4内に露
出させた下層電極2に電気的に接続して絶縁膜3上に延
在する第1の上層電極(接地電極)5と、上層電極5以
外の下層電極2の上に形成して絶縁膜3を介して下層電
極2と対向させた第2の上層電極(電源電極)6とを形
成する。次に、上層電極5,6を含む表面を被覆するパ
ッシベーション膜7を形成してパターニングし、上層電
極5,6のそれぞれにボンディングパッド8,9を形成
し、MIMコンデンサを形成する。
As shown in FIGS. 1A and 1B, the lower layer electrode 2 is selectively formed on the Si substrate 1 in the microwave integrated circuit chip, and the Si substrate 1 including the lower layer electrode 2 is formed. Then, the insulating film 3 having a thickness of about 400 nm is deposited, and the upper portion of the insulating film 3 on the lower electrode 2 is selectively etched to reduce the thickness to 50 nm. Next, a contact hole 4 is formed in the insulating film 3 at one end of the lower layer electrode 2 to expose the surface of the lower layer electrode 2, and a metal film is deposited on the surface of the insulating film 3 including the contact hole 4 for patterning. It is formed on the first upper layer electrode (ground electrode) 5 electrically connected to the lower layer electrode 2 exposed in the hole 4 and extending on the insulating film 3, and on the lower layer electrodes 2 other than the upper layer electrode 5. As a result, a second upper layer electrode (power supply electrode) 6 facing the lower layer electrode 2 via the insulating film 3 is formed. Next, a passivation film 7 covering the surface including the upper layer electrodes 5 and 6 is formed and patterned, and bonding pads 8 and 9 are formed on the upper layer electrodes 5 and 6, respectively, to form an MIM capacitor.

【0010】この場合、MIMコンデンサの容量値C
は、 C=εO ・εS ・S/d (但し、εO は真空の誘電率、εS は誘電体膜の比誘電
率、SはMIMコンデンサ面積、dは誘電体膜の厚さ)
で与えられる。
In this case, the capacitance value C of the MIM capacitor
Is C = ε O · ε S · S / d (where ε O is the dielectric constant of the vacuum, ε S is the relative dielectric constant of the dielectric film, S is the MIM capacitor area, and d is the thickness of the dielectric film).
Given in.

【0011】ここで、S=100μm×100μm、ε
S =7であれば12pF位の容量値を確保できる。
Here, S = 100 μm × 100 μm, ε
If S = 7, a capacitance value of about 12 pF can be secured.

【0012】このようなMIMコンデンサを内蔵するこ
とにより、高周波領域用のチップコンデンサを削除で
き、チップサイズや実装面積の増加無しに、電源からの
リップル等の影響をなくし、高周波特性の改良が可能と
なる。
By incorporating such an MIM capacitor, the chip capacitor for the high frequency region can be eliminated, the influence of ripples from the power source can be eliminated and the high frequency characteristics can be improved without increasing the chip size or mounting area. Becomes

【0013】本実施例で、接地電極用のボンディングパ
ッド8と電源電極用のボンディングパッド9を隣接して
レイアウトされていることが重要となる。それは、ボン
ディングパッド8とボンディングパッド9を離してレイ
アウトし一層配線で接続する場合、ボンディングパッド
の外周部を引き回すことが必要となる為、ペレットサイ
ズの増加につながるからである。
In this embodiment, it is important that the bonding pad 8 for the ground electrode and the bonding pad 9 for the power supply electrode are laid out adjacent to each other. This is because when the bonding pad 8 and the bonding pad 9 are laid out separately and are connected by a single-layer wiring, it is necessary to lay out the outer peripheral portion of the bonding pad, which leads to an increase in the pellet size.

【0014】集積回路内で使用されるコンデンサには、
MIS(Metal−Insulator−Semic
onductor)構造のものもあるが、内蔵するコン
デンサの容量値は使用周波数、応用回路によって様々な
定数を選択する必要があり、MIS構造ではこれらに対
応しきれない場合があるのに対してMIM構造であれば
メタライズ工程のみで所望の容量値を実現できる利点が
ある。
The capacitors used in integrated circuits include:
MIS (Metal-Insulator-Semiic)
There are some types of on-conductor structure, but it is necessary to select various constants for the capacitance value of the built-in capacitor, depending on the operating frequency and application circuit, and the MIS structure may not be able to handle these, whereas the MIM structure. In that case, there is an advantage that a desired capacitance value can be realized only by the metallizing process.

【0015】[0015]

【発明の効果】以上説明したように、本発明はマイクロ
波集積回路、特に広帯域増加器におけるデカップリング
コンデンサをMIM構造のコンデンサ(10pF程度)
で形成する事により、実装面積及びチップサイズを増や
すこと無しに、帯域特性の向上(2GHzを越える領域
で10%〜20%の向上)及びフラットネスの向上(平
坦性±1dBから±0.2dBに改善)が実現できると
いう効果を有する。
As described above, according to the present invention, the decoupling capacitor in the microwave integrated circuit, especially in the wide band amplifier is the MIM structure capacitor (about 10 pF).
In this case, the band characteristic is improved (10% to 20% in the region over 2 GHz) and the flatness is improved (flatness ± 1 dB to ± 0.2 dB) without increasing the mounting area and the chip size. It has the effect that the improvement can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す平面図及びA−A′線
断面図。
FIG. 1 is a plan view and a sectional view taken along the line AA ′ showing an embodiment of the present invention.

【図2】従来の半導体装置の一例を説明するためのブロ
ック図。
FIG. 2 is a block diagram illustrating an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 Si基板 2 下層電極 3 絶縁膜 4 コンタクトホール 5,6 上層電極 7 パッシベーション膜 8,9 ボンディングパッド 1 Si substrate 2 Lower layer electrode 3 Insulating film 4 Contact hole 5,6 Upper layer electrode 7 Passivation film 8, 9 Bonding pad

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 Si基板上に形成した下層電極と、前記
下層電極を含む前記Si基板の表面に形成した絶縁膜
と、前記絶縁膜に設けて前記下層電極の一端の表面を露
出させるコンタクトホールと、前記コンタクトホール内
に露出した前記下層電極に電気的に接続した第1の上層
電極と、前記第1の上層電極以外の前記下層電極上に前
記絶縁膜を介して形成し前記下層電極と対向させた第2
の上層電極とを有することを特徴とする半導体装置。
1. A lower layer electrode formed on a Si substrate, an insulating film formed on the surface of the Si substrate including the lower layer electrode, and a contact hole provided in the insulating film to expose a surface of one end of the lower layer electrode. A first upper layer electrode electrically connected to the lower layer electrode exposed in the contact hole, and the lower layer electrode formed on the lower layer electrodes other than the first upper layer electrode via the insulating film. Second facing
And an upper layer electrode.
JP7103741A 1995-04-27 1995-04-27 Semiconductor device Expired - Lifetime JP2690709B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7103741A JP2690709B2 (en) 1995-04-27 1995-04-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7103741A JP2690709B2 (en) 1995-04-27 1995-04-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08298307A true JPH08298307A (en) 1996-11-12
JP2690709B2 JP2690709B2 (en) 1997-12-17

Family

ID=14362044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7103741A Expired - Lifetime JP2690709B2 (en) 1995-04-27 1995-04-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2690709B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020082549A (en) * 2001-04-24 2002-10-31 주식회사 하이닉스반도체 Method of manufacturing high capacitance mim capacitor
US7224040B2 (en) 2003-11-28 2007-05-29 Gennum Corporation Multi-level thin film capacitor on a ceramic substrate
KR100838965B1 (en) * 2000-07-21 2008-06-16 엔엑스피 비 브이 Mobile telephone device
JP2013084718A (en) * 2011-10-07 2013-05-09 Toshiba Corp High frequency amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03293759A (en) * 1990-04-12 1991-12-25 Fuji Electric Co Ltd Capacitor to be incorporated into mos integrated circuit device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03293759A (en) * 1990-04-12 1991-12-25 Fuji Electric Co Ltd Capacitor to be incorporated into mos integrated circuit device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100838965B1 (en) * 2000-07-21 2008-06-16 엔엑스피 비 브이 Mobile telephone device
KR20020082549A (en) * 2001-04-24 2002-10-31 주식회사 하이닉스반도체 Method of manufacturing high capacitance mim capacitor
US7224040B2 (en) 2003-11-28 2007-05-29 Gennum Corporation Multi-level thin film capacitor on a ceramic substrate
JP2013084718A (en) * 2011-10-07 2013-05-09 Toshiba Corp High frequency amplifier

Also Published As

Publication number Publication date
JP2690709B2 (en) 1997-12-17

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Effective date: 19970729