KR20020082549A - Method of manufacturing high capacitance mim capacitor - Google Patents

Abstract

PURPOSE: A fabrication method of an MIM(Metal Insulator Metal) capacitor in MML(Merged Memory and Logic) devices is provided to maximize a capacitance by surrounding a side of a lower electrode using an upper electrode. CONSTITUTION: After forming a lower layer(10) on a semiconductor substrate(1), a first metal film is formed on the lower layer(10). A lower electrode(30) is formed by patterning the first metal film. A dielectric film(12) and a second metal film are sequentially formed on the lower electrode(30). An upper electrode(40) is formed to surround one side of the lower electrode(30) by patterning the second metal film and the dielectric film, thereby forming an MIM capacitor(50) composed of the lower electrode(30), the dielectric film(12) and the upper electrode(40).

Description

METHOD OF MANUFACTURING HIGH CAPACITANCE MIM CAPACITOR}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a composite memory and logic device, and more particularly, to a method of manufacturing a high capacity metal insulator metal (MIM) capacitor.

BACKGROUND ART As interest in integrated memory and logic devices (MML) increases, the use of these devices has recently increased. The MML device has a structure in which a memory such as DRAM and a logic such as a logic circuit are implemented on a single chip, and due to the structure in which the memory and logic are implemented on a single chip, existing chips without any special design change. Compared to this, high speed and low power can be driven.

On the other hand, in the MML device, the capacitor formed in the logic region is formed of a metal insulator metal (MIM) structure instead of a conventional polysilicon insulator polysilicon (PIP) structure. Among the passive devices used in the RF band, the capacitor requires a high quality factor (Q) value to be used in the analog circuit of the RF band. In order to realize this, depletion is almost impossible as an electrode material. It is because use of a metal electrode with low resistance is essential.

Hereinafter, a method of manufacturing the MIM capacitor will be described with reference to FIGS. 1A to 1D.

First, as shown in FIG. 1A, in a state in which a predetermined base layer 10 is formed on the semiconductor substrate 1, the first metal film 11 and the dielectric film 12 on the base layer 10. ) And the second metal film 13 are sequentially formed. Here, the base layer 10 may be understood to include an interlayer insulating film having a transistor and surface planarization.

Next, as shown in FIG. 1B, the first photoresist pattern 14 is formed on the second metal layer 13 by a known photolithography process, and then the first photoresist pattern ( The capacitor upper electrode 13a is obtained by etching the second metal film 13 and the dielectric film 12 using 14 as an etching mask.

Next, in a state in which the first photoresist pattern is removed, as shown in FIG. 1C, a second photoresist pattern 15 for forming a capacitor lower electrode is formed on the resultant again through a photolithography process. Next, the exposed first metal film part is etched to obtain the capacitor lower electrode 11a, thereby completing the MIM capacitor 20. Unexplained reference numeral 11b denotes a circuit wiring in the logic region.

Thereafter, as shown in FIG. 1D, in a state where the interlayer insulating film 16 is formed on the resultant, predetermined portions of the interlayer insulating film 16 are selectively etched to form the lower and upper electrodes 11a and 13a of the capacitor. Contact holes for exposing the circuit wiring 11b are formed respectively, and then a conductive film is embedded in each contact hole, so that the plug 17 contacts with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a, respectively. ). Then, a metal film is deposited on the interlayer insulating film 16, and then patterned, and the metal is electrically contacted with the circuit wiring 11b and the capacitor lower and upper electrodes 11a and 13a by the plug 17, respectively. Electrodes 18 are formed.

However, in the conventional MIM capacitor manufacturing method as described above, due to the formation of the lower electrode after the formation of the upper electrode, the formation of the capacitance is only made in the area covered by the upper electrode, but not at the side of the lower electrode. Therefore, in order to obtain a high Q value and a low voltage coefficient, it is necessary to have a high capacity per unit area. Therefore, in order to secure a desired capacity, it is necessary to enlarge the capacitor electrode area. And, consequently, undesirable in terms of high integration.

In addition, in the conventional MIM capacitor structure, since a fringe capacity exists on the side of the electrode, there is also a problem in that the capacitor characteristics are degraded due to the fringe capacity.

Accordingly, an object of the present invention is to provide a method of manufacturing a MIM capacitor capable of forming a capacitance on the lower electrode side, which is devised to solve the above problems.

Another object of the present invention is to provide a method of manufacturing a MIM capacitor capable of increasing a capacity per unit area.

In addition, another object of the present invention is to provide a method for manufacturing a MIM capacitor capable of preventing the deterioration of capacitor characteristics due to fringe capacity.

1A to 1D are cross-sectional views for each process for explaining a conventional MIM capacitor manufacturing method.

2A to 2E are cross-sectional views of processes for explaining a method of manufacturing a MIM capacitor according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1 semiconductor substrate 10 base layer

11: first metal film 12: dielectric film

13: second metal film 16: interlayer insulating film

17a, 17b, 17c: plugs 18a, 18b, 18c: electrodes

21: first photosensitive film pattern 22: second photosensitive film pattern

30 capacitor lower electrode 32 circuit wiring

40 capacitor upper electrode 50 MIM capacitor

The manufacturing method of the MIM capacitor of the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a base layer formed on the upper surface; Forming a first metal film on the underlayer; Patterning the first metal film to form a capacitor lower electrode; Sequentially forming a dielectric film and a second metal film on the underlayer so as to cover the capacitor lower electrode; Patterning the second metal layer and the dielectric layer to form a capacitor upper electrode in such a manner as to cover the other side surface while exposing one side upper surface of the capacitor lower electrode.

In addition, the MIM capacitor manufacturing method of the present invention after the step of forming the capacitor upper electrode, forming an interlayer insulating film on the resultant; Forming first and second plugs in the interlayer insulating layer, the first and second plugs contacting an upper surface of the capacitor lower electrode and a portion of the capacitor upper electrode, respectively; And forming first and second electrodes on the interlayer insulating layer, the first and second electrodes contacting the first and second plugs, respectively.

According to the present invention, after forming the capacitor lower electrode, by forming a dielectric film and the upper electrode on one side of the lower electrode, the capacitance can be formed on the side of the lower electrode, thereby increasing the capacitor capacity per unit area In addition, the deterioration of the capacitor characteristics due to the fringe capacity can also be prevented.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views of processes for describing a method of manufacturing a MIM capacitor according to an exemplary embodiment of the present invention. 1A to 1D are denoted by the same reference numerals. In addition, the left side of the figure shows the MIM capacitor formation region in the logic region, and the right side shows the wiring formation region in the logic region.

First, as illustrated in FIG. 2A, a semiconductor substrate 20 for manufacturing an MML device including a memory region and a logic region, and including a MIM capacitor formation region CR and a wiring formation region MR in the logic region. Prepare. Then, a series of processes including device isolation, well formation, gate formation, silicide formation, and memory cell formation processes are performed to form transistors (not shown) in each of the memory regions and logic regions CR and MR. After forming an insulating film (not shown) to cover the transistors, the surface of the insulating film is planarized to form a predetermined base layer 10. Subsequently, the first metal film 11 for the capacitor lower electrode is deposited on the base layer 10.

Next, as shown in FIG. 2B, the first photoresist layer pattern 21 is formed on the first metal layer 11 through a known photolithography process, and the first photoresist layer pattern 21 is used as an etching mask. By etching the first metal film 11, the capacitor lower electrode 30 is formed in the MIM capacitor formation region CR, and the circuit wiring 32 is formed in the wiring formation region MR.

Next, with the first photoresist pattern 21 removed, as shown in FIG. 2C, the dielectric film 12 covers the capacitor lower electrode 30 and the circuit wiring 32 on the base layer 10. ), And subsequently, the second metal film 13 for the capacitor upper electrode is deposited on the dielectric film 12.

Subsequently, as shown in FIG. 2D, a second photoresist layer pattern 22 is formed on the second metal layer 13 for the capacitor upper electrode through a known photolithography process, and the second photoresist layer pattern 22 is formed. The second metal film 13 and the dielectric film 12 are etched using the etch mask to form the capacitor upper electrode 40 so as to surround the other side while exposing one side upper surface of the capacitor lower electrode 30. As a result, the MIM capacitor 50 according to the present invention is formed.

Thereafter, in a state where the second photoresist layer pattern is removed, an interlayer insulating layer 16 is formed on the resultant, as shown in FIG. 2E, and then predetermined portions of the interlayer insulating layer 16 are selectively etched. First, second and third contact holes exposing one side surface of the capacitor lower electrode 30 and the portion of the capacitor upper electrode 40 and the circuit wiring 32 which are not covered by the capacitor upper electrode 40, respectively. The first, second, and first contacts with the capacitor lower electrode 30, the upper electrode 40, and the circuit wiring 32 are formed by filling the conductive film in the first, second, and third contact holes. Third plugs 17a, 17b, and 17c are formed. Then, after depositing a metal film on the interlayer insulating film 16, and patterning it by the first, second and third plugs (17a, 17b, 17c) and the capacitor lower and upper electrodes (30, 40) Electrodes 18a, 18b, and 18c which are respectively in electrical contact with the circuit wiring 32 are formed.

Since the MIM capacitor 50 of the present invention manufactured through the above process is formed in a form in which the upper electrode 40 surrounds one side of the lower electrode 30, a capacitance is formed at the side portion of the lower electrode 30. This is possible, thereby ensuring a high capacity without expanding the electrode area. In addition, since the MIM capacitor 50 of the present invention can be designed in consideration of the fringe capacitance at the electrode side portion, it is possible to prevent the deterioration of the capacitor characteristics caused by the fringe capacitance.

As described above, the method of the present invention allows the upper electrode to surround one side of the lower electrode in the MIM capacitor structure, so that capacitance formation at the electrode side is possible, and thus, as much as the thickness of the lower electrode. Since the capacity can be increased, a high capacity can be ensured, and it is also advantageous in terms of high integration since there is no need to increase the electrode area to secure the capacity.

In addition, the method of the present invention can prevent the deterioration of the capacitor characteristics due to the fringe capacity by considering the fringe capacity in designing the capacitance of the capacitor.

In addition, since the method of the present invention can implement a high capacity MIM capacitor per unit area, a high Q value and a low voltage rate can be obtained, thus improving the characteristics of the MML element.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (3)

Providing a semiconductor substrate having an underlayer formed on an upper surface thereof; Forming a first metal film on the underlayer; Patterning the first metal film to form a capacitor lower electrode; Sequentially forming a dielectric film and a second metal film on the underlayer so as to cover the capacitor lower electrode; And patterning the second metal film and the dielectric film to form a capacitor upper electrode in a form of covering the other side surface while exposing one side upper surface of the capacitor lower electrode. The method of claim 1, wherein the base layer comprises a transistor and an insulating film having surface planarization. The method of claim 1, wherein after forming the capacitor upper electrode, Forming an interlayer insulating film on the resultant product; Forming first and second plugs in the interlayer insulating layer, the first and second plugs contacting an upper surface of the capacitor lower electrode and a portion of the capacitor upper electrode, respectively; And And forming first and second electrodes on the interlayer insulating layer, the first and second electrodes being in contact with the first and second plugs, respectively.