KR100499395B1 - Structure of capacitor in semiconductor device and fabricating method thereof - Google Patents

Abstract

The present invention discloses a capacitor structure of a semiconductor device and a method of manufacturing the same, which maximize the capacitance effective area and contribute to an increase in device integration. A capacitor structure of a semiconductor device according to the present invention disclosed includes first, second, third, and fourth insulating layers sequentially formed on a substrate, trenches formed in the fourth insulating layer, and a first formed on the trench surface. An electrode, a first dielectric film formed on the first electrode, a second electrode formed to completely fill a trench on the first dielectric film, and a portion of the second electrode on the second electrode and the fourth insulating layer. A second dielectric layer formed to expose the second dielectric layer, a third electrode formed on the second dielectric layer, a metal pad formed on the second insulating layer to be electrically connected to the first electrode, and a substrate resultant to cover the third electrode A fifth insulating layer formed on the first insulating layer, a first connecting electrode and a second connecting electrode formed on the fifth insulating layer to be electrically connected to the third electrode and the exposed second electrode, respectively; Electrode and metal pad To couple to include each plug formed in the third, fourth and fifth insulating layers.

Description

Structure of capacitor in semiconductor device and fabricating method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a capacitor structure of a semiconductor device and a method of manufacturing the same, which maximize the capacitance effective area and contribute to an increase in device integration.

The MIM (metal-insulator-metal) capacitors used in the analog circuits of various graphics and multimedia devices, which occupy most of the merged DRAM and logic (MDL) devices, provide high capacitance with small series resistance and low thermal budget. Thermal budgets are widely used because of the high integration of the process.

MIM capacitors have low VCC and high precision mismatching characteristics compared to conventional polysilicon-insulator-polysilicon (PIP) capacitors. That is, the MIM capacitor is an analog capacitor and is formed of a metal having a high Q factor, almost no depletion as an electrode, and low resistance such as tungsten.

The analog capacitor of the prior art mainly uses a PIP flat plate structure, but since the high precision is required due to the high resistance of the polysilicon electrode itself, there is a limit to being used as an electrode material of a capacitor for an RF IC.

Therefore, a flat capacitor having a MIM structure using a metal electrode without depletion of the electrode itself and having a low resistance value has been developed.

In addition, as the degree of integration of semiconductor devices or devices increases greatly, a damascene process using copper or the like is mainly used in a technology for forming aluminum by etching aluminum.

However, the area occupied by the flat plate capacitor on the substrate is increased, including the case where the MIM capacitor is manufactured using a part of the metal wiring formed by the damascene process as the electrode of the capacitor, which is disadvantageous in reducing integration.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a conventional semiconductor device.

Referring to FIG. 1, an insulating film 11 is formed on a silicon substrate 10, and a lower electrode 12 made of polysilicon doped on the insulating film 11 is patterned in a predetermined shape. In this case, the insulating film 11 may be a field oxide film.

On the surface of the lower electrode 12, a dielectric film 13 made of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed. Since the dielectric film 13 has a high dielectric constant value, it is possible to secure necessary capacitance even in a small area.

Next, a capacitor having a PIP structure is completed by polysilicon doped with the upper electrode 14 covering the upper surface and one side surface of the dielectric film 13 and extending to the upper surface of the insulating film 11.

However, the capacitor having such a structure is advantageous in securing capacitance, but is not easy to use due to the resistance of polysilicon in a device requiring high frequency operation, and is disadvantageous in terms of increasing the effective area since only one surface of the electrode is used as the effective area.

2 is a cross-sectional view of a metal-insulator-metal (MIM) capacitor of a conventional semiconductor device.

Referring to FIG. 2, an insulating film 21 is formed on the silicon substrate 20, and a lower electrode 22 made of a metal such as tungsten is patterned on the insulating film 21 in a predetermined shape. In this case, the insulating film 21 may be a field oxide film.

On the surface of the lower electrode 22, a dielectric film 23 having a thickness thicker than that of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed on the characteristics of the MIM structure.

Next, the upper electrode 24 covering the upper surface and one side surface of the dielectric film 23 and extending to the upper surface of the insulating film 21 is made of a metal material such as tungsten to complete the capacitor of the MIM structure.

However, a capacitor having such a structure is advantageous in a device requiring high frequency operation, but is disadvantageous due to a thick dielectric film for securing capacitance, and also disadvantages in terms of increasing an effective area since only one surface of the electrode is used as an effective area.

As described above, in the prior art, PIP structure capacitors are disadvantageous in high frequency operation, and MIM structure capacitors have difficulty in securing required capacitance.

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Accordingly, it is an object of the present invention to provide a capacitor structure of a semiconductor device in which the capacitance effective area is maximized to contribute to an increase in device integration.

In addition, another object of the present invention is to provide a method for manufacturing a capacitor structure of a semiconductor device, which maximizes the effective capacitance area and contributes to an increase in the degree of integration of the device.

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A capacitor structure of a semiconductor device according to the present invention for achieving the above object, the first, second, third and fourth insulating layer formed in sequence on the substrate; A trench formed in the fourth insulating layer; A first electrode formed on the trench surface; A first dielectric film formed on the first electrode; A second electrode formed to completely fill the trench on the first dielectric layer; A second dielectric film formed on the second electrode and the fourth insulating layer to expose a portion of the second electrode; A third electrode formed on the second dielectric film; A metal pad formed on the second insulating layer to be electrically connected to the first electrode; A fifth insulating layer formed on the substrate product to cover the third electrode; First and second connection electrodes formed on the fifth insulating layer to be electrically connected to the third and exposed second electrode portions, respectively; And plugs formed in the third, fourth, and fifth insulating layers, respectively, to electrically connect the first connector electrode and the metal pad. In the above capacitor structure of the present invention, the first electrode and the third electrode form one electrode of the capacitor, and the second electrode forms the other electrode of the capacitor, thereby interposing two first and second dielectric layers, respectively. Configure the capacitor. The trench has a 'c' shape or an 's' shape on a plane. A first hard mask layer and a second hard mask layer are formed on the bottom surface and the top surface of the third insulating layer, respectively. In addition, a method of manufacturing a capacitor structure of a semiconductor device according to the present invention for achieving the above object comprises the steps of: sequentially forming a first insulating layer and a second insulating layer on a substrate; Forming a metal pad extending in a first direction in the second insulating layer; Forming a third insulating layer on the second insulating layer to cover the metal pad; Forming at least two first plugs and second plugs contacting predetermined portions of the metal pads at predetermined portions of the third insulating layer; Forming a fourth insulating layer to cover the first plug and the second plug; Etching the fourth insulating layer to form a trench to expose the first plug and to form a via hole to expose the second plug; Forming a first electrode in contact with the first plug on the trench surface; Forming a first dielectric film on the first electrode; Filling a metal film in the trench and the via hole to form a third plug in contact with the second electrode and the second plug, respectively; Forming a third electrode on the fourth insulating layer including the second electrode, the third electrode having a second dielectric film therebetween, overlapping most of the second electrode and exposing a portion thereof; Forming a fifth insulating layer on the substrate resultant; Forming fourth, fifth, and sixth plugs in the fifth insulating layer, the fourth, fifth, and sixth plugs contacting the third electrode, the third plug, and the second electrode, respectively; And forming a first connector electrode contacting the fourth and fifth plugs and a second connector electrode contacting the sixth plug on the fifth insulating layer. In this case, the fourth insulating layer has a first hard mask layer and a second hard mask layer formed on its lower and upper surfaces, respectively. The second electrode and the third plug are formed by a damascene process. The trench is formed to have a planar 'C' shape or an 'S' shape. According to the present invention, using the first electrode and the third electrode as one capacitor electrode, and using the second electrode interposed between them and the dielectric film as another capacitor electrode, the lower surface, side and top of the second electrode By using most of the surface as the effective area of the capacitor, it is possible to provide a very excellent capacitor in terms of increasing capacitance. (Example)

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Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a layout of a capacitor structure of a semiconductor device according to an embodiment of the present invention, and FIGS. 4A and 4B are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 3. 3, 4A, and 4B, first to fifth interlayer insulating layers 31, 33, 34, 37, and 46 are sequentially stacked on the silicon substrate 30, which is a semiconductor substrate.

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A trench is formed in the fourth interlayer insulating layer 37. The trench may be formed to have a shape capable of maximizing capacitance, for example, having a 'c' shape when viewed in plan view, and may also be formed as an 's' shape in addition to the 'c' shape. The first electrode 391 and the first dielectric film 401 are sequentially formed on the inner surface of the trench, and the second electrode 420 is filled in the remaining trench portions.

The third electrode 44 is formed on the fourth interlayer insulating layer 37 with the second dielectric film 43 interposed therebetween. Like the trench, the third electrode 44 is formed to have a 'c' shape when viewed in plan view. In particular, the third electrode 44 is formed to overlap most of the second electrode 420 except for a part of the second electrode 420. For example, the third electrode 44 is formed so as not to overlap the second electrode portion on the left side of the line A-A ', but overlapping only the second electrode portion on the right side of the line A-A'.

The first connection electrode 480 and the second connection electrode 481 are spaced apart from each other on the second electrode 420 and the third electrode 44 with the fifth interlayer insulating layer 46 interposed therebetween.

In this case, the first connector electrode 480 is electrically connected to the third electrode 44 through the fifth plug 470 and the sixth plug 471 formed to penetrate the fifth interlayer insulating layer 46. In addition, the fourth connector 480 and the third plug 421 and the third plug formed to penetrate the fifth interlayer insulating layer 46 and the fourth plug 421 and the third interlayer insulating layer 37 are formed. The third plug 352 formed to penetrate the interlayer insulating layer 34 is electrically connected to the metal pad 32 formed on the second interlayer insulating layer 33.

In addition, the first electrode 391 is electrically connected to the metal pad 32 through the first and second plugs 350 and 351 formed on the third interlayer insulating layer 34 thereunder.

Meanwhile, an eighth plug 473 electrically connected to a second electrode portion not overlapping with the third electrode 44 is formed on the fifth interlayer insulating layer 46 to form the second connection electrode 481 and the second electrode. The electrode 420 is electrically connected.

Since the fifth plug 470 and the sixth plug 471 are for electrically connecting the third electrode 44 and the first connection electrode 480, any of the two plugs 470 and 471. Omitting one does not affect the operation of the capacitor element.

In addition, since the first plug 350 and the second plug 351 are also for electrically connecting the first electrode 391 and the metal pad 32, one of the two plugs 350 and 351 may be omitted. 4A and 4B, reference numerals 36 and 38, which are not described, denote the first hard mask layer and the second hard mask layer, respectively.

5A through 5E are cross-sectional views illustrating processes of manufacturing a capacitor structure of a semiconductor device according to the present invention. FIGS. 5A through 5D are cross-sectional views taken along a line II ′ of FIG. 3 and FIG. It is process sectional drawing along the II-II 'line | wire of FIG.

Referring to FIG. 5A, a first interlayer insulating layer 31 is formed of an insulator such as an oxide film on a silicon substrate 30, then a first metal layer is deposited thereon, and then patterned by photolithography to form a metal pad 32. ). In this case, the metal pad 32 is formed in a form that can be electrically connected to the first electrode and the third electrode of the capacitor to be formed in a subsequent process, for example, has a rectangular shape extending in the first direction.

Next, after the second interlayer dielectric layer 33 is formed on the first interlayer dielectric layer 31 to cover the metal pad 32, the surface of the second interlayer dielectric layer 33 is subjected to CMP (chemical). mechanical polishing) to expose the surface of the metal pad (32). Then, a third interlayer insulating layer 34 made of an oxide film or the like is formed on the exposed metal pad 32 and the second interlayer insulating layer 33.

Next, the third interlayer insulating layer 34 is etched to form first to third via holes exposing predetermined portions of the metal pad 32, respectively. In this case, the first to third via holes are first coated with a photoresist on the third interlayer insulating layer 34, and then exposed and developed to form the first through third via holes along the cut line I-I ′ of the layout of FIG. 3. After forming a photoresist pattern (not shown) having openings that respectively expose a surface of the third interlayer insulating layer 34 overlapping the metal pad 34 at a predetermined interval, the exposed third interlayer insulating layer portions are formed. It forms by etching.

Next, the photoresist pattern is removed by a method such as oxygen ashing (O ₂ ahing) or the like, and then a conductive layer made of metal such as tungsten is deposited on the third interlayer insulating layer 34 to sufficiently fill the first to third via holes. Next, the conductive layer is etched by CMP or the like so that the surface of the third interlayer insulating layer 34 is exposed, and the first plug 350 and the second plug are respectively formed in the first, second and third via holes. 351 and a third plug 352 are formed.

Here, in the embodiment of the present invention, the first and second via holes and the first and second plugs 350 and 351 filling the metal pads 32 and the first electrodes to be formed subsequently are formed. However, omitting any one of the two plugs 350 and 351 does not significantly affect the operation of the capacitor manufactured according to the present invention. Therefore, the formation of any one of the first or second via holes can be omitted.

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Subsequently, a first hard mask layer 36 made of a nitride film or the like is formed on the third interlayer insulating layer 34 including the surfaces of the first to third plugs 350, 351, and 352.

Next, a fourth interlayer insulating layer 37 is formed on the first hard mask layer 36 with an intermetal dielectric (IMD) to insulate the metal wiring, and then the fourth interlayer insulating layer 37 The second hard mask layer 38 made of a nitride film or the like is formed on the surface of the wafer). Here, the first hard mask layer 26 and the second hard mask layer 38 may be formed of an insulating material having a high etching selectivity with the fourth interlayer insulating layer 37 and the third interlayer insulating layer 34.

Next, after the photoresist is applied on the second hard mask layer 38 again, the photoresist pattern is exposed and developed to form a photoresist pattern (not shown) exposing predetermined portions of the second hard mask layer. At this time, the surface of the second hard mask layer 38 exposed by the photoresist pattern, the first plug 350 and the second plug 351 to define the first electrode forming portion of the capacitor shown in FIG. While overlapping with and exposed in plan view to have a 'c' or 'S' shape, and at the same time to expose the fourth via hole forming portion overlapping the third plug 352. Here, in the embodiment of the present invention, the first electrode forming portion is defined in a 'c' or 'S' shape, but in addition, the first electrode is formed in various forms to maximize the surface area of the capacitor lower electrode such as a square. The site can be defined.

Next, the surface of the second hard mask layer of the portions not protected by the photoresist pattern is removed to expose certain portions of the fourth interlayer insulating layer. After removing the photoresist pattern, the exposed portions of the fourth interlayer insulating layer and the portions of the first hard mask layer below the portions are etched to define the portions where the first electrode is to be formed, thereby defining the first and second plugs 350. , And forming a trench for exposing the 351 and a fourth via hole for exposing the third plug 352.

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Next, a first metal layer 39 made of metal such as tungsten is formed on the trench and the fourth via hole surface at a thin thickness not completely covering the trench by a process such as sputtering, and then the first metal layer 39 is formed. The first insulating film 40 to be used as the first dielectric film is deposited thinly.

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Referring to FIG. 5B, after the photoresist is coated on the first insulating layer 40, the photoresist is exposed and developed to form a photoresist pattern 41 covering only a portion overlapping the trench on the layout. In this case, the photoresist pattern 41 may give a margin to the width so as to completely cover the trench.

Thereafter, the first insulating layer and the first metal layer under the portion not protected by the photoresist pattern 41 are sequentially etched to form the first electrode 390 and the first dielectric layer 400. At this time, the etching of the first insulating layer and the first metal layer proceeds to transient etching so that the upper surface of the third plug 352 is removed by removing the first insulating layer and the first metal layer formed in the fourth via hole V without remaining. To be exposed.

Referring to FIG. 5C, after removing the photoresist pattern by a method such as oxygen ashing, a second metal layer is deposited to completely fill the trench and the fourth via hole. Thereafter, the second metal layer CMP is formed to expose the second hard mask layer 38 to form a second electrode 420 filling the trench, and a fourth plug 421 is formed in the fourth via hole. In this case, the second electrode 420 and another second electrode 420 are actually one electrode connected to each other on the layout, and the fourth plug 421 formed in the fourth via hole is formed of the metal pad 32 and the first electrode. It is electrically connected via the three plug 352.

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In addition, as a result of the CMP, the surface of the second hard mask layer 38 and the upper surfaces of the first electrode 391, the first dielectric layer 401, the second electrode 420, and the fourth plug 421 are coplanar. It is located in the phase.

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Next, a second insulating film to be used as a second dielectric film is deposited on the substrate resultant, and then a third metal layer for forming third electrodes is formed on the second insulating film. In this case, the third metal layer may be formed by depositing a metal such as tungsten by a method such as sputtering.

Then, after the photoresist is applied on the third metal layer, the photoresist pattern 45 is formed by exposing and developing the photoresist. In this case, when the trench is formed in a 'c' shape when viewed in plan view, as shown in FIG. 3, the photoresist pattern 45 is partially offset in the right direction of the A-A 'line to be A-A'. It is formed in a shape that does not overlap with the left part of the line but overlaps only the remaining part.

Subsequently, the third metal layer and the second insulating film under the portion not protected by the photoresist pattern 45 are etched to form the third electrode 44 and the second dielectric film 43, and at the same time, the second The surface of the hard mask layer 38 and the upper surface of the fourth plug 421 are exposed.

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Here, the third electrode 44 and the first electrode 391 are formed to correspond to the second electrode 420 with the second dielectric film 43 and the first dielectric film 401 interposed therebetween, respectively. Will form.

5D and 5E, after the photoresist pattern is removed by an oxygen ashing method, an oxide film or the like is formed on the second hard mask layer 38 including the third electrode 44 and the fourth plug 421. The fifth interlayer insulating layer 46 is formed of an insulator.

Then, after the photoresist is applied on the fifth interlayer insulating layer 46, the photoresist is exposed and developed to expose the fifth and sixth via hole forming portions and the fourth plug 421 exposing the third electrode 44. A photoresist pattern (not shown) having openings exposing portions of the fifth interlayer insulating layer corresponding to the seventh via hole forming portion to be exposed are formed. In this case, the photoresist pattern is formed to have an opening that also exposes a fifth interlayer insulating layer portion corresponding to an eighth hole hole forming portion of a portion of the second electrode 420 that does not overlap with the third electrode 44.

Next, the fifth interlayer insulating layer of the portion not protected by the photoresist pattern is etched to expose the fifth and sixth via holes exposing the surface of the third electrode 44 and the seventh via holes exposing the fourth plug 421. And an eighth via hole exposing the second electrode 420. In this case, any one of the fifth and sixth via holes exposing the surface of the third electrode 44 may be omitted. That is, in the photoresist pattern forming step, one of the fifth and sixth via holes may not be formed by performing a subsequent process so as not to expose the fifth or sixth via hole forming portion. This is because the third electrodes 44 are illustrated as being separated from each other in the drawing, but are actually one electrode connected to each other in layout.

Then, in a state where the photoresist pattern is removed by a method such as oxygen ashing, a conductive layer such as tungsten is sputtered on the fifth interlayer insulating layer 46 to completely fill the fifth to seventh and eighth via holes. After the conductive layer is formed, the conductive layer is CMP to expose the surface of the fifth interlayer insulating layer 46, and at the same time, the fifth plug 470, the sixth plug 471, respectively, in the fifth to eighth via holes. The seventh plug 472 and the eighth plug 473 are formed.

Next, a conductive layer such as aluminum or tungsten is deposited on the fifth interlayer insulating layer 46 including the fifth to eighth plugs 470, 471, 472, and 473, and then patterned to form the fifth to eighth plugs. The seventh plugs 470, 471 and 472 form a rod-shaped first connector electrode 480 and a second connector electrode 481 connected to the eighth plug 473.

As a result, the third electrode 44 and the first electrode 391 are electrically connected to each other through the metal pad 32 and the first connection electrode 480, and the first dielectric film 401 and the second dielectric film ( It is formed so as to correspond to the second electrode 420 with the 43 interposed therebetween to have a capacitor structure consisting of a conductor / dielectric / conductor. That is, a capacitor having an upper electrode composed of the first electrode 391 and the third electrode 44 and a lower electrode composed of the second electrode 420 or the opposite structure is completed.

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As described above, the present invention uses the first electrode and the third electrode as one capacitor electrode, and uses the second electrode interposed between the dielectric film and the other electrode as the other capacitor electrode, the lower surface and the side surface of the second electrode. And by using most of the portion except the upper surface as the effective area of the capacitor, compared to the MIM capacitor of the flat plate structure can minimize the area occupied by the capacitor while providing an excellent capacitor in terms of increased capacitance. In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a conventional semiconductor device.

2 is a cross-sectional view of a metal-insulator-metal (MIM) capacitor of a conventional semiconductor device.

3 is a layout of a capacitor structure of a semiconductor device according to the present invention;

4A and 4B are cross-sectional views taken along lines II ′ and II-II ′ of FIG. 3.

5A through 5E are cross-sectional views of processes for describing a method of manufacturing a capacitor structure of a semiconductor device according to the present invention. * Explanation of symbols on the main parts of the drawings * 30: Silicon substrate 31: First interlayer insulating layer 32: Metal pad 33: Second interlayer insulating layer 34: Third interlayer insulating layer 36: First hard mask layer 37 Four interlayer dielectric layer 38 Second hard mask layer 39 First metal layer 40 First dielectric layer 41, 45 Photoresist pattern 43 Second dielectric layer 44 Third electrode 46 Interlayer dielectric layer 350 First plug 351: second plug 352: third plug 390, 391: first electrode 400,401: first dielectric film 420: second electrode 421: fourth plug 470: fifth plug 471: sixth plug 472: seventh plug 473: eighth plug 480: first connection electrode 481: second connection electrode

Claims (15)

First, second, third, and fourth insulating layers sequentially formed on the substrate; A trench formed in the fourth insulating layer; A first electrode formed on the trench surface; A first dielectric film formed on the first electrode; A second electrode formed to completely fill the trench on the first dielectric layer; A second dielectric film formed on the second electrode and the fourth insulating layer to expose a portion of the second electrode; A third electrode formed on the second dielectric film; A metal pad formed on the second insulating layer to be electrically connected to the first electrode; A fifth insulating layer formed on the substrate product to cover the third electrode; First and second connection electrodes formed on the fifth insulating layer to be electrically connected to the third and exposed second electrode portions, respectively; And And a plug formed in the third, fourth, and fifth insulating layers to electrically connect the first connector electrode and the metal pad, respectively. 2. The capacitor of claim 1, wherein the first electrode and the third electrode form one electrode of the capacitor, and the second electrode forms the other electrode of the capacitor, so as to form two capacitors through the first and second dielectric layers, respectively. A capacitor structure of a semiconductor device, characterized in that. The capacitor structure of claim 1, wherein the trench has a planar '-' shape. 2. The capacitor structure of claim 1, wherein a first hard mask layer and a second hard mask layer are formed on lower and upper surfaces of the third insulating layer, respectively. delete The capacitor structure of claim 1, wherein the trench has an 'S' shape in plan view. delete delete delete delete Sequentially forming a first insulating layer and a second insulating layer on the substrate; Forming a metal pad extending in a first direction in the second insulating layer; Forming a third insulating layer on the second insulating layer to cover the metal pad; Forming at least two first plugs and second plugs contacting predetermined portions of the metal pads at predetermined portions of the third insulating layer; Forming a fourth insulating layer to cover the first plug and the second plug; Etching the fourth insulating layer to form a trench to expose the first plug and to form a via hole to expose the second plug; Forming a first electrode in contact with the first plug on the trench surface; Forming a first dielectric film on the first electrode; Filling a metal film in the trench and the via hole to form a third plug in contact with the second electrode and the second plug, respectively; Forming a third electrode on the fourth insulating layer including the second electrode, the third electrode having a second dielectric film therebetween, overlapping most of the second electrode and exposing a portion thereof; Forming a fifth insulating layer on the substrate resultant; Forming fourth, fifth, and sixth plugs in the fifth insulating layer, the fourth, fifth, and sixth plugs contacting the third electrode, the third plug, and the second electrode, respectively; And Fabricating a capacitor structure of a semiconductor device, comprising forming a first connector electrode contacting the fourth and fifth plugs and a second connector electrode contacting the sixth plug on the fifth insulating layer. Way. 12. The method of claim 11, wherein the fourth insulating layer has a first hard mask layer and a second hard mask layer formed on its lower and upper surfaces, respectively. The method of claim 11, wherein the second electrode and the third plug are formed by a damascene process. 12. The method of claim 11, wherein the trench is formed to have a '-' shape in plan view. 12. The method of claim 11, wherein the trench is formed to have an 'S' shape in plan view.