KR20020065219A - Structure and layout of a capacitor in semiconductor devices and fabricating method thereof - Google Patents

Abstract

PURPOSE: A structure and a layout of a capacitor of a semiconductor device and a method for fabricating the same are provided to maximize an effective area of capacitance by improving the structure and the layout of the capacitor. CONSTITUTION: The first to the fifth interlayer dielectrics are laminated on a silicon substrate(30). The first trench is formed on the fourth interlayer dielectric. The first electrode(391) and the first dielectric layer(401) are formed on a surface of an inside of the trench. The first trench is buried by the second electrode(420). The third electrode(44) is formed on the fourth interlayer dielectric. The first and second connection electrodes(480,481) are formed on the fifth interlayer dielectric. The first connection electrode(480) is connected with the third electrode(44) through the fifth plug(470) and the sixth plug(471). The first connection electrode(480) is connected with the third plug contacted with a metallic pad layer(32) through the seventh plug(472) and the fourth plug(421). A lower surface of the first electrode(391) is connected electrically with the metallic pad layer(32) through the first and second plugs. The eighth plug(473) is formed on the fifth interlayer dielectric. The second connection electrode(481) is connected electrically with the second electrode(420). The third electrode(44) is electrically connected with the first connection electrode(480) by the fifth plug(470) and the sixth plug(471).

Description

Structure and layout of a capacitor in semiconductor devices and fabricating method

According to the present invention, when the metal wiring having the damascene structure is formed as the first electrode, the second electrode is formed to overlap the entire surface except for one side of the first electrode with the dielectric film interposed therebetween, thereby maximizing the capacitance effective area of the capacitor. The present invention relates to a capacitor structure, a layout, and a manufacturing method of a semiconductor device so as to contribute to an increase in device integration.

The MIM (metal-insulator-metal) capacitors used in the analog circuits of various graphics and multimedia devices, which occupy most of the merged DRAM and logic (MDL) devices, provide high capacitance with small series resistance and low thermal budget. Thermal budgets are widely used because of the high integration of the process.

MIM capacitors have low VCC and high precision mismatching characteristics compared to conventional polysilicon-insulator-polysilicon (PIP) capacitors. That is, the MIM capacitor is an analog capacitor and is formed of a metal having a high Q factor, almost no depletion as an electrode, and low resistance such as tungsten.

The analog capacitor of the prior art mainly uses a PIP flat plate structure, but since the high precision is required due to the high resistance of the polysilicon electrode itself, there is a limit to being used as an electrode material of a capacitor for an RF IC.

Therefore, a flat capacitor having a MIM structure using a metal electrode without depletion of the electrode itself and having a low resistance value has been developed.

In addition, as the degree of integration of semiconductor devices or devices increases greatly, a damascene process using copper or the like is mainly used in a technology for forming aluminum by etching aluminum.

However, the area occupied by the flat plate capacitor on the substrate is increased, including the case where the MIM capacitor is manufactured using a part of the metal wiring formed by the damascene process as the electrode of the capacitor, which is disadvantageous in reducing integration.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a semiconductor device according to the prior art.

Referring to FIG. 1, an insulating film 11 is formed on a silicon substrate 10, and a lower electrode 12 made of polysilicon doped on the insulating film 11 is patterned in a predetermined shape. In this case, the insulating film 11 may be a field oxide film.

On the surface of the lower electrode 12, a dielectric film 13 made of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed. Since the dielectric film 13 has a high dielectric constant value, it is possible to secure necessary capacitance even in a small area.

Next, a capacitor having a PIP structure is completed by polysilicon doped with the upper electrode 14 covering the upper surface and one side surface of the dielectric film 13 and extending to the upper surface of the insulating film 11.

However, the capacitor having such a structure is advantageous in securing capacitance, but is not easy to use due to the resistance of polysilicon in a device requiring high frequency operation, and is disadvantageous in terms of increasing the effective area since only one surface of the electrode is used as the effective area.

2 is a cross-sectional view of a metal-insulator-metal capacitor (MIM) of a semiconductor device according to the prior art.

Referring to FIG. 2, an insulating film 21 is formed on the silicon substrate 20, and a lower electrode 22 made of a metal such as tungsten is patterned on the insulating film 21 in a predetermined shape. In this case, the insulating film 21 may be a field oxide film.

On the surface of the lower electrode 22, a dielectric film 23 having a thickness thicker than that of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed on the surface of the MIM structure. However, the dielectric film 23 is thick, making it difficult to secure necessary capacitance.

Next, the upper electrode 24 covering the upper surface and one side surface of the dielectric film 23 and extending to the upper surface of the insulating film 21 is made of a metal material such as tungsten to complete the capacitor of the MIM structure.

However, a capacitor having such a structure is advantageous in a device requiring high frequency operation, but is disadvantageous due to a thick dielectric film for securing capacitance, and also disadvantages in terms of increasing an effective area since only one surface of the electrode is used as an effective area.

As described above, in the prior art, PIP structure capacitors are disadvantageous in high frequency operation, and MIM structure capacitors have difficulty in securing required capacitance.

Accordingly, an object of the present invention is to form a second electrode with a damascene structure as a first electrode to form a second electrode overlapping the entire surface except the one side of the first electrode with a dielectric film interposed therebetween The present invention provides a capacitor layout of a semiconductor device that maximizes the effective area and contributes to an increase in device integration.

In addition, another object of the present invention is to form a metal wire of the damascene structure as the first electrode to form a second electrode so as to overlap the entire surface except the one side of the first electrode with a dielectric film interposed therebetween The present invention provides a capacitor structure of a semiconductor device that maximizes the capacity effective area and contributes to an increase in device integration.

It is still another object of the present invention to form a metal wiring having a damascene structure as a first electrode so that the second electrode is formed so as to overlap the entire surface except for one side of the first electrode with a dielectric film interposed therebetween. The present invention provides a method of manufacturing a capacitor of a semiconductor device that maximizes the effective area and contributes to an increase in device integration.

A capacitor layout of a semiconductor device according to the present invention for achieving the above object is a trench having a '-' shape formed by removing a predetermined portion of the first insulating layer formed on the substrate, and the first formed on the inner surface of the trench An electrode and a first dielectric layer, a second electrode buried in the trench, and a second electrode formed on the first dielectric layer, the second electrode being offset from the second electrode so as to overlap the trench except the upper left surface of the second electrode. A third electrode formed on the first insulating layer and spaced apart from the second electrode by a predetermined distance; a first conductive layer pad formed on the first insulating layer; and a first conductive layer pad, a second electrode, and a third electrode formed on the first insulating layer. A second insulating layer formed on the first insulating layer including an electrode, and formed on the second insulating layer to electrically connect the first conductive layer pad and the third electrode; A large first connection electrode, a second connection electrode formed on the second insulating layer to be electrically connected to the second electrode which does not overlap the third electrode, the first conductive layer pad and the first electrode; And a second conductive layer pad formed to be electrically connected to the first conductive layer pad and a predetermined portion of the first insulating layer under the first electrode.

The capacitor structure of the semiconductor device according to the present invention for achieving the above objects is formed in the form of a single curved line on a predetermined portion of the first to fourth interlayer insulating layer and the third interlayer insulating layer formed on the substrate in order A trench, a first electrode formed only on the inner surface of the trench, a first dielectric film formed on the first conductive layer, a second electrode formed on the first dielectric film to completely fill the trench, and the first electrode; A second dielectric layer covering surfaces of the first dielectric layer and the second electrode but not formed on a part of the upper surface of the second electrode, a third electrode covering the second dielectric layer, and the second interlayer dielectric layer; A metal pad layer formed on the first interlayer insulating layer so as to be electrically connected to the first electrode, and penetrated through the fourth interlayer insulating layer and electrically connected to the third electrode. A first connecting electrode, a plug penetrating the fourth to second interlayer insulating layers and electrically connecting the first connecting electrode and the metal pad layer, and a second dielectric layer are formed through the fourth interlayer insulating layer. And a second connection electrode formed on the fourth interlayer insulating layer to be electrically connected to the second electrode which is not formed.

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device, the method including: forming a first insulating layer on a substrate and forming a metal layer pad running in a first direction on the first insulating layer; Forming a second insulating layer on the first insulating layer to sufficiently cover the at least one second insulating layer; and removing at least one portion of the second insulating layer to expose a predetermined portion of the metal layer pad to expose at least two first via holes and the second. Forming a via hole, forming a first plug and a second plug to fill the first to second via holes with a conductor, and forming a third insulating layer covering the first to second plugs; Removing a predetermined portion of the third insulating layer to form a trench-shaped trench that exposes the first plug, and simultaneously expose the surface of the second plug. Forming a third via hole, sequentially forming a first electrode and a first dielectric layer only on the inner surface of the trench so as not to completely fill the trench; and filling the trench to completely fill the trench and fill the third via hole. Simultaneously forming a second metal layer on the first dielectric layer and the third via hole to form a second electrode and a third plug, respectively, overlapping most of the upper surface of the second electrode, and forming a predetermined portion of the second electrode. Sequentially forming a second dielectric layer and a third electrode on the trench so as not to partially overlap, forming a fourth insulating layer on the third insulating layer including the third electrode, and forming the fourth insulating layer. At least one fourth via hole exposing a third electrode surface by removing a predetermined portion of the layer and a fifth via hole exposing the third plug Forming a sixth via hole exposing a predetermined portion of the second electrode which does not overlap with the third electrode, filling the fourth to fifth via holes and electrically connecting the third electrode and the third plug; And forming a first connection electrode on the fourth insulating layer and forming a second connection electrode on the fourth insulating layer to fill the sixth via hole.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a semiconductor device according to the prior art

2 is a cross-sectional view of a metal-insulator-metal capacitor of a semiconductor device according to the related art.

3 is a layout of a MIM capacitor of a semiconductor device according to the present invention.

4A through 4E are cross-sectional views illustrating a method of manufacturing a MIM capacitor in a semiconductor device according to the present invention.

5A to 5B are cross-sectional views taken along cut lines I-I 'and II-II of FIG. 3, respectively, of a MIM capacitor structure of a semiconductor device according to the present invention.

The present invention relates to a capacitor required for a semiconductor device such as a filter, a voltage controlled oscillator (VCO) using a damascene process.

In the present invention, when the metal wiring is formed by using the damascene process, a part of the metal wiring formed by the damascene process is used as the first electrode of the capacitor, and an insulating film is formed on the upper, lower and most side surfaces of the first electrode. Since the metal thin film is deposited on the surface and used as the second electrode, the area occupied by the capacitor is minimized and the capacitance is maximized as compared with the conventional flat panel MIM capacitor.

Accordingly, since the MIM capacitor according to the present invention uses most of the side surfaces including the upper and lower surfaces of the metal wirings used as the first electrodes for the effective area, the integration of the semiconductor device is greatly improved because the MIM capacitor is secured in the area where the same capacitance is minimized.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 shows a MIM capacitor layout of a semiconductor device according to the present invention.

Referring to FIG. 3, a first interlayer insulating layer (not shown) to a fifth interlayer insulating layer (not shown) are sequentially formed on a silicon substrate 30, which is a semiconductor substrate.

A first trench having a 'c' shape is formed in the fourth interlayer insulating layer, and a first electrode 391 and a first dielectric layer 401 are formed on the inner surface of the trench to have a predetermined thickness, and the remaining first trench portions are formed. 2 electrodes 420 are embedded.

In addition, on the fourth interlayer insulating layer, the third electrode 44 interposed between the second dielectric layer (not shown) does not overlap with the left portion of the 'I' portion of the second electrode 420 having a 'C' shape. Without overlapping the right portion of the 'I' portion and the remaining portion of the 'c'.

Next, on the fifth interlayer insulating layer, the first connecting electrode 480 and the second connecting electrode 481 are formed to be spaced apart from each other.

In this case, the first connection electrode 480 is connected through the fifth plug 470 and the sixth plug 471 through the fifth interlayer insulating layer and in contact with the third electrode 44. 472 and a fourth plug 421 are electrically connected to the third plug 352 penetrating the third interlayer insulating layer and in contact with the metal pad layer 32.

In addition, the lower surface of the first electrode 391 is electrically connected to the metal pad layer 32 through first to second plugs 350 and 351 formed on the third interlayer insulating layer.

Meanwhile, an eighth plug 473 in electrical contact with the upper surface of the second electrode 420 that does not overlap the third electrode 44 is formed in the fifth interlayer insulating layer, so that the second connection electrode 481 is formed. And the second electrode 420 are electrically connected.

Since the fifth plug 470 and the sixth plug 471 are for electrically connecting the third electrode 44 and the first connection electrode 480, one of the two plugs 470 and 471 may be omitted. Also, the operation of the capacitor element is not affected.

Although not shown in the layout, any one of the two plugs may be omitted since the first plug and the second plug are also for electrically connecting the first electrode 391 with the metal pad layer 32. .

4A to 4E are process cross-sectional views illustrating a method of manufacturing a MIM capacitor of a semiconductor device according to the present invention. FIGS. 4A to 4D are process diagrams along the cutting line I-I 'of FIG. 3, and FIG. 4E is a process step of FIG. 4D. 3 is a process view taken along the cut line II-II 'of FIG. 3.

Referring to FIG. 4A, a first interlayer insulating layer 31 for insulation is formed on an silicon substrate 30, which is a semiconductor substrate, using an insulator such as an oxide film, and then a first metal layer is deposited thereon, followed by photolithography. The metal pad layer 32 including the remaining first metal layer 32 is formed by patterning. At this time, the layout of the metal pad layer 32 is formed to have a form that can be electrically connected to the first electrode and the third electrode of the capacitor to be formed in a subsequent process, in the embodiment of the present invention cut line I-I of FIG. Has a rectangular shape around the center.

Then, the second interlayer insulating layer 33 is formed on the first interlayer insulating layer 31 so as to cover the metal pad layer 32, and then the CMP (chemical mechanical polishing) or the like is formed on the second interlayer insulating layer 33. The planarization process is performed to expose the surface of the metal pad layer 32, and then the third interlayer insulating layer 34 is deposited on the exposed metal pad layer 32 and the second interlayer insulating layer 33 by an oxide film or the like. It is formed by depositing. In this case, the second interlayer insulating layer 33 and the third interlayer insulating layer 34 may be deposited at the same time, and then may be planarized by CMP.

Next, anisotropic etching such as dry etching is performed on the third interlayer insulating layer 34 to form first to third via holes exposing predetermined portions of the metal pad layer 32. In this case, the first to third via holes are formed by the following method. First, after the photoresist is applied on the third interlayer insulating layer 34, exposure and development are performed to be spaced apart at predetermined intervals along the cutting line I-I ′ of the layout of FIG. 3 and the metal pad layer 34. After forming a photoresist pattern (not shown) having openings each exposing the surfaces of the overlapping third interlayer insulating layers, the exposed third interlayer insulating layer is removed by anisotropic etching such as dry etching to form a metal pad layer ( The first through third via holes exposing the surface of 32) are formed.

Therefore, the first via hole and the second via hole become the first plug 350 and the second plug 351 forming portion electrically connecting the first electrode and the metal pad layer 32 formed in a subsequent process, and the third via hole The via hole is a forming portion of the third plug 352 that electrically connects the metal pad layer 32 and the third electrode.

In the embodiment of the present invention, the first and second via holes and the first and second plugs filling the first and second via holes are formed to electrically connect the first electrode and the metal pad layer 32, but any one of the two plugs is omitted. Even if there is no significant effect on the operation of the capacitor produced according to the present invention. Therefore, the formation of any one of the first and second via holes can be omitted.

After removing the photoresist pattern by a method such as oxygen ashing (O ₂ ahing), and then forming a conductive layer of a metal such as tungsten on the third interlayer insulating layer 34 to sufficiently fill the first to third via holes, CMP The first plug 350, the second plug 351, and the third plug 352 remaining only in the first to third via holes are formed by exposing the surface of the third interlayer insulating layer 34 by a method such as the above. .

The first hard mask layer 36 is formed of a nitride film or the like on the third interlayer insulating layer 34 including the surfaces of the first to third plugs 350, 351, and 352.

Next, a fourth interlayer insulating layer 37 is formed on the first hard mask layer 36 with an intermetal dielectric (IMD) for insulation between metal lines to a predetermined thickness, and then the fourth interlayer insulating layer is formed. On the layer 37, a second hard mask layer 38 is formed of a nitride film or the like. The first hard mask layer 26 and the second hard mask layer 38 may be formed of an insulating material having a high etching selectivity with the fourth interlayer insulating layer 37 and the third interlayer insulating layer 34.

Then, the photoresist is applied on the second hard mask layer 38 again, and then the steel sheet and the developer are formed to form a photoresist pattern (not shown) that exposes a predetermined portion of the second hard mask layer. In this case, the surface of the second hard mask layer 38 exposed by the photoresist pattern is first overlapped with the first plug 350 and the second plug 351 to define the first electrode forming portion of the capacitor. It is exposed to have a ruler or 'S' shape and at the same time to expose the fourth via hole forming portion overlapping the third plug 352. In this case, in the embodiment of the present invention, the first electrode forming portion is defined in the form of 'c' or 's', but in addition, the first electrode forming portion may be manufactured in various forms to maximize the surface area of the capacitor lower electrode such as a square. Of course.

Next, the surface of the second hard mask layer of the portion not protected by the photoresist pattern is removed to expose a predetermined portion of the fourth interlayer insulating layer, and then the photoresist pattern is removed.

The first trench and the fourth via hole defining a portion where the first electrode is to be formed by removing the fourth interlayer insulating layer which is not protected by the remaining second hard mask layer 38 by anisotropic etching such as dry etching. Form.

Next, the first hard mask layer exposed by the first trench and the fourth via hole is removed to expose the surfaces of the first to third plugs 350, 351, and 352.

Then, the first metal layer 39 is formed of a metal such as tungsten to a thickness that covers the inner surface of the first trench and the fourth via hole thinly and does not completely melt. In the above, the first metal layer 39 may be formed by depositing a metal such as tungsten by sputtering, and the first metal layer 39 is then patterned to form a first electrode of the capacitor.

Next, a first insulating film 40 to be used as the first dielectric film of the first electrode is formed by covering the first metal layer 39.

Referring to FIG. 4B, a photoresist is applied on the first insulating film 40 to be used as the dielectric film, followed by exposure and development to form a photoresist pattern (not shown) covering only portions overlapping the first trenches in the layout. . In this case, the photoresist pattern may give a margin to the width of the photoresist pattern so as to completely cover the first trench.

The surface of the second hard mask layer 38 is exposed by sequentially removing the first insulating film and the first metal layer at portions not protected by the photoresist pattern. At this time, the upper surface of the third plug 352 is completely exposed by performing excessive etching so that the first insulating film and the first metal layer remaining in the fourth via hole V do not remain.

Referring to FIG. 4C, after removing the photoresist pattern by a method such as oxygen ashing, the second metal layers 420 and 421 are made of a second hard layer using a conductive layer such as metal so as to completely fill the first trench and the via hole in which the first insulating film remains. It is formed on the mask layer 38. In this case, the second metal layers 420 and 421 may be formed of copper by a damascene process.

Then, a planarization process such as CMP is performed on the second metal layer to form a second electrode 420 made of the second metal layer remaining in the first trench. In this case, the second electrode 420 and another second electrode 420 become one electrode actually connected to each other on the layout, and the fourth plug 421 made of the second metal layer remaining in the fourth via hole is a metal pad layer. Electrically connected via the 32 and the third plug 352.

Accordingly, in the first trench, the first insulating layer 311 having the first electrode 391 made of the remaining first metal layer 391 and the second electrode 420 made of the remaining second metal layer 420 remaining therebetween The first dielectric layer 401, which is 401, is positioned to be interposed therebetween.

In addition, as a result of the planarization process such as CMP, the surface of the second hard mask layer 38 and the upper surface of the first electrode 391, the first dielectric layer 401, the second electrode 420, and the fourth plug 421. Is located on the same plane.

A second insulating film to be used as the second dielectric film is deposited on the planarized plane of the substrate, and then a third metal layer for forming third electrodes is formed on the second insulating film. In this case, the third metal layer may be formed by depositing a metal such as tungsten by a method such as sputtering.

Subsequently, after the photoresist is applied on the third metal layer, exposure and development are performed to form the first trench in the 'c' shape, the first trench is partially offset to the right side of the 'I' portion of the first trench. As a result, a photoresist pattern 45 is formed that does not overlap a portion of the left portion of the first trench but overlaps the remaining portion.

The third metal layer and the second insulating layer which are not protected by the photoresist pattern 45 are removed to expose the surface of the second hard mask layer 38 and the upper surface of the fourth plug 421.

Accordingly, the remaining third metal layer 44 becomes the third electrode 44, and the second dielectric layer 43 made of the second insulating layer 43 remaining between the third electrode 44 and the second electrode 420. ) Is located.

Therefore, in the subsequent process, the third electrode 44 and the first electrode 391 are formed to correspond to the second electrode 420 with the second dielectric film 43 and the first dielectric film 401 interposed therebetween. Will form.

4D and 4E, the photoresist pattern is removed by an oxygen ashing method, and then an oxide film is formed on the second hard mask layer 38 including the surface of the third electrode 44 and the fourth plug 421. The fifth interlayer insulating layer 46 is formed of an insulator such as an insulator.

After the photoresist is applied on the fifth interlayer insulating layer 46, the fifth and sixth via hole forming portions overlapping the upper surface of the third electrode 44 and the fourth plug 421 overlap each other. A plurality of exposed portions of the fifth interlayer insulating layer 46 corresponding to the eighth via hole forming portion overlapping with the seventh via hole forming portion and the upper surface of the second electrode 420 not overlapping with the third electrode 44. A photoresist pattern (not shown) having two openings is formed.

In addition, the fifth and sixth via holes and the fourth plugs 421 exposing the surface of the third electrode 44 by removing the fifth interlayer insulating layer, which is not protected by the photoresist pattern, by anisotropic etching such as dry etching. After forming the seventh via hole exposing the surface of the ()) and the eighth via hole exposing the surface of the second electrode 420, the photoresist pattern is removed by a method such as oxygen ashing. In this case, any one of the fifth via hole and the sixth via hole exposing the surface of the third electrode 44 may be omitted. That is, when the subsequent process is performed without exposing the fifth via hole or the sixth via hole forming portion in the photoresist pattern forming step, one of the fifth via hole and the sixth via hole may not be formed. This is because the third electrodes 44 are shown as if they are separated from each other in the drawing, but are actually one electrode connected to each other in layout.

Then, a conductive layer such as tungsten is formed on the fifth interlayer insulating layer 46 by sputtering or the like so as to completely fill the fifth to seventh via holes and the eighth via holes, and then planarization process such as CMP is performed. The fifth plug 470, the sixth plug 471, and the seventh plug made of the conductive layer remaining by exposing the surface of the fifth interlayer insulating layer 46 and remaining the conductive layer only inside the fifth to eighth via holes. 472 and an eighth plug 473 are formed.

Then, a conductive layer such as aluminum or tungsten is deposited on the fifth interlayer insulating layer 46 including the surfaces of the fifth to eighth plugs 470, 471, 472 and 473, and then patterned by photolithography to form the fifth to seventh plugs 470, 471, 472. ) To form a rod-shaped first connector electrode 480 and a second connector electrode 481 connected to the eighth plug 473.

Accordingly, the first electrode 391 and the third electrode 44 are electrically connected to each other through the metal pad layer 32 and the first connection electrode 480, and the first dielectric layer 401 and the second dielectric layer 43 ) Is formed so as to correspond to the second electrode 420 with the interposition between the two electrodes 420 and has a capacitor structure consisting of a conductor / dielectric / conductor.

That is, a capacitor having an upper electrode composed of the first electrode 391 and the third electrode 44 and a lower electrode composed of the second electrode 420 or the reverse structure thereof is completed.

5A to 5B are cross-sectional views taken along cut lines I-I 'and II-II of FIG. 3, respectively, of the MIM capacitor structure of the semiconductor device according to the present invention.

5A and 5B, first to fifth interlayer insulating layers 31, 33, 34, 37, and 46 are sequentially stacked on a silicon substrate 30, which is a semiconductor substrate. A first hard mask layer 36 is interposed between the third interlayer insulating layer 34 and the fourth interlayer insulating layer 36, and between the fourth interlayer insulating layer 37 and the fifth interlayer insulating layer 46. The second hard mask layer 38 is interposed.

The first hard mask layer 36, the fourth interlayer insulating layer 37, and the second hard mask layer 38 are formed with a first trench having a 'c' shape in layout, thereby forming an inner surface of the first trench. The first electrode 391 and the first dielectric film 401 are sequentially formed in a predetermined thickness, and the second electrode 420 is filled with the remaining first trench portions. In this case, the second electrode 420 may be formed by a damascene process using copper for forming another wiring.

On the second mask layer 38, the third electrode 44 with the second dielectric layer 43 interposed therebetween is disposed on the left side of the 'I' portion of the second electrode 420 having a 'c' shape. It is formed so as not to overlap with the right portion of the 'I' portion and the remaining portion of the 'c'.

Next, the first connection electrode 480 and the second connection electrode 481 are formed on the fifth interlayer insulating layer 46 so as to be spaced apart from each other.

In this case, the first connection electrode 480 is connected through the fifth plug 470 and the sixth plug 471 through the fifth interlayer insulating layer 46 and in contact with the third electrode 44. The seventh plug 472 and the fourth plug 421 are electrically connected to the third plug 352 penetrating through the third interlayer insulating layer 34 and in contact with the metal pad layer 32.

In addition, the lower surface of the first electrode 391 is electrically connected to the metal pad layer 32 through the first to second plugs 350 and 351 formed on the third interlayer insulating layer 34. In this case, a third plug 352 is formed on the third interlayer insulating layer 34 to electrically connect the fourth plug 421 and the metal pad layer 32.

Meanwhile, an eighth plug 473 is formed on the fifth interlayer insulating layer 46 to be in electrical contact with the upper surface of the second electrode 420 that does not overlap with the third electrode 44. The 481 and the second electrode 420 are electrically connected to each other.

Since the fifth plug 470 and the sixth plug 471 are for electrically connecting the third electrode 44 and the first connection electrode 480, one of the two plugs 470 and 471 may be omitted. Also, the operation of the capacitor element is not affected.

In addition, although not shown in the layout, the first plug 350 and the second plug 351 are also used to electrically connect the first electrode 391 with the metal pad layer 32. May be omitted.

Accordingly, the present invention uses the first electrode and the third electrode as one electrode on the substrate, and the lower electrode, the side surface, and the upper surface of the second electrode using the second electrode with the dielectric film interposed therebetween as the other electrode. Since most of them use the effective area of the capacitor except for a part of, there is an advantage of providing a capacitor which is superior in capacitance increase compared to the MIM capacitor of the flat plate structure.

Claims (15)

First to fourth interlayer insulating layers sequentially formed on the substrate, A trench formed in a planar shape on a predetermined portion of the third interlayer insulating layer; A first electrode formed only on the trench inner surface; A first dielectric layer formed on the first conductive layer, A second electrode formed on the first dielectric layer and completely filling the trench; A second dielectric layer covering surfaces of the first electrode, the first dielectric layer, and the second electrode, the second dielectric layer not being formed on a part of the upper surface of the second electrode; A third electrode covering the second dielectric layer; A metal pad layer formed on the first interlayer insulating layer to be electrically connected to the first electrode through the second interlayer insulating layer; A first connector electrode penetrating the fourth interlayer insulating layer and electrically connected to the third electrode; A plug penetrating the fourth to second interlayer insulating layers and electrically connecting the first connection electrode and the metal pad layer; A capacitor structure of the semiconductor device comprising a second connection electrode formed on the fourth interlayer insulating layer to penetrate the fourth interlayer insulating layer and to be electrically connected to the second electrode on which the second dielectric layer is not formed; The method according to claim 1, Wherein the first electrode and the third electrode form one electrode of the capacitor, and the second electrode forms the other electrode of the capacitor to form a capacitor element interposed between the first and second dielectric layers. rescue. The method according to claim 1, The open curve is a capacitor structure of the semiconductor device characterized in that the '' 'shape. The method according to claim 1, And a first hard mask layer and a second hard mask layer respectively disposed on lower and upper surfaces of the third interlayer insulating layer. The method according to claim 1, And a portion of the plug and the second electrode are formed of the same material and formed on the third interlayer insulating layer. The method according to claim 1, The open curve is a capacitor structure of the semiconductor device characterized in that the 'S' shape. A trench having a 'c' shape formed by removing a predetermined portion of the first insulating layer formed on the substrate, A first electrode and a first dielectric layer sequentially formed on an inner surface of the trench; A second electrode buried in the trench and formed on the first dielectric layer; A third electrode which is offset from the second electrode so as to overlap the trench except for the upper left surface of the second electrode and is formed on the second electrode with a second dielectric layer interposed therebetween; A first conductive layer pad spaced apart from the second electrode by a predetermined distance and formed on the first insulating layer; A second insulating layer formed on the first insulating layer including the first conductive layer pad, the second electrode, and the third electrode; A rod-shaped first connector electrode formed on the second insulating layer to electrically connect the first conductive layer pad and the third electrode; A second connection electrode formed on the second insulating layer to be electrically connected to the second electrode not overlapping with the third electrode; The semiconductor device includes a first conductive layer pad and a second conductive layer pad long formed at a predetermined portion of the first insulating layer under the first electrode to electrically connect the first conductive layer pad and the first electrode. Capacitor layout. The method according to claim 7, The second conductive layer pad and the first connecting electrode are connected through a first contact, the third electrode and the first connecting electrode are connected through a second contact, and the first electrode and the second conductive layer are connected to each other. The pad is connected through a third contact overlapping the second contact, and the second connection electrode is formed at a portion overlapping a predetermined portion of the second electrode that does not overlap with the second electrode and the third electrode. A capacitor layout of a semiconductor device characterized by being connected via four contacts. The method according to claim 7, The third electrode is a capacitor layout of the semiconductor device, characterized in that formed to have a planar structure of the '' 'shape partially overlapping the second electrode. The method according to claim 7, The trench is a capacitor layout of the semiconductor device, characterized in that the 'S' shape instead of the '' '. Forming a first insulating layer on the substrate and forming a metal layer pad running in a first direction on the first insulating layer; Forming a second insulating layer on the first insulating layer so as to cover the metal layer pad sufficiently; Removing at least one portion of the second insulating layer to form at least two first via holes and second via holes exposing a predetermined portion of the metal layer pad; Forming a first plug and a second plug to fill the first to second via holes with a conductor; Forming a third insulating layer covering the first to second plugs, Removing a predetermined portion of the third insulating layer to form a trench in the form of a curved line exposing the first plug and forming a third via hole exposing the surface of the second plug; Sequentially forming a first electrode and a first dielectric layer only on the inner surface of the trench so as not to completely fill the trench; Simultaneously forming a second metal layer on the first dielectric layer and the third via hole to completely fill the trench and fill the third via hole, respectively, forming a second electrode and a third plug; Sequentially forming a second dielectric layer and a third electrode on the trench so as to overlap most of the upper surface of the second electrode but not partially overlap with a predetermined portion of the second electrode; Forming a fourth insulating layer on the third insulating layer including the third electrode; At least one fourth via hole exposing a surface of the third electrode by removing a predetermined portion of the fourth insulating layer and a fifth via hole exposing the third plug and the second electrode not overlapping with the third electrode. Forming a sixth via hole exposing the predetermined region; A first connection electrode is formed on the fourth insulating layer to fill the fourth to fifth via holes and electrically connects the third electrode and the third plug to the fourth insulating layer to fill the sixth via hole. A method for manufacturing a capacitor of a semiconductor device comprising the step of forming a second connection electrode. The method according to claim 11, After forming the first via hole and the second via hole, And forming a first hard mask layer and a second hard mask layer on the lower and upper surfaces of the third insulating layer, respectively. The method according to claim 11, And said second electrode and said third plug are formed by a damascene process. The method according to claim 11, The trench of claim 1, wherein the trench is formed in a planar 'c' shape. The method according to claim 11, The trench of claim 1, wherein the trench has a planar 'S' shape.