JP3153802B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the degree of integration of a semiconductor memory device has been increased, and each element constituting the semiconductor memory device has become extremely fine, and accordingly, each element has been arranged very close. DRA having a general stacked memory cell structure
Taking M as an example, the manufacturing process has a flow of sequentially forming an active region and an element isolation region, a word line (gate electrode), a bit line, and a memory cell capacitor on a semiconductor substrate. Hereinafter, a conventional method of manufacturing a semiconductor memory device will be described with reference to FIGS. 20 to 23 by taking a manufacturing process of a DRAM having a stacked memory cell structure as an example.

First, in a process shown in FIGS. 20A and 20B, a laminated film 302 of a silicon nitride film and a silicon oxide film is formed on a semiconductor substrate (silicon substrate) 301, and a photoresist 303 is used. Laminated film 304 of silicon nitride film and silicon oxide film and semiconductor substrate 3 by photolithography
05 is removed to form a groove 306.

Next, in the steps shown in FIGS. 20C, 20D and 20E, after depositing a CVD silicon oxide film 307, the stacked film 304 of silicon nitride film and silicon oxide film and silicon By removing a part of the oxide film 307, the entire surface is flattened and the buried film 310 is left in the groove 309. Subsequently, all of the stacked film 308 of the silicon nitride film and the silicon oxide film and the buried film 310 are wet-etched. Of the buried film 311
While leaving the semiconductor substrate surface 312 exposed.

Next, in the steps shown in FIGS. 21A and 21B, a gate oxide film 313 and a polysilicon film 314 containing impurities are sequentially formed, and a gate electrode is formed by photolithography using a photoresist 315. (Word line) 316 is formed. Next, in the step shown in FIG.
7, an impurity diffusion layer 318 is formed.

Next, in the steps shown in FIGS. 21D and 22A, a CVD silicon oxide film 319 is deposited and planarized, and then a contact hole 321 is formed by photolithography using a photoresist 320. Open. Next, FIG.
In the step shown in FIG. 2B, a bit line 322 is formed by photolithography after depositing a laminated film 322 of tungsten silicide and polysilicon containing impurities.

Next, in the steps shown in FIGS. 22C and 22D, a CVD silicon oxide film 323 is deposited and flattened, and then a contact hole 325 is opened by photolithography using a photoresist 324. . Next, FIG.
In the steps shown in FIGS. 3A and 3B, a polysilicon film 326 containing impurities is deposited, and a charge accumulation electrode 328 is formed by photolithography using a photoresist 327.

Next, in a step shown in FIG. 23C, a capacitor insulating film 329 composed of a laminated film of a silicon oxide film and a silicon nitride film, and a polysilicon film 330 containing impurities are sequentially formed. A plate electrode 330 is formed.

[0009]

However, in the conventional semiconductor memory device, the gate electrode 316 and the bit line 3
Since the conductive layers 22, the charge storage electrode 328, and the plate electrode 330 are all provided on the semiconductor substrate, a short circuit between the conductive layers may occur if the width of the isolation region between each element or the thickness of the insulating film decreases with the increase in integration. Was likely to occur.

In order to ensure insulation between the upper and lower conductive layers, it is necessary to increase the thickness of the insulating film between the upper and lower conductive layers. Accordingly, the upper conductive layer is connected to the semiconductor substrate. There has been a problem that the depth of the connection hole is increased, the aspect ratio is increased, the state of covering the inside of the connection hole with the conductive layer is deteriorated, and poor electrical connection occurs in the connection hole.

The present invention solves the above-mentioned problem,
Forming a gate electrode in a semiconductor substrate reduces the occurrence of short circuits between conductive layers, improves the electrical connection in connection holes between the semiconductor substrate and the conductive layers, further reduces the number of manufacturing steps, and reduces manufacturing costs. It is an object to provide a storage device and a manufacturing method thereof.

[0012]

According to another aspect of the present invention, there is provided a semiconductor memory device, comprising: a semiconductor substrate; and a first impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed on the semiconductor substrate. A layer, a first opening formed by removing a part of the semiconductor substrate, a buried layer formed of an insulating film formed in the first opening, and removing a part of the buried layer. A second opening formed in the second opening, a gate electrode formed in the second opening, and a conductive material opposite to the semiconductor substrate formed on a part of a side wall and a bottom surface of the first opening. A second impurity diffusion layer of the same type as the semiconductor substrate formed below the second opening, and a second impurity diffusion layer of the same conductivity type as the semiconductor substrate formed under the second opening. Separated by a third impurity diffusion layer ,
An insulating film formed on the semiconductor substrate and a conductive film
And a charge storage electrode of a conductive film.
The connection between the conductor and the surface of the semiconductor substrate is performed by opening the insulating film.
The bit line and the semiconductor substrate surface
The first connection hole penetrating between the
The connection between the storage electrode and the surface of the semiconductor substrate is made by the insulating film
The charge storage electrode and the semiconductor substrate formed by opening
It is characterized in that it is performed by a second connection hole penetrating between the plate surface .

According to the semiconductor memory device as described above, since the gate electrode is provided in the semiconductor substrate, a short circuit between the gate electrode and another conductive layer is less likely to occur, and the reliability of the semiconductor memory device is improved. it can. Further, since the depth of the connection hole between the conductive layer above the gate electrode and the semiconductor substrate can be made shallower, the inside of the connection hole of the conductive layer can be covered well, and electrical connection failure of the conductive layer in the connection hole can be prevented. ,
The reliability of the semiconductor memory device can be improved. Further, the threshold voltage of the switching transistor of the memory cell can be reliably controlled. That is, even when the semiconductor memory device is further miniaturized, the impurity diffusion layers of the conductivity type opposite to the semiconductor substrate are separated by the impurity diffusion layers of the same conductivity type as that of the semiconductor substrate. When the impurity diffusion layer is used for the source and the drain, ON / OFF of the switching transistor can be controlled by the gate voltage.

It is preferable that an insulating film is formed between the bottom surface of the second opening and the gate electrode.
Further, it is preferable that a plate electrode of a conductive film is formed on the charge storage electrode and the insulating film via a capacitance insulating film.

Further, it is preferable that the bit line is formed between the semiconductor substrate and the plate electrode. Preferably, the bit line is formed on the plate electrode via an insulating film.

Further, it is preferable that a connection hole connecting the bit line and the semiconductor substrate passes between the adjacent plate electrodes. According to the above-described semiconductor memory device, the connection hole for connecting the bit line and the semiconductor substrate is secured in the pattern of the plate electrode, so that the semiconductor memory device can be highly integrated.

Further, the depth of the first opening is the first opening.
Is preferably deeper than the depth of the impurity diffusion layer. According to the semiconductor memory device as described above, reliable insulation between memory cells having a switching transistor having a gate electrode disposed inside a semiconductor substrate can be achieved.

The semiconductor device may further include a third opening formed by removing a part of the semiconductor substrate, wherein the gate electrode is not formed in the third opening and the buried layer is buried. Preferably, the buried layer in the third opening forms an isolation region.

The depth of the third impurity diffusion layer is:
It is preferable that the depth is greater than the depth of the second impurity diffusion layer. According to the semiconductor memory device as described above, the impurity diffusion layer of the conductivity type opposite to that of the semiconductor substrate can be reliably separated by the impurity diffusion layer of the same conductivity type as the semiconductor substrate.

It is preferable that the first and second impurity diffusion layers are a source or a drain of a switching transistor of a memory cell, and the gate electrode is a gate electrode of a switching transistor of the memory cell. According to the semiconductor memory device as described above, since the depth of the connection hole between the bit line and the semiconductor substrate and the depth of the connection hole between the charge storage electrode and the semiconductor substrate are reduced, the bit line material inside the connection hole is reduced. And the state of covering of the charge storage electrode material is improved, electrical connection failure in the connection hole is prevented, and the reliability of the semiconductor memory device can be improved.

Next, in the method of manufacturing a semiconductor memory device according to the present invention, a step of forming a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate on the semiconductor substrate; Forming a plurality of first openings by locally removing the first insulating film and the semiconductor substrate by photolithography after forming the insulating film, and forming a second opening on the semiconductor substrate. Depositing an insulating film and forming a buried layer in the first opening; planarizing a first insulating film and a second insulating film on the semiconductor substrate; among the openings of the photo buried layer of the first opening a particular
Forming a second opening by local removal by an etching method, and depositing a third insulating film in the second opening, and then forming a first conductive film on the semiconductor substrate. Depositing and forming a gate electrode in the second opening via the third insulating film by leaving the first conductive film in the second opening. It is characterized by.

According to the method of manufacturing a semiconductor memory device as described above, since the gate electrode is formed in the semiconductor substrate,
Short circuit between the gate electrode and another conductive layer is less likely to occur.
After the gate electrode is formed, the surface of the semiconductor substrate has no steps corresponding to the thickness of the gate electrode, and the surface of the semiconductor substrate is almost flat, so that the thickness of the insulating film deposited on the gate electrode can be reduced. Becomes For this reason, the depth of the connection hole between the conductive layer above the gate electrode and the semiconductor substrate can be made shallow, and the covering state of the inside of the connection hole of the conductive layer becomes good, and the electrical connection failure of the conductive layer in the connection hole is reduced. This makes it easy to manufacture a highly reliable semiconductor memory device. Also, since the switching transistor region of the memory cell and the isolation region between the memory cells are formed at the same time,
The number of manufacturing steps can be reduced, and the manufacturing cost can be reduced.

After the gate electrode is formed, a fourth insulating film is deposited on the semiconductor substrate and planarized, and then a first connection hole reaching the surface of the semiconductor substrate is formed in the fourth insulating film. forming by photoetching method, after depositing the second conductive film on the semiconductor substrate, photo bit line
Forming by an etching method ;
Insulation after film deposited to planarize the second connection hole of the photolithography method to reach the surface of the semiconductor substrate to said fifth insulating film
A step of forming by the after depositing a third conductive film on a semiconductor substrate, it is preferable that a step of the form <br/> formed by photo-etching the charge storage electrode.

Further, after forming the charge storage electrode, after depositing the capacitor dielectric on the semiconductor substrate film and the fourth conductive film, it is preferable to form a plate electrode by photoetching method.

Preferably, the first opening is formed by using a mask pattern of a combination of two figures which do not intersect the active region of the unit memory cell. According to the method of manufacturing a semiconductor memory device as described above, it is possible to simultaneously define the region separating the memory cells and the impurity diffusion layer region, thereby reducing the number of manufacturing steps and reducing the manufacturing cost.

Preferably, the first opening is formed by using a mask pattern of a combination of two congruent figures which do not intersect the active region of the unit memory cell. According to the method of manufacturing a semiconductor memory device as described above, it is possible to simultaneously define the region separating the memory cells and the impurity diffusion layer region, thereby reducing the number of manufacturing steps and reducing the manufacturing cost. Furthermore, since the mask pattern is a combination of two congruent figures, the memory cell area can be made smaller than in the case where the two figures are not congruent, so that higher integration is possible.

After the gate electrode is formed, a fourth insulating film is deposited on the semiconductor substrate and planarized, and then a first connection hole reaching the surface of the semiconductor substrate is formed in the fourth insulating film. forming by photoetching method, after depositing the second conductive film on the semiconductor substrate, a charge storage electrode
Forming by photolithography method, after depositing the capacitor dielectric on the semiconductor substrate film and the third conductive film, and forming a plate electrode by photolithography method, first on the semiconductor substrate 5 after depositing and planarizing the insulating film, shooting a second connection hole reaching the semiconductor substrate surface in the fifth insulating film
Forming a true etching method, after depositing a fourth conductive layer on the semiconductor substrate, a bit line photolithographic method
It is preferable that a step of forming Ri.

After the first opening is formed and before the buried layer is formed, a second impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate is formed in the first opening. It is preferable to include a step of performing

Further, after the second opening is formed and before the third insulating film is formed, the second impurity diffusion is formed in the first opening with the same conductivity type as that of the semiconductor substrate. It is preferable that the method further includes a step of forming a third impurity diffusion layer for separating the layers. By forming the third impurity diffusion layer as described above, the threshold voltage of the switching transistor of the memory cell can be reliably controlled. In other words, even when the semiconductor memory device is further miniaturized, the separated impurity diffusion layers are used for the source and the drain by separating the second impurity diffusion layer by the third impurity diffusion layer. In this case, ON / OFF of the switching transistor can be controlled by the gate voltage.

The depth of the third impurity diffusion layer is:
It is preferable that the depth is greater than the depth of the second impurity diffusion layer. According to the method of manufacturing a semiconductor memory device as described above,
The second impurity diffusion layer can be reliably separated by the third impurity diffusion layer.

Also, the semiconductor substrate surface is 90 °
Ion implantation at an angle of incidence less than
Is preferably formed. According to the method for manufacturing a semiconductor memory device as described above, the impurity diffusion layer in the memory cell is formed inside the first opening, so that the memory cell switching transistor having the gate electrode disposed inside the semiconductor substrate is formed. Formation is possible.

Further, the depth of the first opening is set to the first
It is preferable that the depth is larger than the depth of the impurity diffusion layer.
According to the method of manufacturing a semiconductor memory device as described above, the impurity diffusion layer region constituting the switching transistor and the region where the gate electrode is provided are defined inside the semiconductor substrate, and the conductive layer is removed in the element isolation region. Therefore, a highly reliable semiconductor memory device can be manufactured.

The distance from the surface of the semiconductor substrate to the bottom of the second opening is equal to or deeper than the distance from the surface of the semiconductor substrate to the bottom of the first opening. Further, it is preferable that the second opening is formed so as to be shallower than a distance from a surface of the semiconductor substrate to a bottom of the second impurity diffusion layer at a bottom of the second opening.

According to the method of manufacturing a semiconductor memory device as described above, the region where the gate electrode is provided and the insulating region between the gate electrode and another conductive layer are simultaneously defined inside the semiconductor substrate. In addition, the number of manufacturing steps can be reduced, and the manufacturing cost can be reduced.

[0035]

Embodiment 1 Hereinafter, a semiconductor memory device according to Embodiment 1 and a method for manufacturing the same will be described with reference to FIGS. Each plan view in the figure shows only a main part, and other parts are not shown.

First, in the step shown in FIG. 1, a first impurity diffusion layer 103 having a conductivity type opposite to that of the semiconductor substrate 101 is formed on a semiconductor substrate (silicon substrate) 101 by ion implantation 102. In the step shown in FIG.
A laminated film 105 of a silicon nitride film and a silicon oxide film is formed on a semiconductor substrate 104, and a photoresist 106 is formed by a mask pattern 107. FIG. 2 (a)
It is a top view of FIG.2 (b). As shown in the figure, the mask pattern 107 is a combination of two figures that do not intersect each other in the unit memory cell area. The combination of the two figures is a combination of the mask patterns 107a and 107b or a combination of the mask patterns 107b and 107c.

In the step shown in FIG. 3A, a laminated film 108 of a silicon nitride film and a silicon oxide film is formed by photolithography.
Is removed, and then a portion of the semiconductor substrate 110 is removed deeper than the depth of the impurity diffusion layer 109 to form a first opening 111.

In the step shown in FIG. 3B, the semiconductor substrate 110 is formed on the side wall and a part of the bottom surface of the first opening 114 by ion implantation 113 using a photoresist 112.
A second impurity diffusion layer 115 having a conductivity type opposite to that of the second impurity diffusion layer 115 is formed.

In the step shown in FIG. 3C, a CVD silicon oxide film 116 is deposited. In the step shown in FIG. 3D, the entire surface is flattened and the first opening is removed by removing a part of the stacked film 108 of the silicon nitride film and the silicon oxide film and part of the silicon oxide film 116 by polishing. 1
A buried film 119 is left in 18. Subsequently, in the step shown in FIG. 4A, the entire laminated film 117 of the silicon nitride film and the silicon oxide film and a part of the buried film 119 are removed by wet etching, leaving the buried film 120 and the surface of the semiconductor substrate. Expose 121.

In the steps shown in FIGS. 4B and 4C, a part of the buried film 123 is removed by photolithography using a photoresist 122 to form a second opening 124. Subsequently, a third impurity diffusion layer 160 of the same conductivity type as the semiconductor substrate 110 is formed by ion implantation 161 so as to be deeper than the second impurity diffusion layer 115. This is to ensure that the second impurity diffusion layer 115 is separated by the third impurity diffusion layer 160.
Thereafter, the photoresist 122 is removed.

In the step shown in FIG. 4D, a gate oxide film 125 and a polysilicon film 126 containing impurities are sequentially formed, and in the step shown in FIG. 5B, a gate electrode 127 is formed by etch back. . FIG. 5 (a) is the same as FIG. 5 (b)
FIG. In the steps shown in FIGS. 6A and 6B, a CVD silicon oxide film 128 is deposited and flattened, and then a contact hole 130 is opened by photolithography using a photoresist 129.

In the step shown in FIG. 7B, a bit line 131 is formed by photolithography after depositing a laminated film of tungsten silicide and polysilicon containing impurities. FIG. 7A is a plan view of the state of FIG. 7B.
In the steps shown in FIGS. 8A and 8B, a CVD silicon oxide film 132 is deposited and planarized, and then a contact hole 13 is formed by photolithography using a photoresist 133.
4 is opened.

In the step shown in FIG. 8C, a polysilicon film 135 containing impurities is deposited. In the step shown in FIG. 9B, the charge storage electrode 137 is formed using the photoresist 136 by a photolithography method. Subsequently, a capacitor insulating film 138 composed of a stacked film of a silicon oxide film and a silicon nitride film and a polysilicon film containing impurities are sequentially formed, and a plate electrode 139 is formed by photolithography.
FIG. 9A is a plan view of FIG. 9B.

In the semiconductor memory device manufactured as described above, as shown in FIG. 9, the gate electrode 127 is formed in the second opening in the semiconductor substrate 110 in a specific region of the first opening 111. The buried film 123 and the insulating film of the CVD silicon oxide film 128 cover the periphery of the gate electrode 127. This allows
Short circuit between the gate electrode 127 and another conductive layer hardly occurs, and a highly reliable semiconductor memory device can be realized.

The second impurity diffusion layer 115 of the opposite conductivity type to the semiconductor substrate 110 is separated by the third impurity diffusion layer 160 of the same conductivity type as the semiconductor substrate 110. Therefore, of the separated second impurity diffusion layers 115, one of the second impurity diffusion layers 115 and the first impurity diffusion layer 109 connected thereto are used as a source and the other second impurity diffusion layer 115 is used as a source. The diffusion layer 115 and the first impurity diffusion layer 109 connected thereto can be used as a drain.

Further, such a third impurity diffusion layer 16
By forming 0, the threshold voltage of the switching transistor of the memory cell can be reliably controlled. That is, even when the semiconductor memory device is further miniaturized, the second impurity diffusion layer 115 is separated by the third impurity diffusion layer 160, so that the separated second impurity diffusion layer 115 When used for source and drain as in
/ OFF can be controlled by the gate voltage.

In this embodiment, the case where the second impurity diffusion layer 115 is separated by forming the third impurity diffusion layer 160 has been described. However, in the step of FIG. More second impurity diffusion layer 1
15 may be formed separately in advance, and the third impurity diffusion layer 160 may not be formed. This method is effective when the size of the gate electrode is relatively long and the distance between the source and the drain has a relatively large margin.

The unit memory cells (active regions) 140 and 141 and the isolation regions 142 and 143 between adjacent memory cells shown in FIG. 9 are mask patterns 107 formed of simple figures (see FIG. 2). First opening 1 using
11, the second opening 12
By forming the region 4, the region of the gate electrode 127 is defined, and the region 123 that covers the gate electrode 127 and is insulated from other conductive layers is formed. This simplifies the manufacturing process, reduces the number of manufacturing processes, and reduces manufacturing costs.

FIG. 10A is a conventional example for comparison with the semiconductor memory device according to the present embodiment. FIG. 10 (a)
As shown in FIG. 2, in the conventional semiconductor memory device, the gate electrode 145 is provided on the semiconductor substrate 144, so that the step amount s occurs, and the insulation between the gate electrode 145 and the bit line 147 is ensured. Insulating film 1 necessary for performing
When the thickness t ₁ of 46 is secured, the depth T 1 of the connection hole 148 between the bit line 147 and the semiconductor substrate 144 becomes s + t ₁ . In addition, when the thickness t ₂ of the insulating film 149 necessary for ensuring insulation between the bit line 147 having the film thickness h and the charge storage electrode 150 is secured, the connection between the charge storage electrode 150 and the semiconductor substrate 144 is ensured. The depth T ₂ of the hole 151 is s + t ₁
+ H + t ₂ .

On the other hand, in the semiconductor memory device according to the present embodiment shown in FIG.
3 are arranged inside the semiconductor substrate 152, the depth T1 'of the connection hole 155 between the bit line 156 and the semiconductor substrate 152, and the depth T2' of the connection hole 159 between the charge storage electrode 158 and the semiconductor substrate 152. Means that the thickness of the insulating film 154 is t1,
The thickness of the bit line 155 is h, and the thickness of the insulating film 157 is t2.
Then, t1 and t1 + h + t2 are obtained, respectively.

As described above, the depth of the connection hole between the conductive layer above the gate electrode and the semiconductor substrate can be made shallower, the covering state of the inside of the connection hole of the conductive layer becomes good, and the electric conductivity of the conductive layer in the connection hole becomes large. Connection failure can be prevented.
Therefore, it becomes easy to manufacture a highly reliable semiconductor memory device.

In the first embodiment, the mask pattern 107 is a combination of two figures that do not intersect with each other in the unit memory cell region. However, the mask pattern 107 may be a combination of two congruent figures that do not intersect with each other. In this case, it is necessary to provide a region through which the connection hole between the charge storage electrode and the semiconductor substrate penetrates in the bit line. If the bit line shape is not a linear shape but a shape that bypasses the connection hole opening region between the charge storage electrode and the semiconductor substrate, the connection hole penetrating region in the bit line mask pattern portion is provided. Instead, a mask pattern of a combination of two congruent figures can be used.

In the first embodiment, the gate electrode 127 is formed of a polysilicon film containing impurities. However, a tungsten film, a molybdenum film, a titanium film, a platinum film, a tungsten silicide film, a molybdenum silicide film, a titanium silicide film Or a single layer film such as a platinum silicide film, or a stacked film of a tungsten silicide film, a molybdenum silicide film, a titanium silicide film, or a platinum silicide film and a polysilicon film containing impurities.

Although the bit line 131 is formed of a laminated film of tungsten silicide and polysilicon containing impurities, a polysilicon film containing impurities, a tungsten film, a molybdenum film, a titanium film, a platinum film, a tungsten silicide film, A single-layer film such as a molybdenum silicide film, a titanium silicide film, a platinum silicide film, or a stacked film of a molybdenum silicide film, a titanium silicide film, a platinum silicide film, and a polysilicon film containing impurities may be used.

Although the charge storage electrode 137 is formed of a polysilicon film containing impurities, a tungsten silicide film, a molybdenum silicide film, a titanium silicide film,
A single-layer film of tungsten or the like, or a stacked film of a polysilicon film containing impurities, a platinum film, and a tantalum film may be used.

Further, the capacitor insulating film 138 is formed of a laminated film of a silicon oxide film and a silicon nitride film. However, a tantalum oxide film, a strontium titanate film, a strontium titanate film to which barium is added, lead, zirconium and titanium , An oxide containing lead, lanthanum, zirconium, and titanium (PLZT), or a stacked film of a tantalum oxide film and a silicon oxide film.

Although the plate electrode 139 is formed of a polysilicon film containing impurities, it may be formed of a titanium nitride film, a tungsten film, a tungsten silicide film, a molybdenum film, a molybdenum silicide film, or the like.

Embodiment 2 Hereinafter, a semiconductor memory device and a method of manufacturing the same according to Embodiment 2 of the present invention will be described with reference to FIGS. Each plan view shows only a main part, and the other parts are not shown.

First, in the step shown in FIG. 11, a first impurity diffusion layer 203 having a conductivity type opposite to that of the semiconductor substrate 201 is formed on a semiconductor substrate (silicon substrate) 201 by ion implantation 202.

In the step shown in FIG. 12B, a laminated film 205 of a silicon nitride film and a silicon oxide film is formed on a semiconductor substrate 204, and a photoresist 206 formed by a mask pattern 207 is attached. FIG. 12 (a)
FIG. 13 is a plan view of FIG. As shown in the figure, the mask pattern 207 is in the unit memory cell region.
This is a combination of two congruent figures that do not intersect each other. 2
The combination of two congruent figures is the mask pattern 207a
And 207b, or the mask pattern 207
b and 207c.

In the step shown in FIG. 13A, a laminated film 20 of a silicon nitride film and a silicon oxide film is formed by photolithography.
8 is removed, and then a portion of the semiconductor substrate 210 is removed deeper than the depth of the impurity diffusion layer 209 to form a first opening 211.

In the step shown in FIG. 13B, the first photoresist is
The semiconductor substrate 21 is partially formed on the side wall and a part of the bottom surface of the opening 214 of
A second impurity diffusion layer 215 having a conductivity type opposite to 0 is formed.

In the step shown in FIG. 13C, a CVD silicon oxide film 216 is deposited. In the step shown in FIG. 13D, the entire surface is flattened and the first opening is removed by removing a part of the stacked film 208 of the silicon nitride film and the silicon oxide film and part of the silicon oxide film 216 by polishing. A buried film 219 is left in 218,
In the step shown in FIG. 2A, the entire silicon nitride film and silicon oxide film laminated film 217 and part of the buried film 219 are removed by wet etching, leaving the buried film 220 and exposing the semiconductor substrate surface 221. .

In the steps shown in FIGS. 14B and 14C,
Using the photoresist 222, a part of the buried film 223 is removed by photolithography to form a second opening 224. Subsequently, a third impurity diffusion layer 245 of the same conductivity type as the semiconductor substrate 210 is formed by ion implantation 246 so as to be deeper than the second impurity diffusion layer 215. This is to ensure that the second impurity diffusion layer 215 is separated by the third impurity diffusion layer 245.
Thereafter, the photoresist 222 is removed.

In the step shown in FIG. 14D, a gate oxide film 225 and a polysilicon film 226 containing impurities are sequentially formed, and in the step shown in FIG. 15B, a gate electrode 227 is formed by etch-back. I do. FIG. 15A is a plan view of FIG. In the steps shown in FIGS. 16A and 16B, a CVD silicon oxide film 228 is deposited and planarized, and then a contact hole 230 is opened by photolithography using a photoresist 229.

In the steps shown in FIGS. 16C and 16D,
After depositing the polysilicon film 231 containing impurities, the charge storage electrode 233 is formed by photolithography using the photoresist 232.

In the step shown in FIG. 17B, the capacitor insulating film 2 composed of a stacked film of a silicon oxide film and a silicon nitride film is formed.
34, a polysilicon film 235 containing impurities is sequentially formed, a plate electrode 235 is formed by a photolithography method, and an empty region 236 is formed. FIG. 17 (a)
It is a top view of FIG.

In the steps shown in FIGS. 18A and 18B,
A CVD silicon oxide film 237 is deposited and planarized, and then a contact hole 239 is opened by photolithography using a photoresist 238. In the step shown in FIG. 19B, a bit line 240 made of a laminated film of tungsten silicide and polysilicon containing impurities is formed by photolithography. FIG. 19A is a plan view of FIG. 19B.

In the semiconductor memory device manufactured as described above, as shown in FIG. 19, the gate electrode 227 is formed in the second opening formed in a specific region of the first opening 211 in the semiconductor substrate 210. The buried film 223 and the insulating film of the CVD silicon oxide film 228 are covered around the gate electrode 227. Accordingly, a short circuit between the gate electrode 227 and another conductive layer hardly occurs, and a highly reliable semiconductor memory device can be realized.

The second impurity diffusion layer 215 having the opposite conductivity type to the semiconductor substrate 210 is separated by the third impurity diffusion layer 245 having the same conductivity type as the semiconductor substrate 210. Therefore, of the separated second impurity diffusion layers 215, one of the second impurity diffusion layers 215 and the first impurity diffusion layer 209 connected thereto are used as a source and the other second impurity diffusion layer 215 is used as a source. The diffusion layer 215 and the first impurity diffusion layer 209 connected thereto can be used as a drain.

Further, such a third impurity diffusion layer 24
By forming 5, the threshold voltage of the switching transistor of the memory cell can be reliably controlled. That is, even when the semiconductor memory device is further miniaturized, the second impurity diffusion layer 215 is separated by the third impurity diffusion layer 245. When used for source and drain as in
/ OFF can be controlled by the gate voltage.

In the present embodiment, the case where the separation of the second impurity diffusion layer 215 is performed by forming the third impurity diffusion layer 245 has been described. However, in the step of FIG. Further, the second impurity diffusion layer 215 may be formed separately in advance, and the third impurity diffusion layer 245 may not be formed. This method is effective when the size of the gate electrode is relatively long and the distance between the source and the drain has a relatively large margin.

The unit memory cells (active regions) 241 and 242 and the isolation regions 243 and 244 between adjacent memory cells shown in FIG. 19 are mask patterns 207 (see FIG. 12) formed by simple figures. Is defined by forming the first opening 211 using the first opening 211, and by forming the second opening 224, the region of the gate electrode 227 is defined, and another conductive layer covering the gate electrode 227 is formed. Is formed, which forms a region 223 that insulates them. This simplifies the manufacturing process, reduces the number of manufacturing processes, and reduces manufacturing costs.

As shown in FIG. 12A, the mask pattern 207 is a combination of two congruent figures which do not intersect each other in the unit memory cell area. As compared with the case where mask patterns 107 having different vertical lengths from each other are used, the unit memory cell area can be made smaller, so that higher integration can be achieved.

Further, as shown in FIG.
Contact hole 239 between semiconductor substrate 201 and semiconductor substrate 201
Penetrates the plate electrode 235 in a form insulated from the plate electrode 235 by the CVD silicon oxide films 228 and 239. Regarding this, when patterning the plate electrode 235 as shown in FIG.
6 is used.

As shown in FIGS. 18A and 18B, after depositing a CVD silicon oxide film 237 as an insulating film, the empty region 236 is filled with the CVD silicon oxide film 237, and then the empty region 236 is formed. Since the connection hole 239 is opened by using a mask having an opening pattern of a smaller size, the CVD oxide film 237 is left between the free region 236 of the plate electrode 235 and the connection hole 239. And the material for the bit line 240 is
Even if it is embedded in 39, the plate electrode 235 and the bit line 24
0 is reliably insulated.

Using such a mask pattern and using the mask pattern 207 as shown in FIG. 12, the active regions 241 and 242 and the element isolation regions 243 and 244 are used.
By forming the impurity diffusion layer region 209 of the active region on the same line as shown in FIG. 19, the memory cell region can be secured in a small area, thereby realizing a highly integrated semiconductor memory device. can do.

Although the gate electrode 227 is formed of a polysilicon film containing impurities in the second embodiment, a tungsten film, a molybdenum film, a titanium film, a platinum film, a tungsten silicide film, a molybdenum silicide film, a titanium film A single-layer film such as a silicide film or a platinum silicide film, or a stacked film of a tungsten silicide film, a molybdenum silicide film, a titanium silicide film, or a platinum silicide film and a polysilicon film containing impurities may be used.

Although the charge storage electrode 233 is formed of a polysilicon film containing impurities, a tungsten silicide film, a molybdenum silicide film, a titanium silicide film,
A single-layer film of tungsten or the like, or a stacked film of a polysilicon film containing impurities, a platinum film, and a tantalum film may be used.

The capacitance insulating film 234 is formed of a laminated film of a silicon oxide film and a silicon nitride film. However, a tantalum oxide film, a strontium titanate film, a strontium titanate film to which barium is added, a lead, zirconium and titanium , An oxide containing lead, lanthanum, zirconium, and titanium (PLZT), or a stacked film of a tantalum oxide film and a silicon oxide film.

Although the plate electrode 235 is formed of a polysilicon film containing impurities, a titanium nitride film, a tungsten film, a tungsten silicide film, a molybdenum film,
It may be formed of a molybdenum silicide film or the like.

Further, although the bit line 240 is formed of a laminated film of tungsten silicide and polysilicon containing impurities, the polysilicon film containing impurities, tungsten film, molybdenum film, titanium film, platinum film, tungsten silicide film, A single-layer film such as a molybdenum silicide film, a titanium silicide film, a platinum silicide film, or a stacked film of a molybdenum silicide film, a titanium silicide film, a platinum silicide film, and a polysilicon film containing impurities may be used.

[0083]

As described above, according to the semiconductor memory device of the present invention, since the gate electrode is provided in the semiconductor substrate, a short circuit between the gate electrode and another conductive layer hardly occurs. The reliability of the device can be improved. Since the depth of the connection hole between the conductive layer above the gate electrode and the semiconductor substrate can be made shallower, the covering state inside the connection hole of the conductive layer becomes good, and the poor connection of the conductive layer in the connection hole is prevented, The reliability of the semiconductor memory device can be improved.

Next, according to the method for manufacturing a semiconductor memory device of the present invention, since the gate electrode is formed in the semiconductor substrate, a short circuit between the gate electrode and another conductive layer hardly occurs. After the gate electrode is formed, the surface of the semiconductor substrate has no steps corresponding to the thickness of the gate electrode, and the surface of the semiconductor substrate is almost flat, so that the thickness of the insulating film deposited on the gate electrode can be reduced. Becomes For this reason, the depth of the connection hole between the conductive layer above the gate electrode and the semiconductor substrate can be made shallow, and the covering state of the inside of the connection hole of the conductive layer becomes good, and the electrical connection failure of the conductive layer in the connection hole is reduced. This makes it easy to manufacture a highly reliable semiconductor memory device. Also, since the switching transistor region of the memory cell and the isolation region between the memory cells are formed at the same time,
The number of manufacturing steps can be reduced, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a sectional view showing a manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 5 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 6 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 7 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 8 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 9 is a sectional view showing the manufacturing process of the semiconductor memory device according to the first embodiment of the present invention;

FIG. 10A is a cross-sectional view of a conventional semiconductor memory device. FIG. 10B is a cross-sectional view of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 12 is a sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 13 is a sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 14 is a sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 15 is a sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 16 is a sectional view showing a manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 17 is a sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 18 is a sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 19 is a sectional view showing the manufacturing process of the semiconductor memory device according to the second embodiment of the present invention;

FIG. 20 is a sectional view showing a manufacturing process of a conventional semiconductor memory device.

FIG. 21 is a sectional view showing a manufacturing process of a conventional semiconductor memory device.

FIG. 22 is a sectional view showing a manufacturing process of a conventional semiconductor memory device;

FIG. 23 is a sectional view showing a manufacturing process of a conventional semiconductor memory device.

[Explanation of symbols]

101,104,110,144,152,201,2
04, 210 Semiconductor substrate 102, 113, 161, 202, 213, 246 Ion implantation 103, 109, 203, 209 First impurity diffusion layer 105, 108, 117, 205, 208, 217 Silicon nitride film and silicon oxide film Laminated film 106, 112, 122, 129, 133, 136, 2
06, 212, 222, 229, 232, 238 Photoresist 107, 207 Mask pattern 111, 114, 118, 211, 214, 218 First opening 115, 215 Second impurity diffusion layer 160, 245 Third impurity Diffusion layer 116 CVD silicon oxide film 119, 120, 123, 219, 220, 223 Buried oxide film in first opening 121, 221 Semiconductor substrate surface 124, 224 Second opening 125, 225 Gate oxide film 126, 226 , 231 Multi-layer film of polysilicon containing impurities 127, 145, 153, 227 Gate electrode 128 CVD silicon oxide film 130, 134, 230, 239, 321, 325 Contact hole 131, 147, 156, 240 Bit line 132, 216, 228,237 C VD silicon oxide film 137, 150, 158, 233 Charge storage electrode 138, 234 Capacitance insulating film 139, 235 Plate electrode 140, 141, 241, 242 Unit memory cell 142, 143, 243, 244 Isolation region between adjacent memory cells 146, 149, 154, 157 Insulating film 148, 155 Connection hole between bit line and semiconductor substrate 151, 159 Connection hole between charge storage electrode and semiconductor substrate 236 Free area of plate electrode

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (22)

(57) [Claims] 1. A semiconductor substrate, a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate formed on the semiconductor substrate, and a first impurity diffusion layer formed by removing a part of the semiconductor substrate.
An opening, an embedded layer formed of an insulating film formed in the first opening, a second opening formed by removing a part of the embedded layer, and an opening formed in the second opening. A gate electrode formed; a second impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate formed on a part of a side wall and a bottom surface of the first opening; provided with a formed the semiconductor substrate and the same conductivity type third impurity diffusion layer of the said second impurity diffusion layer is separated by the third impurity diffusion layer of, further said semiconductor substrate
The insulating film formed on the top, the bit line of the conductive film, and the conductive film
A charge storage electrode of a conductive film, wherein the bit line and the semiconductor
The connection with the body substrate surface is formed by opening the insulating film.
Penetrating between the bit line and the surface of the semiconductor substrate
The connection is made by a first connection hole, the charge storage electrode and the
Connection with the semiconductor substrate surface is formed by opening the insulating film
Between the charge storage electrode and the surface of the semiconductor substrate.
The semiconductor memory device is performed by a second connection hole penetrating therethrough . 2. The semiconductor memory device according to claim 1, wherein an insulating film is formed between a bottom surface of said second opening and said gate electrode. 3. A semiconductor memory device according to the charge storage electrode and on the insulating film according to claim 1 or 2, plate electrode conductor film via a capacitor insulating film is formed on. 4. The semiconductor memory device according to claim 3 , wherein said bit line is formed between said semiconductor substrate and said plate electrode. 5. The semiconductor memory device according to claim 3 , wherein said bit line is formed on said plate electrode via an insulating film. 6. The semiconductor memory device according to claim 5 , wherein a connection hole connecting said bit line and said semiconductor substrate passes between adjacent plate electrodes. 7. A semiconductor memory device according to any one of the first depth of the opening from a deep claims 1 than the depth of the first impurity diffusion layer 6. 8. A semiconductor device further comprising a third opening formed by removing a part of the semiconductor substrate, wherein the gate electrode is not formed in the third opening and the buried layer is buried. is to have a semiconductor memory device according to any one of claims 1 to 7, wherein said buried layer of said third opening is formed isolation regions. Wherein said depth of the third impurity diffusion layer of the semiconductor memory device according to any one of the second from the deep claims 1 than the depth of the impurity diffusion layer 8. 10. The first and second impurity diffusion layers,
A source or drain of the switching transistor of the memory cell, the gate electrode of claims 1, which is a gate electrode of the switching transistor of the memory cell 9
The semiconductor memory device according to any one of the above. 11. A step of forming a first impurity diffusion layer of a conductivity type opposite to that of the semiconductor substrate on the semiconductor substrate, and forming a first insulating film on the semiconductor substrate, Forming a plurality of first openings by locally removing an insulating film and the semiconductor substrate by photolithography; and depositing a second insulating film on the semiconductor substrate to form the first opening. Forming a buried layer in the portion, flattening a first insulating film and a second insulating film on the semiconductor substrate, and forming a specific first opening of the plurality of first openings. Forming a second opening by locally removing a buried layer of the portion by photolithography, and depositing a third insulating film in the second opening, and then forming a second insulating film on the semiconductor substrate. Depositing one conductive film, and leaving the first conductive film in the second opening, Forming a gate electrode in the second opening via the third insulating film. 12. After the gate electrode is formed, a fourth insulating film is deposited on the semiconductor substrate and flattened, and then a first connection hole reaching the surface of the semiconductor substrate in the fourth insulating film. forming by photoetching method, after depositing the second conductive film on the semiconductor substrate, photo bit line diet
A step of forming by embossing method, wherein after the fifth deposited to planarize the insulating film on a semiconductor substrate, a second connection hole for a photo-etching to reach the semiconductor substrate surface in the fifth insulating film To
Step and the after depositing a third conductive film on a semiconductor substrate, a method of manufacturing a semiconductor memory device according to claim 11 including forming a charge storage electrode by photoetching method to further form . 13. After forming the charge storage electrode, after depositing a capacitor insulating film and the fourth conductive film on the semiconductor substrate, according to claim which includes a step of forming a plate electrode by photoetching method 13. The method for manufacturing a semiconductor memory device according to item 12 . 14. The method according to claim 11 , wherein the first opening is formed using a mask pattern of a combination of two figures that do not intersect the active region of the unit memory cell. 15. The method of manufacturing a semiconductor memory device according to claim 11 , wherein said first opening is formed using a mask pattern of a combination of two congruent figures which do not intersect the active region of a unit memory cell. . 16. After the gate electrode is formed, a fourth insulating film is deposited on the semiconductor substrate and planarized, and then the first connection hole reaching the semiconductor substrate surface in the fourth insulating film. forming by photoetching method, after depositing the second conductive film on the semiconductor substrate, copy charge storage electrode
Forming a true etching method, after depositing the capacitor dielectric on the semiconductor substrate film and the third conductive film, and forming a plate electrode by photolithography method, first on the semiconductor substrate 5 After depositing and planarizing the insulating film, a second connection hole reaching the surface of the semiconductor substrate is photographed in the fifth insulating film.
Forming by an etching method ;
Forming a bit line by photolithography after depositing the conductive film of claim 1. 12. The method of manufacturing a semiconductor memory device according to claim 11 , further comprising: 17. After forming the first opening and before forming the buried layer, a second impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate is formed in the first opening. 17. The method according to claim 11, further comprising the step of: 18. After the second opening is formed and before the third insulating film is formed, the second impurity is diffused into the first opening in the same conductivity type as the semiconductor substrate. 18. The method according to claim 17 , further comprising the step of forming a third impurity diffusion layer for separating the layers. 19. The depth of the third impurity diffusion layer of the method of manufacturing a semiconductor memory device according to the second deep Claim 18 than the depth of the impurity diffusion layer. 20. The semiconductor memory device according to claim 17 , wherein the second impurity diffusion layer is formed by ion-implanting the semiconductor substrate surface at an incident angle of less than 90 °. Production method. 21. The depth of the first opening is set to the first depth.
Claim 11, deeper than the depth of the impurity diffusion layers from 2
0. The method for manufacturing a semiconductor memory device according to any one of the above items. 22. A distance from a surface of the semiconductor substrate to a bottom of the second opening is equal to or deeper than a distance from a surface of the semiconductor substrate to a bottom of the first opening; 22. The second opening according to claim 11 , wherein the second opening is formed so as to be shallower than a distance from a surface of the semiconductor substrate to a bottom of the second impurity diffusion layer at a bottom of the second opening. A method for manufacturing the semiconductor memory device according to any one of the above.