KR20020066090A - Method of fabricating a capacitor in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to remarkably increase capacitance as compared with a metal-insulator-metal(MIM) capacitor, by using the first and third electrodes as one electrode and by using the second electrode interposed between the one electrode and a dielectric layer as the other electrode. CONSTITUTION: The first interlayer dielectric(31) is formed on a substrate(30). The first metal layer pad is formed on the first interlayer dielectric. The second interlayer dielectric(33) is formed to sufficiently cover the first metal layer pad. A predetermined portion of the second interlayer dielectric is removed to form at least two first and second via holes. The first and second plugs are formed. The first electrode(35), the first dielectric layer(36) and the second electrode(370) are sequentially formed on the second interlayer dielectric. The second dielectric layer(38) is formed on the second electrode, covering the exposed surface of the second electrode and exposing a partial surface of the second electrode. The third electrode(39) is formed only on the second dielectric layer. The third interlayer dielectric(40) is formed. A predetermined portion of the third interlayer dielectric is removed to form a plurality of via holes. The third plug contacting the third electrode, the fourth plug(411) contacting the second plug and the fifth plug not overlapping the third electrode and contacting the second electrode are formed in the via holes, respectively. The first connecting electrode(420) electrically connecting the third and fourth plugs and the second connecting electrode(421) electrically connected to the fifth plugs are formed.

Description

Method of fabricating a capacitor in a semiconductor device

The present invention forms a first electrode on the lower surface of the second electrode and forms a third electrode so as to overlap most surfaces of the upper and side surfaces of the second electrode, so that the dielectric film is formed in the overlapping portion of the second electrode and the first and third electrodes. The present invention relates to a method for manufacturing a MIM capacitor of a semiconductor device, which maximizes the capacitance effective area of a capacitor and contributes to an increase in device integration.

The MIM (metal-insulator-metal) capacitors used in the analog circuits of various graphics and multimedia devices, which occupy most of the merged DRAM and logic (MDL) devices, provide high capacitance with small series resistance and low thermal budget. Thermal budgets are widely used because of the high integration of the process.

MIM capacitors have low VCC and high precision mismatching characteristics compared to conventional polysilicon-insulator-polysilicon (PIP) capacitors. That is, the MIM capacitor is an analog capacitor and is formed of a metal having a high Q factor, almost no depletion as an electrode, and low resistance such as tungsten.

The analog capacitor of the prior art mainly uses a PIP flat plate structure, but since the high precision is required due to the high resistance of the polysilicon electrode itself, there is a limit to being used as an electrode material of a capacitor for an RF IC.

Therefore, a flat capacitor having a MIM structure using a metal electrode without depletion of the electrode itself and having a low resistance value has been developed.

However, the method of manufacturing a MIM capacitor according to the prior art uses only a part of the surface of the flat plate capacitor on the substrate as the effective area, so that the area occupied by the capacitor is increased, which is disadvantageous in reducing integration.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a semiconductor device according to the prior art.

Referring to FIG. 1, an insulating film 11 is formed on a silicon substrate 10, and a lower electrode 12 made of polysilicon doped on the insulating film 11 is patterned in a predetermined shape. In this case, the insulating film 11 may be a field oxide film.

On the surface of the lower electrode 12, a dielectric film 13 made of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed. Since the dielectric film 13 has a high dielectric constant value, it is possible to secure necessary capacitance even in a small area.

Next, a capacitor having a PIP structure is completed by polysilicon doped with the upper electrode 14 covering the upper surface and one side surface of the dielectric film 13 and extending to the upper surface of the insulating film 11.

However, the capacitor having such a structure is advantageous in securing capacitance, but is not easy to use due to the resistance of polysilicon in a device requiring high frequency operation, and is disadvantageous in terms of increasing the effective area since only one surface of the electrode is used as the effective area.

2 is a cross-sectional view of a metal-insulator-metal capacitor (MIM) of a semiconductor device according to the prior art.

Referring to FIG. 2, an insulating film 21 is formed on the silicon substrate 20, and a lower electrode 22 made of a metal such as tungsten is patterned on the insulating film 21 in a predetermined shape. In this case, the insulating film 21 may be a field oxide film.

On the surface of the lower electrode 22, a dielectric film 23 having a thickness thicker than that of an oxide-nitride-oxide (ONO) film or an inter-polysilicon layer (IPO) film is formed on the surface of the MIM structure. However, the dielectric film 23 is thick, making it difficult to secure necessary capacitance.

Next, the upper electrode 24 covering the upper surface and one side surface of the dielectric film 23 and extending to the upper surface of the insulating film 21 is made of a metal material such as tungsten to complete the capacitor of the MIM structure.

However, the capacitor having such a structure uses only one surface of the electrode as the effective area, which is disadvantageous in terms of increasing the effective area, and thus, it is difficult to secure the required capacitance in the case of the MIM structure capacitor.

Accordingly, an object of the present invention is to form a first electrode on the lower surface of the second electrode and to form a third electrode so as to overlap most surfaces of the upper and side surfaces of the second electrode, thereby forming the second electrode and the first and third electrodes. The present invention provides a method of manufacturing a MIM capacitor of a semiconductor device in which a dielectric film is provided in an overlapping portion to maximize the capacitance effective area of the capacitor, thereby contributing to an increase in device integration.

A method of manufacturing a capacitor of a semiconductor device according to the present invention for achieving the above objects is to form a first interlayer insulating layer on a substrate and to run a first metal layer pad having a predetermined length in a first direction on the first insulating layer and running long. Forming a second interlayer insulating layer on the first interlayer insulating layer to sufficiently cover the first metal layer pad, and removing a predetermined portion of the second insulating layer to remove a predetermined portion of the metal layer pad. Forming at least two or more first via holes and second via holes to be exposed at predetermined intervals; forming a first plug and a second plug to fill the first to second via holes with a conductor; A second electrode spaced apart from the second plug and in contact with the first plug, in which a zigzag first electrode, a first dielectric film, and a second electrode are sequentially formed on the second interlayer insulating layer; Forming a second dielectric film on the second electrode, the second dielectric film covering the exposed surface of the second electrode but exposing a part surface of the second electrode; and forming a third electrode only on the second dielectric film. With the steps. Forming a second interlayer insulating layer covering the third electrode and the second electrode on the second interlayer insulating layer, and removing a predetermined portion of the third interlayer insulating layer to form a plurality of via holes, and Forming a third plug in contact with an electrode, a fourth plug in contact with the second plug, and a fifth plug in contact with the second electrode not overlapping with the third electrode in the plurality of via holes, respectively; And forming a first connection part electrode electrically connecting the third plug and the fourth plug and a second connection part electrode electrically connected to the fifth plug on the third interlayer insulating layer.

1 is a cross-sectional view of a polysilicon-insulator-polysilicon (PIP) capacitor of a semiconductor device according to the prior art

2 is a cross-sectional view of a metal-insulator-metal capacitor of a semiconductor device according to the related art.

3 is a layout of a MIM capacitor of a semiconductor device according to the present invention.

4A through 6B are cross-sectional views illustrating a method of manufacturing a MIM capacitor of a semiconductor device according to the present invention, taken along cut lines I-I 'and II-II of FIG. 3, respectively.

As the degree of integration of semiconductor devices further increases, the area ratio of capacitors in analog semiconductor devices increases relatively. In order to reduce the area ratio occupied by such a capacitor, a method of forming a dielectric film with a dielectric having a high dielectric constant or reducing a capacitor area to have a stack or trench structure is mainly used.

However, the dielectric having high dielectric constant is disadvantageous in the problem of leakage current characteristics and causes an increase in manufacturing cost due to the addition of equipment. When manufacturing a capacitor in the form of a stack or a trench, the manufacturing process is complicated and the semiconductor device manufacturing yield is reduced.

Accordingly, in the present invention, a part of the metal wiring used in the semiconductor device is used as one electrode of the capacitor, the surface of the metal wiring is covered with an insulating film, and another electrode is formed on the insulating film to manufacture a capacitor having a MIM structure.

That is, in the present invention, a part of the metal wiring is used as one electrode of the capacitor, and the lower surface, the upper surface, and the side surface of the one electrode are used as the effective area, so that the capacitor occupied area is reduced compared to the conventional flat capacitor, thereby reducing the analog. Increasing the integration degree of semiconductor devices, etc., and also using the insulating film used for the interlayer insulating film and passivation used in the prior art as a dielectric film can improve the productivity without additional equipment investment cost, and additional tuning (tuning) It is also advantageous in terms of process flow as it can maintain the flow of the existing interlayer wiring process without any change.

According to the present invention, when a part of the wiring for the electrical connection of a device is formed in the semiconductor device manufacturing process, the surface of the part of the wiring to be the capacitor electrode is covered with an insulator such as a dielectric film, and the dielectric film is covered with a metal thin film again to form a MIM structure. It relates to a method of manufacturing a capacitor.

The MIM capacitor manufactured according to the present invention employs a conventional process flow without adjustment of a metal wiring process formed on an interlayer insulating layer of a general semiconductor device manufacturing process to implement a capacitor having a large capacity in a smaller area than a conventional flat plate capacitor. To make it possible.

The present invention provides a capacitor manufacturing method required in a semiconductor device such as a filter circuit and a voltage controlled oscillator (VCO).

That is, in the present invention, when using a metal such as Al, TiN, etc. as one electrode of the capacitor, the MIM structure has a structure in which the metal wiring is used as one electrode of the capacitor and most of the upper, lower and side surfaces of the metal wiring are covered with an insulating film. Since the capacitor is manufactured, the required capacitance of the device is secured in a relatively small area compared with the flat plate structure of the prior art, thereby improving the integration degree of the semiconductor device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 shows a MIM capacitor layout of a semiconductor device according to the present invention.

Referring to FIG. 3, a first interlayer insulating layer (not shown) to a third interlayer insulating layer (not shown) are sequentially formed on a silicon substrate 30, which is a semiconductor substrate.

The first dielectric layer (not shown), the first electrode (not shown), the first dielectric layer (not shown), and the second electrode 370 having a '-' shape are formed in the second interlayer insulating layer in the same pattern.

In addition, the surface of the second electrode 370 is a view of the 'I' portion of the second electrode 370 having a 'c' shape with the third electrode 39 interposed between the second dielectric layer (not shown). It does not overlap with the left part and is formed to overlap the right part of the 'I' part and the rest of the 'c' part.

Next, the first connecting electrode 420 and the second connecting electrode 421 are formed on the third interlayer insulating layer to be spaced apart from each other.

In this case, the first connection electrode 420 is connected through the third plug 410 and the fourth plug 411 through the third interlayer insulating layer and in contact with the third electrode 39. The fifth plug 412 is electrically connected to the second metal pad layer 371 through the layer.

In addition, a lower surface of the first electrode 35 is electrically connected to the first metal pad layer 32 through first to second plugs 340 and 341 formed on the second interlayer insulating layer.

Meanwhile, a sixth plug 413 is formed on the third interlayer insulating layer to electrically contact the upper surface of the second electrode 370 that does not overlap with the third electrode 39. The second electrode 370 is electrically connected.

Since the third plug 410 and the fourth plug 411 are for electrically connecting the third electrode 39 and the first connection electrode 420, one of the two plugs 410 and 411 may be omitted. Also, the operation of the capacitor element is not affected.

In addition, since the second metal layer pad 371 is for electrically connecting the fifth plug 412 and the second plug 341, the overlapping margin and electrical connection between the two plugs 412 and 341 may be omitted. have.

4A through 6B are cross-sectional views illustrating a method of manufacturing a MIM capacitor of a semiconductor device according to the present invention. FIGS. 4A and 4B and FIGS. 6A and 6B are cut lines I-I 'and II of FIG. 3, respectively. Fig. 5 is a cross sectional view taken along the line II, and Fig. 5 is taken along the line II-II '.

4A and 4B, after forming a first interlayer insulating layer 31 for insulation on a silicon substrate 30, which is a semiconductor substrate, using an insulator such as an oxide film, a first metal layer is deposited thereon, and then a photo. The first metal pad layer 32 is formed of the remaining first metal layer 32 by patterning by lithography. At this time, the layout of the first metal pad layer 32 is formed to have a form capable of electrically connecting the first electrode and the third electrode of the capacitor to be formed in a subsequent process, and in the embodiment of the present invention, the cutting line I of FIG. It has a rectangular shape around -I '. That is, the first metal pad layer 32 is formed in such a manner that a predetermined portion may overlap with the second metal pad layer, the first electrode, and the third electrode to be formed at least in a subsequent process.

A second interlayer insulating layer 33 is formed on the first interlayer insulating layer 31 so as to cover the first metal pad layer 32. At this time, the planarization process may be performed by chemical mechanical polishing (CMP) to planarize the surface of the second interlayer insulating layer 33.

Next, the first via hole and the second to expose a predetermined portion of the first metal pad layer 32 by performing photolithography using anisotropic etching such as dry etching on the second interlayer insulating layer 33. Form a via hole. At this time, the first via hole and the second via hole are formed as follows. First, after the photoresist is applied on the second interlayer insulating layer 33, exposure and development are performed, and the first metal pad layer 32 is spaced a predetermined distance along the cutting line I-I 'of the layout of FIG. ) And a photoresist pattern (not shown) having two openings each exposing the surface of the second interlayer insulating layer that overlaps the layer). Then, the exposed second interlayer insulating layer is removed by anisotropic etching such as dry etching. A first via hole and a second via hole exposing the surfaces of the first metal pad layer 32 are formed.

Accordingly, the first via hole becomes a first plug 340 forming portion electrically connecting the first electrode and the first metal pad layer 32 formed in a subsequent process, and the second via hole is the first metal pad layer 32. ) And a second plug 341 forming portion electrically connecting the third electrode.

After removing the photoresist pattern by a method such as oxygen ashing (O ₂ ahing), and then forming a conductive layer of a metal such as tungsten on the second interlayer insulating layer 33 to sufficiently fill the first and second via holes. The first plug 340 and the second plug 341 remaining only in the first via hole and the second via hole are formed by exposing the surface of the second interlayer insulating layer 32 by CMP or the like.

The first metal layer 35 to be used as the first electrode 35 is deposited on the second interlayer insulating layer 33 so as to contact the surfaces of the exposed first plug 340 and the second plug 341. Form. In this case, the first metal layer may be formed by depositing Al, W, TiN, Cu, Ti, TiW, Ta, or the like with a thickness of about 100-3000 kPa by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Next, a first insulating film 36 to be used as the first dielectric film 36 is formed on the first metal layer to a predetermined thickness. In this case, the first insulating film is formed by depositing an insulator such as SiO _x , SiO _x N _1-x , SiN, Ta ₂ O ₅ , or the like by a PVD or CVD method to a thickness of about 100-2000 μs.

After the photoresist is applied onto the first insulating film 36, exposure and development are performed to form a photoresist pattern (not shown) that exposes a predetermined portion of the first insulating film. At this time, the photoresist pattern is zigzag, such as 'c' character, 'r' character or 's' character partially overlapping the first plug 340 and the second plug 341 so as to define the first electrode forming portion of the capacitor. Determine the layout to have a (jig jag) shape. In this case, in the embodiment of the present invention, the first electrode forming portion is defined in the form of 'c' or 'S', but in addition, it may be formed to maximize the surface area of the lower electrode of the capacitor in various curved shapes. Of course.

Next, the first insulating film and the first metal layer of the portion not protected by the photoresist pattern are sequentially removed by anisotropic etching such as dry etching to expose a predetermined portion of the second interlayer insulating layer, and then the photoresist pattern is removed.

Therefore, on the second interlayer insulating layer 33, for example, a first electrode 35 having a 'c' shape and a first dielectric film 36 having the same layout pattern as the 35 are formed. The first electrode is electrically connected to the first metal layer pad 32 through the first plug 340, and the upper surface of the second plug 341 is exposed again.

The second interlayer insulating layer 33 includes second metal layers 370 and 371 for forming the second electrode 370 and the second metal layer pad 371 so as to cover the surfaces of the second dielectric layer 36 and the second plug 341. It is formed in a predetermined thickness on the phase. In this case, the second metal layer may be formed by depositing Al, W, TiN, Cu, Ti, TiW, Ta, or the like with a thickness of about 100-3000Å by physical vapor deposition (PVD) or chemical vapor deposition (CVD). The second metal layer may be formed using a wiring layer forming process for forming another metal wiring.

Next, after the photoresist is applied on the second metal layer, exposure and development are performed to have the same pattern as the first electrode 35 and the dielectric film 36 formed in the previous step, and the second plug 341 is also provided. A sufficient photoresist pattern (not shown) is formed. At this time, in the embodiment of the present invention, the photoresist pattern portion covering the region overlapping with the second plug 341 is formed in a rectangular shape on the layout, but sufficient overlap margin for forming a contact portion for electrical connection with the first plug 341 is provided. Of course, it can be formed in various forms having a.

The second metal layer, which is not protected by the photoresist pattern, is removed by anisotropic etching, such as dry etching, to form the second electrode 370 on the first dielectric layer 360 and to be in electrical contact with the second plug 341. The second metal layer pad 371 is formed.

Since the role of the second metal layer pad 371 in the above process is for electrical connection between the second plug 341 and the fifth plug 412 to be formed in a subsequent process, the fifth plug and the second plug 371 may be electrically connected. If the connection can be secured, the formation of the 371 can be omitted. Therefore, in the photolithography process for forming the second electrode 370, the second metal layer may be left only on the second dielectric layer 36 and removed in the remaining regions.

Next, the photoresist pattern is removed by a method such as oxygen ashing to expose the top surfaces of the second electrode 370 and the second metal layer pad 371.

FIG. 5 is a sectional view taken along the cutting line II-II 'of FIG. 3 as a subsequent process step which is performed after the process steps of FIGS. 4A and 4B.

Referring to FIG. 5, a second insulating layer to be used as the second dielectric layer 38 is formed on the second interlayer insulating layer 33 including the surface of the second electrode 370. In this case, the second insulating layer may be formed by depositing an insulator such as SiOx, SiO _x N _1-x , SiN, Ta ₂ O ₅ , or the like by using a PVD or CVD method.

Then, a third metal layer is formed on the second insulating film to form a thin film for forming the third electrode as one electrode of the capacitor. In this case, the third metal layer may be formed by depositing Al, W, TiN, Cu, Ti, TiW, Ta, or the like with a thickness of about 100-3000 kPa by physical vapor deposition (PVD) or chemical vapor deposition (CVD).

Next, after the photoresist is applied on the third metal layer, exposure and development are performed, and most of the regions on the layout of the second electrode 370 have a predetermined free space and overlap the first plug 340 sufficiently. A photoresist pattern (not shown) that does not overlap the upper surface of the second electrode 370 that is not opposite to each other is formed.

Accordingly, the surface of the third metal layer covered by the photoresist pattern overlaps most of the upper portion of the second electrode 370, but does not overlap the upper portion of the second 370 electrode opposite to the side where the first plug 340 is not formed. The portion overlaps with most of the upper region of the second electrode 370. In this case, the portion that does not overlap with the second electrode is an area that comes into contact with the sixth plug 413 that is to be in electrical contact with the second electrode in a subsequent process.

And a second electrode 39 formed of the third metal layer remaining by removing the third metal layer and the second insulating film which are not protected by the photoresist pattern by an anisotropic etching such as dry etching, and the second insulating film remaining. The dielectric film 38 is formed.

Then, the photoresist pattern is removed by a method such as oxygen ashing.

Accordingly, as shown in the drawing, the surface of the second electrode 370 covered by the second dielectric layer 38 and the third electrode 39 may be formed on the surface of the second electrode 370 except for the portion where the sixth plug is to be formed. Most of the top surface and side.

6A and 6B, the third interlayer insulating layer 40 may be formed of an oxide film or the like to sufficiently cover the exposed surfaces of the second electrode 370, the third electrode 39, and the second metal layer pad 371. An insulating material is deposited to form on the second interlayer insulating layer 33.

After the photoresist is applied on the third interlayer insulating layer 40, the photoresist is exposed and developed to overlap a portion of the upper surface of the third electrode 39, and a portion of the upper surface of the second metal layer pad 371. A photoresist pattern having a plurality of openings is formed to overlap and expose a surface of the third interlayer insulating layer 40 overlapping with a part of the surface of the second electrode 370 not covered by the second dielectric layer 38.

Then, a predetermined portion of the third interlayer insulating layer 40 which is not protected by the photoresist pattern is removed by anisotropic etching, such as dry etching, so that a part of the upper surface of the third electrode 39 and the second metal layer pad are removed. A third via hole and a fourth via hole exposing an upper surface of the 371, a part of the second electrode 370 not covered by the second dielectric layer 38, and a fifth via hole and a sixth via hole, respectively. do. At this time, in the exemplary embodiment of the present invention, the third via hole and the fourth via hole are formed to expose the upper surface of the third electrode 39, but only one of the via holes may be formed and the rest may be omitted.

Then, the photoresist pattern is removed by a method such as oxygen ashing to expose the upper surface of the third interlayer insulating layer 40.

Then, a conductive layer is formed of metal or the like on the third interlayer insulating layer to fill the third to sixth via holes with a conductor. In this case, the conductive layer may be formed of tungsten.

In addition, a planarization process such as CMP is performed on the conductive layer to expose the surface of the third interlayer insulating layer 40 so that the conductive layer remains only in the third through sixth via holes, so that the third plug 410 and the fourth plug ( 411, the fifth plug 412, and the sixth plug 413.

Next, a conductive layer covering the third to sixth plug surfaces is formed of metal, and then patterned by photolithography to electrically connect the third to fifth plugs 410, 411, and 412 to each other. The first connection electrode 420 and the second connection electrode 421 contacting the sixth plug 413 are formed.

Accordingly, the first electrode 35 and the third electrode 39 may include the first plug 340, the first metal layer pad 32, the second plug 341, the second metal layer pad 371, and the fifth plug ( 412, the first connection electrode 420, and the third to fourth plugs 410 and 411 are electrically connected to each other to be used as one electrode of the capacitor, while the lower, upper and side surfaces of the second electrode 370 are formed. Most of them are covered by the first dielectric film 36 and the second dielectric film 38 and used as other electrodes of the capacitor.

Accordingly, the present invention uses the first electrode and the third electrode as one electrode on the substrate, and the lower electrode, the side surface, and the upper surface of the second electrode using the second electrode with the dielectric film interposed therebetween as the other electrode. Since most of them use the effective area of the capacitor except for a part of, there is an advantage of providing a capacitor which is superior in capacitance increase compared to the MIM capacitor of the flat plate structure.

Claims (6)

Forming a first interlayer insulating layer on the substrate, and forming a first metal layer pad having a predetermined length and running in a first direction on the first insulating layer; Forming a second interlayer dielectric layer on the first interlayer dielectric layer so as to cover the first metal layer pad sufficiently; Removing at least one portion of the second insulating layer to form at least two or more first via holes and second via holes exposing predetermined portions of the metal layer pads at predetermined intervals; Forming a first plug and a second plug to fill the first to second via holes with a conductor; Sequentially forming a first electrode, a first dielectric layer, and a second electrode in a zigzag shape spaced apart from the second plug and in contact with the first plug, on the second interlayer insulating layer; Forming a second dielectric layer on the second electrode covering the exposed surface of the second electrode but exposing a portion of the surface of the second electrode; Forming a third electrode only on the second dielectric layer; Forming a second interlayer insulating layer covering the third electrode and the second electrode on the second interlayer insulating layer; A third plug which forms a plurality of via holes and contacts the third electrode by removing a predetermined portion of the third interlayer insulating layer, a fourth plug that contacts the second plug, and does not overlap the third electrode Forming a fifth plug in contact with the second electrode in the plurality of via holes, respectively; Forming a first connection electrode electrically connecting the third plug and the fourth plug and a second connection electrode electrically connected to the fifth plug on the third interlayer insulating layer. Way. The method according to claim 1, Wherein the first electrode and the third electrode are formed by depositing any one of Al, W, TiN, Cu, Ti, TiW, and Ta to a thickness of about 100-3000 Å. The method according to claim 1, The second electrode is a capacitor manufacturing method of a semiconductor device, characterized in that formed by depositing any one of Al, W, TiN, Cu, Ti, TiW, Ta to a thickness of 100-3000Å. The method according to claim 1, And the second electrode is formed using a part of a wiring layer for forming another metal wiring. The method according to claim 1, The first dielectric film and the first electrode is a capacitor manufacturing method of a semiconductor device, characterized in that formed in the planar '' 'shape. The method according to claim 1, And the first dielectric layer and the first electrode are formed in a planar 'S' shape.