CN113921712A - Layout structure, semiconductor device structure and manufacturing method thereof - Google Patents
Layout structure, semiconductor device structure and manufacturing method thereof Download PDFInfo
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- CN113921712A CN113921712A CN202111536910.8A CN202111536910A CN113921712A CN 113921712 A CN113921712 A CN 113921712A CN 202111536910 A CN202111536910 A CN 202111536910A CN 113921712 A CN113921712 A CN 113921712A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000003990 capacitor Substances 0.000 claims abstract description 117
- 239000000463 material Substances 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000000034 method Methods 0.000 claims abstract description 31
- 239000010410 layer Substances 0.000 claims description 626
- 239000011229 interlayer Substances 0.000 claims description 77
- 239000003989 dielectric material Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 229910052719 titanium Inorganic materials 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- 239000010949 copper Substances 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 229910052732 germanium Inorganic materials 0.000 description 2
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- 239000012212 insulator Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- -1 gallium arsenide Chemical class 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
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- 230000001360 synchronised effect Effects 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a layout structure, a semiconductor device structure and a manufacturing method thereof, wherein the semiconductor device structure comprises an interconnection structure formed on a substrate of a device area and a capacitor structure formed on the substrate of a redundant area, and the capacitor structure is formed on the substrate of the redundant area, so that the area of the device area can be prevented from being occupied. The material of the first electrode layer in the capacitor structure is the same as that of the first conductive layer or the contact layer in the interconnection structure, so that the first electrode layer and the first conductive layer or the contact layer can be formed in the same process step, and masks are saved. Furthermore, the material of part of the second electrode layer in the capacitor structure is the same as that of the second conductive layer in the interconnection structure, and the second electrode layer in the capacitor structure and the second conductive layer in the interconnection structure can be formed in the same process step, so that the mask can be further saved.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a layout structure, a semiconductor device structure and a manufacturing method thereof.
Background
The capacitor is an important component unit in an integrated circuit and is widely applied to chips such as a memory, microwaves, radio frequencies, smart cards, high voltage and filtering chips and the like. In a Semiconductor device, such as a MOS (Metal-Oxide-Semiconductor) device, a commonly used capacitor generally includes an MIM (Metal-insulator-Metal) capacitor. MIM capacitors can provide electrical characteristics superior to MOS capacitors or PN junction capacitors in some special applications because MOS capacitors and PN junction capacitors are limited in their own structures and electrodes easily generate a hole layer when operating, resulting in a reduction in their frequency characteristics. Whereas MIM capacitors may provide better frequency and temperature dependent characteristics. However, in the semiconductor device structure, the capacitor structure is usually formed in the device region of the semiconductor device, and therefore the capacitor structure needs to be isolated from the adjacent devices, which occupies the area of the device region, and the capacitor structure and other devices in the device region are formed asynchronously, so that an additional mask layer needs to be added when the capacitor structure is formed.
Disclosure of Invention
The invention aims to provide a layout structure, a semiconductor device structure and a manufacturing method thereof, so as to avoid the area of a device area occupied by a capacitor structure.
Another objective of the present invention is to reduce the mask layer used in the manufacturing process of the capacitor structure.
To achieve the above object, the present invention provides a semiconductor device structure comprising: a substrate having a device region and a redundant region; the interconnection structure is formed on the substrate of the device region and comprises a first conductive layer, a contact layer and a second conductive layer which are sequentially stacked from bottom to top; the capacitor structure comprises a first electrode layer, an inter-electrode dielectric layer and a second electrode layer which are sequentially stacked from bottom to top, wherein partial materials of the first electrode layer are the same as those of the first conducting layer or those of the contact layer, partial materials of the second electrode layer are the same as those of the first conducting layer, and partial materials of the second electrode layer are the same as those of the second conducting layer.
Optionally, in the semiconductor device structure, the semiconductor device structure further includes an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer has a contact opening and a capacitor opening, the capacitor opening penetrates through the interlayer dielectric layer in a partial thickness of the redundant region, the contact opening penetrates through the interlayer dielectric layer in a partial thickness of the device region, the first conductive layer is embedded in the interlayer dielectric layer at the bottom of the contact opening, the contact layer fills the contact opening and is electrically connected to the first conductive layer, and the second conductive layer covers the contact layer and extends to cover a part of the interlayer dielectric layer in the device region.
Optionally, in the semiconductor device structure, the first electrode layer includes a first portion, a second portion, and a third portion, where the first portion is embedded in the interlayer dielectric layer at the bottom of the capacitor opening, a top surface of the first portion is flush with a top surface of the first conductive layer, the second portion covers a sidewall and a bottom of the capacitor opening and is electrically connected to the first portion, the third portion covers the second portion and is electrically connected to the second portion, and the inter-electrode dielectric layer covers the third portion of the first electrode layer.
Optionally, in the semiconductor device structure, the second electrode layer includes a fourth portion and a fifth portion, the fourth portion covers the inter-electrode dielectric layer, the fourth portion has an electrode layer opening aligned with the capacitor opening, and the fifth portion is filled in the electrode layer opening.
Optionally, in the semiconductor device structure, the material of the second portion of the first electrode layer and the material of the contact layer are both metal tungsten; the fourth part of the second electrode layer and the third part of the first electrode layer are both made of metal titanium and titanium nitride; the material of the first part of the first electrode layer, the material of the fifth part of the second electrode layer, the material of the first conducting layer and the material of the second conducting layer are all metal aluminum or metal copper.
Optionally, in the semiconductor device structure, the interlayer dielectric layer is made of silicon oxide.
Optionally, in the semiconductor device structure, the capacitor structure further includes a connection layer formed on the interlayer dielectric layer and a conductive plug formed in the interlayer dielectric layer, the conductive plug penetrates through the inter-electrode dielectric layer and is electrically connected to the first electrode layer, and the first electrode layer is electrically connected to the connection layer through the conductive plug.
Based on the same inventive concept, the invention also provides a manufacturing method of the semiconductor device structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a device area and a redundant area; and forming an interconnection structure on the substrate of the device area, and forming a capacitor structure on the substrate of the redundant area, wherein the capacitor structure comprises a first electrode layer, an inter-electrode dielectric layer and a second electrode layer which are sequentially stacked from bottom to top, the interconnection structure comprises a first conductive layer, a contact layer and a second conductive layer which are sequentially stacked from bottom to top, partial materials of the first electrode layer are the same as those of the first conductive layer or those of the contact layer, partial materials of the second electrode layer are the same as those of the first conductive layer, and partial materials of the second electrode layer are the same as those of the second conductive layer.
Optionally, in the manufacturing method of the semiconductor device structure, the forming method of the interconnect structure and the capacitor structure includes: forming a first conductive layer on the substrate of the device region, and forming a first portion of a first electrode layer on the substrate of the redundant region, the first portion of the first electrode layer covering a portion of the substrate of the redundant region, the first conductive layer covering a portion of the substrate of the device region; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the first conducting layer, the first part of the first electrode layer and the substrate; forming a contact opening and a capacitor opening in the interlayer dielectric layer, wherein the capacitor opening penetrates through the interlayer dielectric layer with partial thickness of the redundant region and exposes the first part of the first electrode layer, and the contact opening penetrates through the interlayer dielectric layer with partial thickness of the device region and exposes the first conductive layer; sequentially forming a first film layer, a second film layer, an inter-electrode dielectric material layer and a third film layer, wherein the first film layer fills the contact opening and extends to cover the bottom wall and the side wall of the capacitor opening and the interlayer dielectric layer, the second film layer covers the first film layer, the inter-electrode dielectric material layer covers the second film layer, the third film layer covers the inter-electrode dielectric material layer, and an electrode layer opening aligned with the capacitor opening is formed in the third film layer; removing the third film layer on the interlayer dielectric layer, and reserving the third film layer on the bottom wall and the side wall of the capacitor opening to form a fourth part of a second electrode layer, removing the inter-electrode dielectric material layer on the interlayer dielectric layer, and reserving the inter-electrode dielectric material layer on the bottom wall and the side wall of the capacitor opening to form an inter-electrode dielectric layer, and removing the second film layer on the interlayer dielectric layer, and reserving the second film layer on the bottom wall and the side wall of the capacitor opening to form a third part of a first electrode layer, and removing the first film layer on the interlayer dielectric layer, and reserving the first film layer on the bottom wall and the side wall of the capacitor opening to form a second part of the first electrode layer, and reserving the first film layer in the contact opening to form the contact layer; and forming a second conductive layer and a fifth part of the second electrode layer, wherein the fifth part of the second electrode layer is filled in the electrode layer opening, and the second conductive layer covers the contact layer and extends to cover the interlayer dielectric layer of the device region.
Based on the same inventive concept, the present invention further provides a layout structure for manufacturing the semiconductor device structure, wherein the layout structure has an adjacent device layout region and a redundant layout region, and the layout structure includes: an interconnect structure layout located in the device layout region, the interconnect structure layout including a first conductive layer pattern, a second conductive layer pattern, and a contact layer pattern, the first conductive layer pattern extending along a first direction, the second conductive layer pattern extending along a second direction, and a portion of the second conductive layer pattern overlapping a portion of the first conductive layer pattern, the contact layer pattern being aligned with an overlapping portion of the second conductive layer pattern and a portion of the first conductive layer pattern, wherein the first direction is perpendicular to the second direction; and the capacitor structure layout is positioned in the redundant layout area and is separated from the interconnection structure layout, and the capacitor structure layout comprises a first electrode layer pattern, an inter-electrode dielectric layer pattern and a second electrode layer pattern which are sequentially stacked from bottom to top.
Optionally, in the layout structure, the first conductive layer pattern, the contact layer pattern, the second conductive layer pattern, the first electrode layer pattern, the inter-electrode dielectric layer pattern, and the second electrode layer pattern are rectangular.
Optionally, in the layout structure, the size of the second electrode layer pattern is smaller than the size of the inter-electrode dielectric layer pattern, the size of the inter-electrode dielectric layer pattern is smaller than the size of the first electrode layer pattern, and a part of the first electrode layer pattern is exposed by the inter-electrode dielectric layer pattern.
Optionally, in the layout structure, the capacitor structure layout further includes a conductive plug pattern and a connection layer pattern, the connection layer pattern extends from the redundant layout area to the exposed first electrode layer pattern, and the conductive plug pattern is located between the connection layer pattern and the first electrode layer pattern.
In the layout structure, the semiconductor device structure and the manufacturing method thereof provided by the invention, the semiconductor device structure comprises an interconnection structure formed on the substrate of the device region and a capacitor structure formed on the substrate of the redundant region, and the capacitor structure is formed on the substrate of the redundant region, so that the occupation of the area of the device region can be avoided. Furthermore, the material of the first electrode layer in the capacitor structure is the same as the material of the first conductive layer or the contact layer in the interconnection structure, so that the first electrode layer in the capacitor structure and the first conductive layer or the contact layer in the interconnection structure can be formed in the same process step, thereby saving the mask. Furthermore, the material of part of the second electrode layer in the capacitor structure is the same as the material of the second conductive layer in the interconnection structure, so that the second electrode layer in the capacitor structure and the second conductive layer in the interconnection structure can be formed in the same process step, thereby further saving the mask.
Drawings
Fig. 1 is a schematic cross-sectional view of a semiconductor device structure of an embodiment of the present invention.
Fig. 2 is a flow chart illustrating a method of fabricating a semiconductor device structure according to an embodiment of the present invention.
Fig. 3 is a schematic cross-sectional view of a substrate formed by the method of manufacturing a semiconductor device structure according to an embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a first portion of the first conductive layer and the first electrode layer formed in the method of manufacturing the semiconductor device structure of the embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of an interlayer dielectric layer formed in the method of manufacturing a semiconductor device structure according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a contact opening and a capacitor opening formed in a method of fabricating a semiconductor device structure according to an embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a first film layer, a second film layer, and a third film layer formed in a method of fabricating a semiconductor device structure according to an embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of the second portion of the first electrode layer, the third portion of the first electrode layer, the second electrode layer, the inter-electrode dielectric layer, and the contact layer formed in the method for manufacturing the semiconductor device structure according to the embodiment of the present invention.
Fig. 9 is a schematic structural diagram of a layout structure according to an embodiment of the present invention.
100-a substrate; 101-interlayer dielectric layer; 101 a-contact openings; 101 b-capacitive opening; 110-an interconnect structure; 111-a first conductive layer; 112-a contact layer; 113-a second conductive layer; 120-a capacitive structure; 121-a first electrode layer; 1211-first part; 1212-a second portion; 1212 a-a first membrane layer; 1213-third part; 1213 a-second film layer; 122-inter-electrode dielectric layer; 122 a-a layer of inter-electrode dielectric material; 123-a second electrode layer; 1231-fourth section; 1231 a-a third film layer; 1231 b-electrode layer opening; 1232-part five; 210-interconnect structure layout; 211 — a first conductive layer pattern; 212-a contact layer pattern; 213-second conductive layer pattern; 220-capacitor structure layout; 221-a first electrode layer pattern; 222-inter-electrode dielectric layer pattern; 223-a second electrode layer pattern; 224-a conductive plug pattern; 225-connecting layer pattern.
Detailed Description
The layout structure, the semiconductor device structure and the manufacturing method thereof proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 1 is a schematic cross-sectional view of a semiconductor device structure of an embodiment of the present invention. As shown in fig. 1, the semiconductor device structure includes: a substrate 100, the substrate 100 having a device region I and a redundant region II; an interconnect structure 110 formed on the substrate 100 of the device region I, wherein the interconnect structure 110 includes a first conductive layer 111, a contact layer 112 and a second conductive layer 113 stacked in sequence from bottom to top; and a capacitor structure 120 formed on the substrate 100 of the redundant region II, wherein the capacitor structure 120 includes a first electrode layer 121, an inter-electrode dielectric layer 122, and a second electrode layer 123 stacked in sequence from bottom to top, a part of the material of the first electrode layer 121 is the same as the material of the first conductive layer 111 or the material of the contact layer 112, a part of the material of the second electrode layer 123 is the same as the material of the first conductive layer 111, and a part of the material of the second electrode layer 123 is the same as the material of the second conductive layer 113. Since the capacitor structure 120 is formed on the substrate 100 of the redundant region II, the area of the device region I can be avoided.
Further, as shown in fig. 1, the semiconductor device structure further includes an Inter Metal Dielectric (ILD) layer 101 formed on the substrate 100, where the ILD layer 101 is made of an insulating material, for example, the ILD layer 101 is made of silicon oxide. In other embodiments of the invention, the material of the interlayer dielectric layer 101 may be a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9) or an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant less than 2.6), so as to reduce the parasitic capacitance in the interconnect structure 110. The interlayer dielectric layer 101 may isolate the interconnect structure 110 from the capacitor structure 120.
In addition, the capacitor structure 120 further includes a connection layer (not shown) formed on the interlayer dielectric layer 101, and a conductive plug (not shown) formed in the interlayer dielectric layer 101, the conductive plug penetrating the interlayer dielectric layer 101 and electrically connected to the first electrode layer 121, and the first electrode layer 121 is electrically connected to the connection layer through the conductive plug. In addition, in another embodiment of the present invention, the conductive plug may be electrically connected to the first electrode layer 121 or the second electrode layer 123 separately, so as to electrically connect the first electrode layer 121 or the second electrode layer 123 to an external circuit. The conductive plug may be made of tungsten. The material of the connection layer may be the same as the material of the first electrode layer 121 or the material of the second electrode layer 123, that is, the material of the connection layer may be metal aluminum. The interlayer dielectric layer 101 is provided with a contact opening and a capacitor opening, the capacitor opening penetrates through the interlayer dielectric layer 101 in the partial thickness of the redundant region II, and the contact opening penetrates through the interlayer dielectric layer 101 in the partial thickness of the device region I. The depth of the contact opening and the depth of the capacitor opening can be the same, for example, the depth of the contact opening and the depth of the capacitor opening can be both 1000 angstroms to 2000 angstroms.
Wherein the bottom of the contact opening is flush with the top surface of the first conductive layer 111. The cross-sectional shape of the contact opening may be an inverted trapezoid, i.e., the width of the bottom of the contact opening is smaller than the width of the top of the contact opening, so as to facilitate the subsequent filling of the contact layer 112. The cross-sectional shape of the capacitor opening may be rectangular, and the width of the capacitor opening may be greater than the width of the top of the contact opening. The width of the top of the contact opening may be, for example, less than 0.8 microns, and the width of the capacitor opening may be, for example, greater than 1 micron, to meet the design rules of the capacitor structure 120 and thus meet the performance requirements of the capacitor structure 120.
As shown in fig. 1, the first conductive layer 111 is embedded in the interlayer dielectric layer 101 at the bottom of the contact opening, the contact layer 112 fills the contact opening and is electrically connected to the first conductive layer 111, and the second conductive layer 113 covers the contact layer 112 and extends to cover a portion of the interlayer dielectric layer 101 in the device region I.
In this embodiment, as shown in fig. 1, the first electrode layer 121 includes a first portion 1211, a second portion 1212, and a third portion 1213, where the first portion 1211 is embedded in the interlayer dielectric layer 101 at the bottom of the capacitor opening, and a top surface of the first portion 1211 is flush with a top surface of the first conductive layer 111, that is, a thickness of the first portion 1211 of the first electrode layer 121 is the same as a thickness of the first conductive layer 111. Further, the material of the first portion 1211 of the first electrode layer 121 is the same as the material of the first conductive layer 111, so that the first portion 1211 of the first electrode layer 121 and the first conductive layer 111 can be formed in the same process step, thereby saving masks.
In this embodiment, the material of the first portion 1211 of the first electrode layer 121 and the material of the first conductive layer 111 can be both metal, such as metal aluminum or metal copper.
With continued reference to fig. 1, the second portion 1212 of the first electrode layer 121 covers the sidewalls and bottom of the capacitor opening and is electrically connected to the first portion 1211. The material of the second portion 1212 of the first electrode layer 121 is the same as the material of the contact layer 112, so that the second portion 1212 of the first electrode layer 123 and the contact layer 112 can be formed in the same step, thereby further saving masks and saving process time. The material of the second portion 1212 of the first electrode layer 121 is the same as the material of the contact layer 112, and the material of the second portion 1212 of the first electrode layer and the material of the contact layer may be, for example, metal tungsten.
As shown in fig. 1, the third portion 1213 of the first electrode layer 121 covers the second portion 1212 and is electrically connected to the second portion 1212, and optionally, the third portion 1213 of the first electrode layer 121 includes a stacked titanium layer and a titanium nitride layer, or the third portion 1213 of the first electrode layer 121 includes titanium and titanium nitride, so that good electrical conductivity can be achieved, and adhesion between the second portion 1212 of the first electrode layer 121 and the inter-electrode dielectric layer 122 can be better achieved.
The inter-electrode dielectric layer 122 covers the third portion 1213 of the first electrode layer 121, i.e. the inter-electrode dielectric layer 122 is deposited along the surface of the first electrode layer 121. The inter-electrode dielectric layer 122 is mainly used for isolating the first electrode layer 121 and the second electrode layer 123. The inter-electrode dielectric layer 122 may be made of silicon oxide (SiO)2) Or silicon nitride (SiN), in other embodiments of the present invention, the inter-electrode dielectric layer 122 may be made of a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide, such as hafnium oxide (HfO)2) Or titanium dioxide (TiO)2). The high-k dielectric material is selected, so that the capacitance value of the capacitor structure is improved, and the density of the capacitor can be correspondingly improved.
As shown in fig. 1, the second electrode layer 123 includes a fourth portion 1231 and a fifth portion 1232, the fourth portion 1231 covers the inter-electrode dielectric layer 122, and the fourth portion 1231 has an electrode layer opening aligned with the capacitor opening therein, the electrode layer opening can be used as an alignment mark in a process, and the fifth portion 1232 is filled in the electrode layer opening. Further, the top surface of the fifth portion 1232 of the second electrode layer 123 is close to the same level as the top surface of the second conductive layer 113, so as to avoid affecting the photolithography process.
Specifically, the fourth portion 1231 of the second electrode layer 123 includes a titanium layer and a titanium nitride layer, which are stacked, or the fourth portion 1231 of the second electrode layer 123 includes titanium and titanium nitride, so that good conductivity can be achieved, and adhesion between the inter-electrode dielectric layer 122 and the fifth portion 1232 of the second electrode layer 123 can be better achieved.
Preferably, the material of the fifth portion 1232 of the second electrode layer 123 is the same as the material of the second conductive layer 113, for example, the material of the fifth portion 1232 of the second electrode layer 123 and the material of the second conductive layer 113 may both be copper or aluminum. Thus, the fifth portion 1232 of the second electrode layer 123 and the second conductive layer 113 can be formed in the same process step, thereby saving process time.
Fig. 2 is a flow chart illustrating a method of fabricating a semiconductor device structure according to an embodiment of the present invention. Referring to fig. 2, correspondingly, the present invention further provides a method for manufacturing a semiconductor device structure, including: step S1: providing a substrate, wherein the substrate is provided with a device area and a redundant area; step S2: the interconnection structure is formed on the substrate of the device area, the capacitor structure is formed on the substrate of the redundant area, the capacitor structure comprises a first electrode layer, an inter-electrode dielectric layer and a second electrode layer which are sequentially stacked from bottom to top, the interconnection structure comprises a first conducting layer, a contact layer and a second conducting layer which are sequentially stacked from bottom to top, partial materials of the first electrode layer are the same as those of the first conducting layer or those of the contact layer, partial materials of the second electrode layer are the same as those of the first conducting layer, and partial materials of the second electrode layer are the same as those of the second conducting layer.
Fig. 3 is a schematic cross-sectional view of a substrate formed by the method of manufacturing a semiconductor device structure according to an embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of a first portion of the first conductive layer and the first electrode layer formed in the method of manufacturing the semiconductor device structure of the embodiment of the invention. Fig. 5 is a schematic cross-sectional view of an interlayer dielectric layer formed in the method of manufacturing a semiconductor device structure according to an embodiment of the present invention. Fig. 6 is a schematic cross-sectional view of a contact opening and a capacitor opening formed in a method of fabricating a semiconductor device structure according to an embodiment of the present invention. Fig. 7 is a schematic cross-sectional view of a first film layer, a second film layer, and a third film layer formed in a method of fabricating a semiconductor device structure according to an embodiment of the present invention. Fig. 8 is a schematic cross-sectional view of the second portion of the first electrode layer, the third portion of the first electrode layer, the second electrode layer, the interlayer dielectric layer, and the contact layer formed in the method of manufacturing the semiconductor device structure according to the embodiment of the present invention. The method for manufacturing the semiconductor device structure provided by the present invention will be described in more detail with reference to fig. 3 to 8.
In step S1, as shown in fig. 3, a substrate 100 is provided, the substrate 100 having a device region I and a redundant region II. The material of the substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC), or Silicon On Insulator (SOI), Germanium On Insulator (GOI); or other materials such as III-V compounds such as gallium arsenide, in this embodiment, the material of the substrate 100 is single crystal silicon (Si).
In this embodiment, a well region, a source region, and a drain region are further formed in the substrate 100 of the device region I, and a gate structure is further formed on the substrate 100 of the device region I. The redundant area II may be, for example, a metal dummy area (metal dummy area) of the substrate 100.
In step S2, as shown in fig. 4 to 8 and fig. 1, an interconnection structure 110 is formed on the substrate 100 in the device region I, and a capacitor structure 120 is formed on the substrate 100 in the redundant region II, the capacitor structure 120 includes a first electrode layer 121, an inter-electrode dielectric layer 122, and a second electrode layer 123 stacked in sequence from bottom to top, the interconnection structure 110 includes a first conductive layer 111, a contact layer 112, and a second conductive layer 113 stacked in sequence from bottom to top, a part of the material of the first electrode layer 121 is the same as the material of the first conductive layer 111 or the material of the contact layer 112, a part of the material of the second electrode layer 123 is the same as the material of the first conductive layer 111, and a part of the material of the second electrode layer 123 is the same as the material of the second conductive layer 113.
Specifically, the forming method of the interconnect structure 110 and the capacitor structure 120 includes: first, as shown in fig. 4, a first conductive layer 111 is formed on the substrate 100 of the device region I, and a first portion 1211 of a first electrode layer 121 is formed on the substrate 100 of the redundant region II, the first portion 1211 of the first electrode layer 121 covers a portion of the substrate 100 of the redundant region II, and the first conductive layer 111 covers a portion of the substrate 100 of the device region I. The material of the first conductive layer 111 is the same as the material of the first portion 1211 of the first electrode layer 121. The material of the first conductive layer 111 and the material of the first portion 1211 of the first electrode layer 121 are both copper or aluminum, and since the material of the first conductive layer 111 is the same as the material of the first portion 1211 of the first electrode layer 121, the first conductive layer 111 and the first portion 1211 of the first electrode layer 121 can be formed in a synchronous process step, thereby saving masks. Further, the first conductive layer 111 and the first portion 1211 of the first electrode layer 121 may be formed by an electroplating method or a physical vapor deposition method.
As shown in fig. 5, after the first conductive layer 111 and the first portion 1211 of the first electrode layer 121 are formed, an interlayer dielectric layer 101 is formed on the substrate 100, the interlayer dielectric layer 101 covers the first conductive layer 111, the first portion 1211 of the first electrode layer 121, and the substrate 100, and the interlayer dielectric layer 101 may be made of silicon oxide, which is used for isolating the interconnection structure 110 from the capacitor structure 120. The interlayer dielectric layer 101 may be formed by a chemical vapor deposition process.
Next, as shown in fig. 6, a contact opening 101a and a capacitor opening 101b are formed in the interlayer dielectric layer 101, the capacitor opening 101b penetrates through the interlayer dielectric layer 101 in the partial thickness of the redundant region II and exposes the first portion 1211 of the first electrode layer 121, and the contact opening 101a penetrates through the interlayer dielectric layer 101 in the partial thickness of the device region I and exposes the first conductive layer 111. The contact opening 101a and the capacitor opening 101b may be formed in the interlayer dielectric layer 101 by a dry etching process.
In addition, when the contact opening 101a and the capacitor opening 101b are formed in the interlayer dielectric layer 101, a conductive plug opening (not shown) is also formed in the redundant region II, that is, the contact opening 101a, the capacitor opening 101b and the conductive plug opening can be formed through the same mask.
Next, as shown in fig. 7, a first film layer 1212a, a second film layer 1213a, an inter-electrode medium material layer 122a and a third film layer 1231a are sequentially formed, the first film layer 1212a fills the contact opening 101a and extends to cover the bottom wall and the side wall of the capacitor opening 101b and the inter-electrode medium layer 101, the second film layer 1213a covers the first film layer 1212a, the inter-electrode medium material layer 122a covers the second film layer 1213a, the third film layer 1231a covers the inter-electrode medium material layer 122a, and the third film layer 1231a has an electrode layer opening 1231b aligned with the capacitor opening 101 b. In addition, the first film layer 1212a also fills the conductive plug opening to form a conductive plug.
The third film 1231a may include metal titanium and titanium nitride, and the third film 1231a may be formed by a physical vapor deposition process. The inter-electrode dielectric material layer 122a may be made of silicon oxide, and the inter-electrode dielectric material layer 122a may be formed by a chemical vapor deposition process (e.g., a high density plasma chemical vapor deposition process) or a furnace process. The second film layer 1213a may include titanium and titanium nitride, the first film layer 1212a may be tungsten, the first film layer 1212a may be formed by a pvd process, and the second film layer 1213a may be formed by a pvd process.
Next, as shown in fig. 8, the third film 1231a on the interlayer dielectric layer 101 is removed, and the third film layer 1231a on the bottom wall and the side wall of the capacitor opening 101b is remained to form a fourth portion 1231 of the second electrode layer 122, and removing the inter-electrode dielectric material layer 122a on the interlayer dielectric layer 101, and leaving the inter-electrode dielectric material layer 122a on the bottom wall and the side wall of the capacitor opening to form the inter-electrode dielectric layer 122, and removing the second film layer 1213a on the interlayer dielectric layer 101 and leaving the second film layer 1213a on the bottom wall and the sidewall of the capacitor opening to form a third portion 1213 of the first electrode layer 121, and removing the first film layer 1212a on the interlayer dielectric layer 101, and leaving the first film layer 1212a on the bottom wall and the sidewall of the capacitor opening to form a second portion 1212 of the first electrode layer 121, and retaining the first film layer 1212a within the contact opening to form the contact layer 112. The third film 1231a on the interlayer dielectric layer 101, the second film 1213a on the interlayer dielectric layer 101, the first film 1212a on the interlayer dielectric layer 101, and the inter-electrode dielectric material layer 122a on the interlayer dielectric layer 101 may be removed by a chemical mechanical polishing process.
Next, with continuing reference to fig. 1, a second conductive layer 113 and a fifth portion 1232 of the second electrode layer 123 are formed, the fifth portion 1232 of the second electrode layer 123 is filled in the electrode layer opening 1231b, and the second conductive layer 113 covers the contact layer 112 and extends to cover the interlayer dielectric layer 101 of the device region I.
Specifically, the method for forming the second conductive layer 113 and the fifth portion 1232 of the second electrode layer 123 includes: first, a fourth film layer (not shown) is formed, wherein the fourth film layer fills the electrode layer opening 1231b and extends to cover the interlayer dielectric layer 101 and the contact layer 112. Then, the fourth film layer is etched by a dry etching process to be divided, and the divided fourth film layer is used to form the second conductive layer 113 and the fifth portion 1232 of the second electrode layer 123. At this time, the fifth portion 1232 of the second electrode layer 123 exposes two sidewalls of the electrode layer opening 1231b, i.e., the fifth portion 1232 of the second electrode layer 123 is spaced apart from the sidewalls of the electrode layer opening 1231 b. Further, the fourth film may be divided into three parts, that is, a part of the fourth film may constitute the second conductive layer 113, a second part of the fourth film may constitute the fifth part 1232 of the second electrode layer 123, and a third part of the fourth film may constitute a connection layer, which is located on the dielectric layer of the redundant region and electrically connected to the conductive plug. That is, the second conductive layer 113, the second electrode layer 123, and the connection layer may be formed through the same mask layer.
Fig. 9 is a schematic structural diagram of a layout structure according to an embodiment of the present invention. Based on the same inventive concept, the invention also provides a layout structure, which is used in the manufacturing method of the semiconductor device structure to manufacture the semiconductor device structure.
As shown in fig. 9, the layout structure has a device layout area a1 and a redundant layout area a2 which are adjacent to each other, and the layout structure includes an interconnect structure layout 210 located in the device layout area a1, and a capacitor structure layout 220 located in the redundant area and spaced from the interconnect structure layout 210. The interconnect layout 210 may be used to form the interconnect structure 110 in the semiconductor device structure of the present embodiment, and the capacitor layout 220 may be used to form the capacitor structure 120 in the semiconductor device structure of the present embodiment. The interconnect structure layout 210 includes a first conductive layer pattern 211, a second conductive layer pattern 213, and a contact layer pattern 212, where the first conductive layer pattern 211 extends along a first direction, the second conductive layer pattern 213 extends along a second direction, and a portion of the second conductive layer pattern 213 overlaps a portion of the first conductive layer pattern 211, and the contact layer pattern 212 corresponds to an overlapping portion of the second conductive layer pattern 213 and a portion of the first conductive layer pattern 211, where the first direction is perpendicular to the second direction. The first conductive layer pattern 211, the contact layer pattern 212, and the second conductive layer pattern 213 are rectangular.
The capacitor structure layout 220 includes a first electrode layer pattern 221, an inter-electrode dielectric layer pattern 222, and a second electrode layer pattern 223, which are sequentially stacked from bottom to top. The first electrode layer pattern 221, the inter-electrode dielectric layer pattern 222, and the second electrode layer pattern 223 are rectangular. The size of the second electrode layer pattern 223 is smaller than that of the inter-electrode dielectric layer pattern 222, and the size of the inter-electrode dielectric layer pattern 222 is smaller than that of the first electrode layer pattern 221, that is, the projection of the inter-electrode dielectric layer pattern 222 and the projection of the second electrode dielectric layer pattern 223 are located in the projection of the first electrode layer pattern 221.
In addition, the electrode layer dielectric layer pattern 222 exposes a portion of the first electrode layer pattern 221. Further, the capacitor structure layout further includes a conductive plug pattern 224 and a connection layer pattern 225, the connection layer pattern 225 extends from the redundancy layout area a2 to the exposed first electrode layer pattern 221, that is, the connection layer pattern 225 is located outside the inter-electrode dielectric layer pattern 222, and a portion of the connection layer pattern 225 overlaps a portion of the first electrode layer pattern 221, that is, the connection layer pattern 225 covers a portion of the first electrode layer pattern 221. The conductive plug pattern 224 is positioned between the connection layer pattern 225 and the first electrode layer pattern 221, i.e., the conductive plug pattern 224 corresponds to an overlap of the connection layer pattern 225 and the first electrode layer pattern 221. The number of the conductive plug patterns 224 may be one or more than two, and conductive plugs in the semiconductor device structure may be formed through the conductive plug patterns 224.
In addition, in the manufacturing process of the semiconductor device, the inter-electrode dielectric layer pattern 222 and the film layer corresponding to the conductive plug pattern 224 may be formed through the same mask. The second electrode layer pattern 223 and the film layer corresponding to the connection pattern 225 may be formed through the same mask, so that the mask may be saved.
In summary, in the layout structure, the semiconductor device structure and the manufacturing method thereof according to the embodiments of the present invention, the semiconductor device structure includes the interconnection structure formed on the substrate of the device region, and the capacitor structure formed on the substrate of the redundant region, and the capacitor structure is formed on the substrate of the redundant region, so that the area occupied by the device region can be avoided. The material of the first electrode layer in the capacitor structure is the same as that of the first conductive layer or the contact layer in the interconnection structure, so that the first electrode layer and the first conductive layer or the contact layer can be formed in the same process step, and masks are saved. Furthermore, the material of part of the second electrode layer in the capacitor structure is the same as that of the second conductive layer in the interconnection structure, and the second electrode layer in the capacitor structure and the second conductive layer in the interconnection structure can be formed in the same process step, so that the mask can be further saved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (13)
1. A semiconductor device structure, comprising:
a substrate having a device region and a redundant region;
the interconnection structure is formed on the substrate of the device region and comprises a first conductive layer, a contact layer and a second conductive layer which are sequentially stacked from bottom to top;
the capacitor structure comprises a first electrode layer, an inter-electrode dielectric layer and a second electrode layer which are sequentially stacked from bottom to top, wherein partial materials of the first electrode layer are the same as those of the first conducting layer or those of the contact layer, partial materials of the second electrode layer are the same as those of the first conducting layer, and partial materials of the second electrode layer are the same as those of the second conducting layer.
2. The semiconductor device structure of claim 1, further comprising an interlayer dielectric layer formed on the substrate, wherein the interlayer dielectric layer has a contact opening and a capacitor opening therein, the capacitor opening penetrates through a portion of the thickness of the interlayer dielectric layer in the redundant region, the contact opening penetrates through a portion of the thickness of the interlayer dielectric layer in the device region, wherein the first conductive layer is embedded in the interlayer dielectric layer at the bottom of the contact opening, the contact layer fills the contact opening and is electrically connected to the first conductive layer, and the second conductive layer covers the contact layer and extends to cover a portion of the interlayer dielectric layer in the device region.
3. The semiconductor device structure of claim 2, wherein the first electrode layer comprises a first portion, a second portion and a third portion, the first portion is embedded in the interlayer dielectric layer at the bottom of the capacitor opening, the top surface of the first portion is flush with the top surface of the first conductive layer, the second portion covers the sidewall and the bottom of the capacitor opening and is electrically connected to the first portion, the third portion covers the second portion and is electrically connected to the second portion, and the inter-electrode dielectric layer covers the third portion of the first electrode layer.
4. The semiconductor device structure of claim 3, wherein the second electrode layer comprises a fourth portion and a fifth portion, the fourth portion covers the inter-electrode dielectric layer and has an electrode layer opening therein aligned with the capacitor opening, and the fifth portion fills in the electrode layer opening.
5. The semiconductor device structure of claim 4, wherein the material of the second portion of the first electrode layer and the material of the contact layer are both metal tungsten; the fourth part of the second electrode layer and the third part of the first electrode layer are both made of metal titanium and titanium nitride; the material of the first part of the first electrode layer, the material of the fifth part of the second electrode layer, the material of the first conducting layer and the material of the second conducting layer are all metal aluminum or metal copper.
6. The semiconductor device structure of any one of claims 1 to 4, wherein the interlayer dielectric layer is made of silicon oxide.
7. The semiconductor device structure of claim 2, wherein the capacitor structure further comprises a connection layer formed on the interlayer dielectric layer and a conductive plug formed in the interlayer dielectric layer, the conductive plug penetrating the interlayer dielectric layer and electrically connected to the first electrode layer, the first electrode layer electrically connected to the connection layer through the conductive plug.
8. A method of fabricating a semiconductor device structure, comprising:
providing a substrate, wherein the substrate is provided with a device area and a redundant area; and the number of the first and second groups,
the interconnection structure is formed on the substrate of the device area, the capacitor structure is formed on the substrate of the redundant area, the capacitor structure comprises a first electrode layer, an inter-electrode dielectric layer and a second electrode layer which are sequentially stacked from bottom to top, the interconnection structure comprises a first conducting layer, a contact layer and a second conducting layer which are sequentially stacked from bottom to top, partial materials of the first electrode layer are the same as those of the first conducting layer or those of the contact layer, partial materials of the second electrode layer are the same as those of the first conducting layer, and partial materials of the second electrode layer are the same as those of the second conducting layer.
9. The method of fabricating the semiconductor device structure of claim 8, wherein the method of forming the interconnect structure and the capacitor structure comprises:
forming a first conductive layer on the substrate of the device region, and forming a first portion of a first electrode layer on the substrate of the redundant region, the first portion of the first electrode layer covering a portion of the substrate of the redundant region, the first conductive layer covering a portion of the substrate of the device region;
forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the first conducting layer, the first part of the first electrode layer and the substrate;
forming a contact opening and a capacitor opening in the interlayer dielectric layer, wherein the capacitor opening penetrates through the interlayer dielectric layer with partial thickness of the redundant region and exposes the first part of the first electrode layer, and the contact opening penetrates through the interlayer dielectric layer with partial thickness of the device region and exposes the first conductive layer;
sequentially forming a first film layer, a second film layer, an inter-electrode dielectric material layer and a third film layer, wherein the first film layer fills the contact opening and extends to cover the bottom wall and the side wall of the capacitor opening and the interlayer dielectric layer, the second film layer covers the first film layer, the inter-electrode dielectric material layer covers the second film layer, the third film layer covers the inter-electrode dielectric material layer, and an electrode layer opening aligned with the capacitor opening is formed in the third film layer;
removing the third film layer on the interlayer dielectric layer, and reserving the third film layer on the bottom wall and the side wall of the capacitor opening to form a fourth part of a second electrode layer, removing the inter-electrode dielectric material layer on the interlayer dielectric layer, and reserving the inter-electrode dielectric material layer on the bottom wall and the side wall of the capacitor opening to form an inter-electrode dielectric layer, and removing the second film layer on the interlayer dielectric layer, and reserving the second film layer on the bottom wall and the side wall of the capacitor opening to form a third part of a first electrode layer, and removing the first film layer on the interlayer dielectric layer, and reserving the first film layer on the bottom wall and the side wall of the capacitor opening to form a second part of the first electrode layer, and reserving the first film layer in the contact opening to form the contact layer; and the number of the first and second groups,
and forming a second conductive layer and a fifth part of the second electrode layer, wherein the fifth part of the second electrode layer is filled in the electrode layer opening, and the second conductive layer covers the contact layer and extends to cover part of the interlayer dielectric layer of the device region.
10. A layout structure for manufacturing a semiconductor device structure according to any one of claims 1 to 7, wherein the layout structure has adjacent device layout regions and redundancy layout regions, and the layout structure comprises:
an interconnect structure layout located in the device layout region, the interconnect structure layout including a first conductive layer pattern, a second conductive layer pattern, and a contact layer pattern, the first conductive layer pattern extending along a first direction, the second conductive layer pattern extending along a second direction, and a portion of the second conductive layer pattern overlapping a portion of the first conductive layer pattern, the contact layer pattern corresponding to an overlapping portion of the second conductive layer pattern and a portion of the first conductive layer pattern, wherein the first direction is perpendicular to the second direction;
and the capacitor structure layout is positioned in the redundant layout area and is separated from the interconnection structure layout, and the capacitor structure layout comprises a first electrode layer pattern, an inter-electrode dielectric layer pattern and a second electrode layer pattern which are sequentially stacked from bottom to top.
11. The layout structure of claim 10, wherein the first conductive layer pattern, the contact layer pattern and the second conductive layer pattern, the first electrode layer pattern, the inter-electrode dielectric layer pattern and the second electrode layer pattern are all rectangular.
12. The layout structure of claim 11, wherein the size of the second electrode layer pattern is smaller than the size of the inter-electrode dielectric layer pattern, the size of the inter-electrode dielectric layer pattern is smaller than the size of the first electrode layer pattern, and a portion of the first electrode layer pattern is exposed by the inter-electrode dielectric layer pattern.
13. The layout structure according to claim 12, wherein the capacitor structure layout further includes a conductive plug pattern and a connection layer pattern, the connection layer pattern extending from the redundant layout area onto the exposed first electrode layer pattern, the conductive plug pattern being located between the connection layer pattern and the first electrode layer pattern.
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Application publication date: 20220111 |