KR20030050058A - Method for manufacturing of capacitor of semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a capacitor of a semiconductor device is provided to save the money and time for production by simplifying a fabricating process through a damascene process. CONSTITUTION: The first metal interconnection(103b) and a capacitor lower electrode(103a) are simultaneously and selectively formed on the first interlayer dielectric(102). The second interlayer dielectric(104) that has a plurality of the first via holes to expose the first metal interconnection and the lower electrode is formed. The first plug filling the first via hole is formed. The third interlayer dielectric(107) that has the second and third via holes to expose the first plug is formed. The first metal layer, the first insulation layer and the second metal layer are sequentially deposited on the resultant structure. A chemical mechanical polishing(CMP) process is performed to simultaneously form the upper electrode of the capacitor and the second metal interconnection. The fourth interlayer dielectric that has the fourth via hole to expose the second metal interconnection is formed. The third plug filling the fourth via hole is formed. The third metal interconnection(117) connected to the third plug is formed. The fifth interlayer dielectric(118) that has the fifth via hole(119) to expose the upper electrode and the third metal interconnection is formed. The fourth plug filling the fifth via hole is formed. The fourth metal interconnection(121) connected to the fourth plug is formed.

Description

METHODS FOR MANUFACTURING OF CAPACITOR OF SEMICONDUCTOR DEVICE

The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device that can simplify the process by using a damascene process.

Recently, the mixed signal used in the RF band is made of silicon base, and such a circuit has a basic insoluble-resistor, capacitor, and inductor. Used. In the case of the double capacitor, a high quality factor is required to be used in an analog circuit in an RF band, and in order to realize this, an electrode has almost no depletion and a low resistance metal plate as an electrode. Use is essential.

In line with this trend, the structure of capacitors is being changed from MIS (Metal Insulator Silicon) to MIM (Metal Insulator Metal). It is mainly used for.

However, since the MIM type analog capacitor must be implemented at the same time as other semiconductor devices, the MIM type analog capacitor must be electrically connected to the semiconductor device through a metal wiring, which is an interconnection line.

Hereinafter, a capacitor manufacturing method of a conventional semiconductor device will be described with reference to the accompanying drawings.

1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor having a conventional MIM structure.

As shown in FIG. 1A, after forming the first interlayer insulating film 12 on the semiconductor substrate 11, depositing a first metal layer on the first interlayer insulating film 12, and selectively patterning the plurality of metal layers. The first metal wiring 13 is formed.

Subsequently, after the second interlayer insulating layer 14 is formed on the entire surface including the first metal wiring 13, a plurality of first via holes 15 are formed to expose the first metal wiring 13. In addition, a second metal layer is deposited on the entire surface including the first via hole 15, and a first plug 16 filling the first via hole 15 is formed through a CMP and an entire surface etching process.

As illustrated in FIG. 1B, the third metal layer 17, the first insulating layer 18, and the fourth metal layer 19 are sequentially deposited on the resultant including the first plug 16, and then the fourth metal layer ( The first photoresist 20 is deposited on 19 and patterned using an exposure and development process. The upper metal layer 19a of the capacitor is defined by selectively etching the fourth metal layer 19 and the first insulating layer 18 using the patterned first photoresist 20 as a mask. Here, the first insulating film 18 is a dielectric film of the capacitor.

After removing the patterned first photoresist 20 as shown in FIG. 1C, the second photoresist 21 is deposited on the resultant including the upper electrode 19a, and then exposed and developed. Pattern.

Subsequently, the third metal layer 17 is selectively etched using the patterned second photoresist 21 as a mask to form a lower electrode 17a and a second metal wiring 17b of the capacitor.

Thus, a capacitor having a MIM structure is completed.

As shown in FIG. 1D, the patterned second photoresist 21 is removed, a third interlayer insulating layer 22 is deposited on the resultant, and then planarized by performing a chemical mechanical polishing (CMP) process.

Subsequently, a third photoresist 23 is deposited on the third interlayer insulating layer 22 and patterned by using an exposure and development process, and then the second patterned third photoresist 23 is used as a mask. The third interlayer insulating layer 22 is selectively etched to expose the metal wiring 17b, the upper electrode 19a, and the lower electrode 17a to form a plurality of second via holes 24.

As illustrated in FIG. 1E, the fifth metal layer is deposited on the resultant using CVD (Chemical Vapor Deposition), and then the entire surface of the second via hole 24 is filled by performing a CMP process or an entire surface etching using plasma. The second plug 25 is formed.

After the sixth metal layer 26 is deposited on the resultant product, the third metal wiring 26 is formed by using a photolithography process.

As shown in FIG. 1F, a fourth interlayer insulating layer 27 is formed on the resultant including the third metal wiring 26, and the photolithography process is used to selectively expose the third metal wiring 26. A plurality of third via holes 28 is formed.

Subsequently, after depositing the sixth metal layer on the resultant including the third via hole 28, the third plug 29 filling the third via hole 29 is embedded by performing a front surface etching using a CMP process or plasma. Form.

After depositing a seventh metal layer on the resultant product including the third plug 29, a fourth metal wiring 30 is formed by selectively patterning the seventh metal layer to be connected to the third plug 29 using a photolithography process. do.

However, the above-described conventional manufacturing method of the capacitor of the semiconductor device has the following problems.

Masks designed to form MIM capacitors are very expensive, and as the number of masks applied to the process increases, capacitor manufacturing costs rise proportionally.

In addition, the process is very complicated due to the increase in process time due to frequent movement between equipment.

The present invention has been made to solve the above problems and relates to a method for manufacturing a capacitor of a semiconductor device that can reduce the time and cost required for production by simplifying the process using a damascene process.

1A to 1F are cross-sectional views illustrating a method of manufacturing a capacitor having a conventional MIM structure.

2A through 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

101 semiconductor substrate 102 first interlayer insulating film

103a: lower electrode of capacitor 103b: first metal wiring

104: second interlayer insulating film 105: first via hole

106: first plug 107: third interlayer insulating film

108: first photoresist 109: second via hole

110: third via hole 111: third metal layer

112: first insulating film 113: fourth metal layer

114: fourth interlayer insulating film 115: fourth via hole

116: second plug 117: third metal wiring

118: fifth interlayer insulating film 119: fifth via hole

120: third plug 121: fourth metal wiring

According to another aspect of the present invention, there is provided a method of manufacturing a capacitor of a semiconductor device of the present invention, the method comprising: simultaneously forming a first metal wiring and a lower electrode of a capacitor on a first interlayer insulating film; Forming a second interlayer insulating film having a plurality of first via holes to expose the first layer; forming a first plug to fill the first via hole; and having a second via hole and a third via hole to expose the first plug. Forming a third interlayer insulating film, depositing a first metal layer, a first insulating film, and a second metal layer on top of the resultant, and then performing a CMP process to simultaneously form an upper electrode and a second metal wiring of the capacitor; Forming a fourth interlayer insulating layer having a fourth via hole to expose the second metal wiring; and a third plug to fill the fourth via hole. Forming a third metal wiring connected to the third plug, forming a fifth interlayer insulating film having a fifth via hole to expose the upper electrode and the third metal wiring; And forming a fourth plug filling the fifth via hole and forming a fourth metal wire connected to the fourth plug.

In addition, the size of the second via hole is the same size as that of the upper electrode, and is preferably larger than that of the third via hole.

The first insulating film is a dielectric film and preferably has a low dielectric constant.

Hereinafter, a capacitor manufacturing method of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, after forming the first interlayer insulating film 102 on the semiconductor substrate 101, depositing a first metal layer on the first interlayer insulating film 102, and then selectively patterning the capacitor The lower electrode 103a and the first metal wiring 103b are formed.

Subsequently, after the second interlayer insulating film 104 is formed on the entire surface including the lower electrode 103a and the first metal wiring 103b, the plurality of lower electrodes 103a and the first metal wiring 103b are exposed. First via holes 105 are formed. In this case, two via holes 105 are formed in the lower electrode 103a to connect the upper electrode of the capacitor to be formed in a subsequent process and the second metal wiring.

As shown in FIG. 2B, a second metal layer is deposited on the entire surface including the first via hole 105, and a first plug 106 is formed to fill the first via hole 105 through a CMP and an entire surface etching process. do.

After the third interlayer insulating film 107 is formed on the resultant, the first photoresist 108 is deposited, and then patterned using an exposure and development process.

Subsequently, second and third via holes 109 and 110 are simultaneously formed to expose the first plug 106 by using the patterned first photoresist 108 as a mask. In this case, the size of the second via hole 109 is the same size as that of the upper electrode to be formed in a subsequent process, and is larger than the third via hole 110.

After removing the patterned first photoresist 108 as shown in FIG. 2C, the third metal layer 111 is disposed on the third interlayer insulating layer 107 including the second and third via holes 109 and 110. ), The first insulating layer 112 and the fourth metal layer 113 are sequentially deposited. At this time, the first insulating film () is a dielectric film and has a low dielectric constant (Low-K) characteristics.

In this case, when the third metal layer 111, the first insulating layer 112, and the fourth metal layer 113 are deposited by the CVD method, deposition proceeds at a constant speed in all directions from the lower layer surface due to the deposition method characteristics.

Therefore, when deposited to a thickness similar to the size of the third via hole 110, the third via hole 110 is buried by the third metal layer 111 and the second via hole 109 is uniform from its bottom and sidewalls. Since the third metal layer 111 is deposited to have a thickness, the third metal layer 111 is not planarized, and thus, is formed in a p-shape.

As shown in FIG. 2D, a CMP process is performed on the resultant to form the upper electrode 111a of the capacitor, and at the same time, the second metal wiring 111b is formed.

Subsequently, after forming the fourth interlayer insulating layer 114 on the resultant, a plurality of fourth via holes 115 are formed to expose the second metal wiring 111b by using a photolithography process.

As shown in FIG. 2E, after depositing a fifth metal layer on the resultant product including the fourth via hole 115, the second via filling the fourth via hole 115 by performing surface etching using a CMP process or plasma. The plug 116 is formed.

After depositing a sixth metal layer on the resultant product including the second plug 116, the third metal wiring 117 is formed by selectively patterning the sixth metal layer to be connected to the second plug 116 using a photolithography process. do.

As shown in FIG. 2F, a fifth interlayer insulating layer 118 is formed on the resultant including the third metal wiring 117, and the fifth electrode is exposed to expose the upper electrode 111 a and the third metal wiring 117. The via hole 119 is formed.

Subsequently, after depositing a sixth metal layer on the resultant product including the fifth via hole 119, the third plug 120 filling the fifth via hole 119 is formed by performing a front surface etching using a CMP process or plasma. Form.

After depositing a seventh metal layer on the resultant including the third plug 120, the fourth metal wiring 121 is formed by selectively patterning the seventh metal layer to be connected to the third plug 120 using a photolithography process. do.

As described above, according to the method of manufacturing the capacitor of the semiconductor device of the present invention, since the mask process is reduced as compared with the related art, the manufacturing cost is reduced and the process can be simplified.

Therefore, more products can be produced in mass production.

Claims (3)

Optionally simultaneously forming a first metal interconnection and a lower electrode of the capacitor on the first interlayer insulating film; Forming a second interlayer insulating film having a plurality of first via holes to expose the first metal wiring and the lower electrode; Forming a first plug filling the first via hole, and forming a third interlayer insulating film having a second via hole and a third via hole to expose the first plug; Depositing a first metal layer, a first insulating film, and a second metal layer in order on the resultant, and then performing a CMP process to simultaneously form an upper electrode and a second metal wiring of the capacitor; Forming a fourth interlayer insulating film having a fourth via hole to expose the second metal wiring; Forming a third plug to fill the fourth via hole, and forming a third metal wiring connected to the third plug; Forming a fifth interlayer insulating film having a fifth via hole to expose the upper electrode and the third metal wiring; And forming a fourth plug filling the fifth via hole, and forming a fourth metal wiring connected to the fourth plug. The method of claim 1, The second via hole has the same size as that of the upper electrode and is larger than the third via hole. The method of claim 1, And the first insulating film is a dielectric film and has a low dielectric constant.