KR100390892B1 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- KR100390892B1 KR100390892B1 KR1019960049846A KR19960049846A KR100390892B1 KR 100390892 B1 KR100390892 B1 KR 100390892B1 KR 1019960049846 A KR1019960049846 A KR 1019960049846A KR 19960049846 A KR19960049846 A KR 19960049846A KR 100390892 B1 KR100390892 B1 KR 100390892B1
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- planarization
- film
- photoresist
- insulating film
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 20
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000005498 polishing Methods 0.000 claims 1
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 12
- 239000002184 metal Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 PECVD(Plasma Enhanced CVD) 산화막을 이용하여 소자의 평탄화를 이룩할 수 있는 반도체 소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device capable of achieving planarization of a device using a PECVD (Plasma Enhanced CVD) oxide film.
도 1A 내지 도 1C는 BPSG막을 이용한 종래의 반도체 소자의 평탄화 방법을 설명하기 위한 공정 단면도이다.1A to 1C are process cross-sectional views for explaining a conventional method of planarizing a semiconductor device using a BPSG film.
먼저, 도 1A에 도시된 바와 같이, 반도체 기판(1) 상에 하부층 패턴(2), 예컨대 필드 산화막 또는 도전층 등을 형성하고, 그 상부에 평탄화막으로서 BPSG막(3)을 증착한다.First, as shown in FIG. 1A, a lower layer pattern 2, for example, a field oxide film or a conductive layer is formed on a semiconductor substrate 1, and a BPSG film 3 is deposited thereon as a planarizing film.
도 1B에 도시된 바와 같이, 850℃의 고온의 노(furnace) 공정을 통하여 BPSG막(3)을 플로우(flow) 시킴으로써 하부층 패턴의 평탄화를 이룩한다.As shown in FIG. 1B, the BPSG film 3 is flowed through a furnace process at a high temperature of 850 ° C. to achieve planarization of the lower layer pattern.
도 1C에 도시된 바와 같이, 포토리소그라피 및 식각 공정을 통하여 반도체 기판(1)과 전기적 연결을 위한 콘택홀(도시되지 않음)을 형성하고, 콘택홀을 통하여 반도체 기판(1)과 접촉하는 금속층 패턴(4)을 형성한다.As shown in FIG. 1C, a contact hole (not shown) for electrical connection with the semiconductor substrate 1 is formed through a photolithography and etching process, and a metal layer pattern (4).
그런데, 상기한 BPSG막을 이용한 종래의 평탄화 방법은 고온의 플로우 공정에 의해 다음과 같은 문제가 있게 된다.However, the conventional flattening method using the BPSG film has the following problems due to the high-temperature flow process.
즉, 도면에 도시되지는 않았지만 기가 비트 디램(Giga bit DRAM)의 캐패시터 제조 공정시 매우 유망한 유전물질로서 Ta2O5막이 사용되고 있다. 그러나, 상기 Ta2O5막은 매우 높은 유전 상수와 우수한 스텝 커버리지 특성을 갖는 반면, 상기한 BPSG막의 플로우 공정과 같은 고온의 공정에서는 누설 전류가 매우 크게 증가하는 단점이 있는 바, 상기 Ta2O5의 누설 전류를 감소시키려면 캐패시터 제조 공정후, 500℃ 이하의 공정이 진행되어야 한다.That is, although not shown, a Ta 2 O 5 film is used as a very promising dielectric material in a process of manufacturing a capacitor of a gigabit DRAM (Giga bit DRAM). However, the Ta 2 O 5 film is very high dielectric constant and excellent while having a step coverage characteristics, in the high-temperature process such as the one BPSG film flow process bars with a drawback that the leakage current is very greatly increased, the Ta 2 O 5 The process of 500 ° C or lower must be performed after the capacitor manufacturing process.
따라서, 본 발명은 상기한 문제점을 감안하여 창출된 것으로서, 고온의 플로우를 요하는 BPSG막 대신에 저온에서 진행되는 PECVD 산화막을 이용하여 소자의 평탄화를 이룩할 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of fabricating a semiconductor device that can achieve planarization of a device using a PECVD oxide film that proceeds at a low temperature instead of a BPSG film requiring high- There is a purpose.
도 1A 내지 도 1C는 BPSG막을 이용한 종래의 반도체 소자의 평탄화 바법을 설명하기 위한 공정 단면도.1A to 1C are process cross-sectional views for explaining a conventional flattening method of a semiconductor device using a BPSG film.
도 2A 내지 도 2E는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.FIGS. 2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명DESCRIPTION OF THE REFERENCE NUMERALS
11 : 반도체 기판 12 : 하부층 패턴11: semiconductor substrate 12: lower layer pattern
13 : 평탄화막 16 : 금속층 패턴13: planarization film 16: metal layer pattern
상기 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조방법은 하부층 패턴이 형성된 반도체 기판 상부에 제 1 평탄화절연막을 형성하는 단계; 상기 제 1 평탄화 절연막 상에 제 1 감광막을 도포하는 단계; 상기 제 1 평탄화절연막이 노출되도록 상기 제 1 감광막 및 상기 제 1 평탄화절연막을 에치백하여 1차 평탄화하는 단계; 상기 제 1 평탄화절연막 상에 잔류하는 상기 제 1 감광막을 제거하는 단계; 상기 제 1 평탄화절연막 상에 제 2 평탄화절연막을 형성하는 단계; 상기 제 2 평탄화절연막 상에 제 2 감광막을 도포하는 단계; 상기 제 2 평탄화절연막이 노출되도록 상기 제 2 감광막 및 상기 제 2 평탄화절연막을 에치백하여 2차 평탄화하는 단계; 및, 상기 제 2 평탄화절연막 상에 잔류하는 상기 제 2 감광막을 제거하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, including: forming a first planarization insulating layer on a semiconductor substrate having a lower layer pattern; Applying a first photosensitive film on the first planarization insulating film; Etching back the first photoresist layer and the first planarization insulating layer to form a first planarization layer so that the first planarization layer is exposed; Removing the first photoresist film remaining on the first planarization insulating film; Forming a second planarization insulating film on the first planarization insulating film; Applying a second photosensitive film on the second planarization insulating film; Etching back the second photoresist layer and the second planarization layer to planarize the second planarization layer to expose the second planarization layer; And removing the second photoresist film remaining on the second planarization insulating film.
또한, 상기 제 1 및 제 2 평탄화막은 PECVD 산화막인 것을 특징으로 한다.In addition, the first and second planarization films are PECVD oxide films.
상기 구성으로 된 본 발명에 의하면, 평탄화막으로서 BPSG막 대신에 PECVD 산화막의 형성 후 식각 공정을 통하여 소자의 평탄화를 이룩할 수 있게 된다.According to the present invention having the above structure, it is possible to achieve planarization of the device through the etching process after forming the PECVD oxide film instead of the BPSG film as the planarizing film.
[실시예][Example]
이하, 첨부된 도면을 참조하여 본 발명의 실시예를 설명한다.Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
도 2A 내지 도 2E는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 순차적인 공정 단면도이다.2A to 2E are sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.
먼저, 도 2A에 도시된 바와 같이, 반도체 기판(11) 상에 하부층 패턴(12), 예컨대 도전층을 형성한다.First, as shown in FIG. 2A, a lower layer pattern 12, for example, a conductive layer, is formed on a semiconductor substrate 11.
도 2B에 도시된 바와 같이, 하부층 패턴(12) 및 반도체 기판(11) 상부에 평탄화를 이루기 위한 제 1 평탄화막(13-1)으로서 PECVD 산화막을 450 내지 500℃의 온도에서 형성한다. 이때, 반도체 기판(11)과 하부층 패턴(12)의 통상적인 토플로지가 0.8 내지 2㎛ 정도임을 감안하여, 제 1 평탄화막(13-1)은 10,000 내지 20,000Å의 두께로 형성한다. 그런 다음, 제 1 평탄화막(13-1) 상부에 제 1 감광막(14)을 도포한다.As shown in FIG. 2B, a PECVD oxide film is formed as a first planarization film 13-1 for planarization on the lower layer pattern 12 and the semiconductor substrate 11 at a temperature of 450 to 500.degree. The first planarization layer 13-1 is formed to have a thickness of 10,000 to 20,000 ANGSTROM considering that the typical topology of the semiconductor substrate 11 and the lower layer pattern 12 is about 0.8 to 2 mu m. Then, the first photosensitive film 14 is coated on the first planarization film 13-1.
도 2C에 도시된 바와 같이, 제 1 감광막(14)에 의한 제 1 평탄화막(13-1)의 에치백을 실시하고, 제 1 감광막(14)을 제거한다. 이때, 상기 에치백은 화학적 기계적 연마법을 이용한다. 이어서, 에치백된 제 1 평탄화막(13-1) 상부에 제 1 평탄화막(13-1)과 마찬가지로 450 내지 500℃의 온도에서 PECVD 산화막을 제 2 평탄화막(13-2)으로 형성한다.As shown in Fig. 2C, the first planarizing film 13-1 is etched back by the first photoresist film 14, and the first photoresist film 14 is removed. At this time, the etch-back uses chemical mechanical coupling. Next, a PECVD oxide film is formed as a second planarization film 13-2 on the first planarization film 13-1, which is etched back, at a temperature of 450 to 500 ° C in the same manner as the first planarization film 13-1.
이때, 제 2 평탄화막(13-2)은 감광막(14)에 의해 에치백된 제 1 평탄화막(13-1)에 의해 어느 정도 평탄화가 이루어졌으므로, 제 1 평탄화막(13-1) 보다 얇은 5,000 내지 10,000Å의 두께로 형성한다. 그런 다음, 제 2 평탄화막(13-2) 상부에 제 2 감광막(15)을 도포한다.Since the second flattening film 13-2 is planarized to some extent by the first flattening film 13-1 etched back by the photoresist film 14, the second flattening film 13-2 is thinner than the first flattening film 13-1 To a thickness of 5,000 to 10,000 ANGSTROM. Then, the second photosensitive film 15 is coated on the second planarizing film 13-2.
도 2D에 도시된 바와 같이, 제 2 감광막(15)에 의한 제 2 평탄화막(13-2)의 에치백을 실시하고, 제 2 감광막(15)을 제거하여 하부층 패턴의 평탄화를 이룩한다. 이때, 상기 에치백 공정은 금속 유전율을 고려하여 하부층 패턴(12) 상부의 제 1 및 제 2 평탄화막(13)의 최종 두께(a)가 5,000 내지 10,000Å이 되도록 실시한다.2D, the second planarizing film 13-2 is etched back by the second photoresist film 15, and the second photoresist film 15 is removed to planarize the lower layer pattern. At this time, the etch back process is performed so that the final thickness (a) of the first and second planarization films 13 on the lower layer pattern 12 is 5,000 to 10,000 ANGSTROM considering the metal permittivity.
도 2E에 도시된 바와 같이, 포토리소그라피 및 식각 공정을 통하여 반도체 기판(11)과 전기적 상호 연결을 위한 콘택홀(도시되지 않음)을 형성하고, 콘택홀을 통하여 반도체 기판(11)과 접촉하는 금속층 패턴(16)을 형성한다.As shown in FIG. 2E, a contact hole (not shown) for electrical interconnection with the semiconductor substrate 11 is formed through a photolithography and etching process, and a metal layer Pattern 16 is formed.
상기 실시예에 의하면, 고온의 플로우를 요하는 BPSG막 대신에 저온에서 진행되는 PECVD 산화막을 평탄화막으로 형성하고, 감광막을 이용한 에치백을 통하여 하부층 패턴의 평탄화를 이룩할 수 있게 된다.According to this embodiment, instead of the BPSG film requiring a high-temperature flow, a PECVD oxide film which proceeds at a low temperature is formed into a flattening film, and the lower layer pattern can be planarized through the etch-back using the photoresist film.
이에 따라, BPSG막의 사용으로 인해 발생되는 디펙트를 방지할 수 있게 됨으로써 제조 수율을 향상시킬 수 있을 뿐만 아니라, BPSG막의 사용이 억제됨에 따라 공정 진행의 여유도를 증대시킬 수 있게 된다.Thus, it is possible to prevent the defect caused by the use of the BPSG film, thereby improving the production yield and increasing the margins of the process as the use of the BPSG film is suppressed.
또한, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 요지를 벗어나지 않는 범위내에서 다양하게 변형시켜 실시할 수 있다.The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the technical gist of the present invention.
이상 설명한 바와 같이 본 발명에 의하면, PECVD 산화막을 이용하여 소자의 평탄화를 이룩할 수 있는 반도체 소자의 제조방법을 실현할 수 있게 된다.As described above, according to the present invention, it is possible to realize a method of manufacturing a semiconductor device that can achieve planarization of a device using a PECVD oxide film.
Claims (8)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960049846A KR100390892B1 (en) | 1996-10-29 | 1996-10-29 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960049846A KR100390892B1 (en) | 1996-10-29 | 1996-10-29 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19980030452A KR19980030452A (en) | 1998-07-25 |
| KR100390892B1 true KR100390892B1 (en) | 2003-10-04 |
Family
ID=37421878
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960049846A KR100390892B1 (en) | 1996-10-29 | 1996-10-29 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100390892B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05235184A (en) * | 1992-02-26 | 1993-09-10 | Nec Corp | Manufacturing method of multilayer wiring structural body of semiconducot rdevice |
| US5516729A (en) * | 1994-06-03 | 1996-05-14 | Advanced Micro Devices, Inc. | Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate |
| KR960015750A (en) * | 1994-10-28 | 1996-05-22 | 김주용 | Semiconductor device manufacturing method |
| KR100250745B1 (en) * | 1993-12-30 | 2000-06-01 | 김영환 | Method of forming inter metal oxide of semiconductor device |
-
1996
- 1996-10-29 KR KR1019960049846A patent/KR100390892B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05235184A (en) * | 1992-02-26 | 1993-09-10 | Nec Corp | Manufacturing method of multilayer wiring structural body of semiconducot rdevice |
| KR100250745B1 (en) * | 1993-12-30 | 2000-06-01 | 김영환 | Method of forming inter metal oxide of semiconductor device |
| US5516729A (en) * | 1994-06-03 | 1996-05-14 | Advanced Micro Devices, Inc. | Method for planarizing a semiconductor topography using a spin-on glass material with a variable chemical-mechanical polish rate |
| KR960015750A (en) * | 1994-10-28 | 1996-05-22 | 김주용 | Semiconductor device manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980030452A (en) | 1998-07-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR0179292B1 (en) | Method for forming multi-level interconnections | |
| KR0179289B1 (en) | Forming method of metal wiring | |
| US5966632A (en) | Method of forming borderless metal to contact structure | |
| US7211495B2 (en) | Semiconductor devices having a capacitor and methods of manufacturing the same | |
| KR100390892B1 (en) | Method for manufacturing semiconductor device | |
| KR100367695B1 (en) | Method for forming via contact in semiconductor device | |
| US6153936A (en) | Method for forming via hole and semiconductor structure formed thereby | |
| KR20020034468A (en) | Method of manufacturing a semiconductor device | |
| KR100365936B1 (en) | Method for forming via contact in semiconductor device | |
| KR100252873B1 (en) | Multilayer metal line of semiconductor device and method for forming the same | |
| KR100299332B1 (en) | Method for manufacturing intermetal dielectric layer of semiconductor devices | |
| KR100871370B1 (en) | Method for forming metal line of semiconductor device | |
| KR100414951B1 (en) | Method for forming plug of semiconductor device | |
| KR20010063260A (en) | Method of manufacturing semiconductor device | |
| KR100311499B1 (en) | Method for manufacturing capacitor in semiconductor device | |
| KR20010094721A (en) | method for manufacturing of semiconductor device | |
| KR20040010932A (en) | Method for forming the capacitor of Metal-Insulator-Metal structure | |
| KR100269662B1 (en) | Method for manufacturing conductor plug of semiconductor device | |
| KR100265828B1 (en) | A method for fabricating semiconductor device | |
| KR100359786B1 (en) | Method for Fabricating of Semiconductor Device | |
| KR20000044854A (en) | Method for forming interlayer dielectric of semiconductor device | |
| KR20030056914A (en) | Method for manufacturing capacitor of semiconductor device | |
| KR20030001642A (en) | Method for forming the contact plug of semiconductor device | |
| KR20020025317A (en) | Method for forming metal insulator metal capacitor | |
| KR960026329A (en) | Planarization method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20110526 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |